gem5::VegaISA::InFmt_SOP2 Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	SSRC0: 8
unsigned int	SSRC1: 8
unsigned int	SDST: 7
unsigned int	OP: 7
unsigned int	ENCODING: 2

Detailed Description

Definition at line 1830 of file gpu_decoder.hh.

Member Data Documentation

ENCODING

unsigned int gem5::VegaISA::InFmt_SOP2::ENCODING

Definition at line 1835 of file gpu_decoder.hh.

OP

unsigned int gem5::VegaISA::InFmt_SOP2::OP

Definition at line 1834 of file gpu_decoder.hh.

SDST

unsigned int gem5::VegaISA::InFmt_SOP2::SDST

Definition at line 1833 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOP2__S_ABSDIFF_I32::execute(), gem5::VegaISA::Inst_SOP2__S_ADD_I32::execute(), gem5::VegaISA::Inst_SOP2__S_ADD_U32::execute(), gem5::VegaISA::Inst_SOP2__S_ADDC_U32::execute(), gem5::VegaISA::Inst_SOP2__S_AND_B32::execute(), gem5::VegaISA::Inst_SOP2__S_AND_B64::execute(), gem5::VegaISA::Inst_SOP2__S_ANDN2_B32::execute(), gem5::VegaISA::Inst_SOP2__S_ANDN2_B64::execute(), gem5::VegaISA::Inst_SOP2__S_ASHR_I32::execute(), gem5::VegaISA::Inst_SOP2__S_ASHR_I64::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_I32::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_I64::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_U32::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_U64::execute(), gem5::VegaISA::Inst_SOP2__S_BFM_B32::execute(), gem5::VegaISA::Inst_SOP2__S_BFM_B64::execute(), gem5::VegaISA::Inst_SOP2__S_CSELECT_B32::execute(), gem5::VegaISA::Inst_SOP2__S_CSELECT_B64::execute(), gem5::VegaISA::Inst_SOP2__S_LSHL_B32::execute(), gem5::VegaISA::Inst_SOP2__S_LSHL_B64::execute(), gem5::VegaISA::Inst_SOP2__S_LSHR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_LSHR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_MAX_I32::execute(), gem5::VegaISA::Inst_SOP2__S_MAX_U32::execute(), gem5::VegaISA::Inst_SOP2__S_MIN_I32::execute(), gem5::VegaISA::Inst_SOP2__S_MIN_U32::execute(), gem5::VegaISA::Inst_SOP2__S_MUL_HI_I32::execute(), gem5::VegaISA::Inst_SOP2__S_MUL_HI_U32::execute(), gem5::VegaISA::Inst_SOP2__S_MUL_I32::execute(), gem5::VegaISA::Inst_SOP2__S_NAND_B32::execute(), gem5::VegaISA::Inst_SOP2__S_NAND_B64::execute(), gem5::VegaISA::Inst_SOP2__S_NOR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_NOR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_OR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_OR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_ORN2_B32::execute(), gem5::VegaISA::Inst_SOP2__S_ORN2_B64::execute(), gem5::VegaISA::Inst_SOP2__S_SUB_I32::execute(), gem5::VegaISA::Inst_SOP2__S_SUB_U32::execute(), gem5::VegaISA::Inst_SOP2__S_SUBB_U32::execute(), gem5::VegaISA::Inst_SOP2__S_XNOR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_XNOR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_XOR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_XOR_B64::execute(), gem5::VegaISA::Inst_SOP2::generateDisassembly(), and gem5::VegaISA::Inst_SOP2::initOperandInfo().

SSRC0

unsigned int gem5::VegaISA::InFmt_SOP2::SSRC0

Definition at line 1831 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOP2__S_ABSDIFF_I32::execute(), gem5::VegaISA::Inst_SOP2__S_ADD_I32::execute(), gem5::VegaISA::Inst_SOP2__S_ADD_U32::execute(), gem5::VegaISA::Inst_SOP2__S_ADDC_U32::execute(), gem5::VegaISA::Inst_SOP2__S_AND_B32::execute(), gem5::VegaISA::Inst_SOP2__S_AND_B64::execute(), gem5::VegaISA::Inst_SOP2__S_ANDN2_B32::execute(), gem5::VegaISA::Inst_SOP2__S_ANDN2_B64::execute(), gem5::VegaISA::Inst_SOP2__S_ASHR_I32::execute(), gem5::VegaISA::Inst_SOP2__S_ASHR_I64::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_I32::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_I64::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_U32::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_U64::execute(), gem5::VegaISA::Inst_SOP2__S_BFM_B32::execute(), gem5::VegaISA::Inst_SOP2__S_BFM_B64::execute(), gem5::VegaISA::Inst_SOP2__S_CSELECT_B32::execute(), gem5::VegaISA::Inst_SOP2__S_CSELECT_B64::execute(), gem5::VegaISA::Inst_SOP2__S_LSHL_B32::execute(), gem5::VegaISA::Inst_SOP2__S_LSHL_B64::execute(), gem5::VegaISA::Inst_SOP2__S_LSHR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_LSHR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_MAX_I32::execute(), gem5::VegaISA::Inst_SOP2__S_MAX_U32::execute(), gem5::VegaISA::Inst_SOP2__S_MIN_I32::execute(), gem5::VegaISA::Inst_SOP2__S_MIN_U32::execute(), gem5::VegaISA::Inst_SOP2__S_MUL_HI_I32::execute(), gem5::VegaISA::Inst_SOP2__S_MUL_HI_U32::execute(), gem5::VegaISA::Inst_SOP2__S_MUL_I32::execute(), gem5::VegaISA::Inst_SOP2__S_NAND_B32::execute(), gem5::VegaISA::Inst_SOP2__S_NAND_B64::execute(), gem5::VegaISA::Inst_SOP2__S_NOR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_NOR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_OR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_OR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_ORN2_B32::execute(), gem5::VegaISA::Inst_SOP2__S_ORN2_B64::execute(), gem5::VegaISA::Inst_SOP2__S_SUB_I32::execute(), gem5::VegaISA::Inst_SOP2__S_SUB_U32::execute(), gem5::VegaISA::Inst_SOP2__S_SUBB_U32::execute(), gem5::VegaISA::Inst_SOP2__S_XNOR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_XNOR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_XOR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_XOR_B64::execute(), gem5::VegaISA::Inst_SOP2::generateDisassembly(), gem5::VegaISA::Inst_SOP2::hasSecondDword(), and gem5::VegaISA::Inst_SOP2::initOperandInfo().

SSRC1

unsigned int gem5::VegaISA::InFmt_SOP2::SSRC1

Definition at line 1832 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOP2__S_ABSDIFF_I32::execute(), gem5::VegaISA::Inst_SOP2__S_ADD_I32::execute(), gem5::VegaISA::Inst_SOP2__S_ADD_U32::execute(), gem5::VegaISA::Inst_SOP2__S_ADDC_U32::execute(), gem5::VegaISA::Inst_SOP2__S_AND_B32::execute(), gem5::VegaISA::Inst_SOP2__S_AND_B64::execute(), gem5::VegaISA::Inst_SOP2__S_ANDN2_B32::execute(), gem5::VegaISA::Inst_SOP2__S_ANDN2_B64::execute(), gem5::VegaISA::Inst_SOP2__S_ASHR_I32::execute(), gem5::VegaISA::Inst_SOP2__S_ASHR_I64::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_I32::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_I64::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_U32::execute(), gem5::VegaISA::Inst_SOP2__S_BFE_U64::execute(), gem5::VegaISA::Inst_SOP2__S_BFM_B32::execute(), gem5::VegaISA::Inst_SOP2__S_BFM_B64::execute(), gem5::VegaISA::Inst_SOP2__S_CSELECT_B32::execute(), gem5::VegaISA::Inst_SOP2__S_CSELECT_B64::execute(), gem5::VegaISA::Inst_SOP2__S_LSHL_B32::execute(), gem5::VegaISA::Inst_SOP2__S_LSHL_B64::execute(), gem5::VegaISA::Inst_SOP2__S_LSHR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_LSHR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_MAX_I32::execute(), gem5::VegaISA::Inst_SOP2__S_MAX_U32::execute(), gem5::VegaISA::Inst_SOP2__S_MIN_I32::execute(), gem5::VegaISA::Inst_SOP2__S_MIN_U32::execute(), gem5::VegaISA::Inst_SOP2__S_MUL_HI_I32::execute(), gem5::VegaISA::Inst_SOP2__S_MUL_HI_U32::execute(), gem5::VegaISA::Inst_SOP2__S_MUL_I32::execute(), gem5::VegaISA::Inst_SOP2__S_NAND_B32::execute(), gem5::VegaISA::Inst_SOP2__S_NAND_B64::execute(), gem5::VegaISA::Inst_SOP2__S_NOR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_NOR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_OR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_OR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_ORN2_B32::execute(), gem5::VegaISA::Inst_SOP2__S_ORN2_B64::execute(), gem5::VegaISA::Inst_SOP2__S_SUB_I32::execute(), gem5::VegaISA::Inst_SOP2__S_SUB_U32::execute(), gem5::VegaISA::Inst_SOP2__S_SUBB_U32::execute(), gem5::VegaISA::Inst_SOP2__S_XNOR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_XNOR_B64::execute(), gem5::VegaISA::Inst_SOP2__S_XOR_B32::execute(), gem5::VegaISA::Inst_SOP2__S_XOR_B64::execute(), gem5::VegaISA::Inst_SOP2::generateDisassembly(), gem5::VegaISA::Inst_SOP2::hasSecondDword(), and gem5::VegaISA::Inst_SOP2::initOperandInfo().

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The documentation for this struct was generated from the following file:

• arch/amdgpu/vega/gpu_decoder.hh