gem5::VegaISA::InFmt_SOPP Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	SIMM16: 16
unsigned int	OP: 7
unsigned int	ENCODING: 9

Detailed Description

Definition at line 1852 of file gpu_decoder.hh.

Member Data Documentation

ENCODING

unsigned int gem5::VegaISA::InFmt_SOPP::ENCODING

Definition at line 1855 of file gpu_decoder.hh.

OP

unsigned int gem5::VegaISA::InFmt_SOPP::OP

Definition at line 1854 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOPP::generateDisassembly(), and gem5::VegaISA::Decoder::subDecode_OP_SOPP().

SIMM16

unsigned int gem5::VegaISA::InFmt_SOPP::SIMM16

Definition at line 1853 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOPP__S_BRANCH::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECNZ::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECZ::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC0::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC1::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCNZ::execute(), gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCZ::execute(), gem5::VegaISA::Inst_SOPP__S_SETPRIO::execute(), gem5::VegaISA::Inst_SOPP__S_SLEEP::execute(), gem5::VegaISA::Inst_SOPP__S_WAITCNT::execute(), gem5::VegaISA::Inst_SOPP::generateDisassembly(), and gem5::VegaISA::Inst_SOPP::initOperandInfo().

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The documentation for this struct was generated from the following file:

• arch/amdgpu/vega/gpu_decoder.hh