gem5  v21.1.0.2
tarmac_base.hh
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37 
49 #ifndef __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
50 #define __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
51 
52 #include "base/trace.hh"
53 #include "base/types.hh"
54 #include "cpu/static_inst.hh"
55 #include "sim/insttracer.hh"
56 
57 namespace gem5
58 {
59 
60 class ThreadContext;
61 
62 namespace Trace {
63 
65 {
66  public:
69  {
74  };
75 
79 
82 
84  struct InstEntry
85  {
86  InstEntry() = default;
90  bool predicate);
91 
92  bool taken;
95  std::string disassemble;
98  };
99 
101  struct RegEntry
102  {
104  {
105  Lo = 0,
106  Hi = 1,
107  // Max = (max SVE vector length) 2048b / 64 = 32
108  Max = 32
109  };
110 
111  RegEntry() = default;
113 
118  };
119 
121  struct MemEntry
122  {
123  MemEntry() = default;
124  MemEntry(uint8_t _size, Addr _addr, uint64_t _data);
125 
126  uint8_t size;
128  uint64_t data;
129  };
130 
131  public:
132  TarmacBaseRecord(Tick _when, ThreadContext *_thread,
133  const StaticInstPtr _staticInst, ArmISA::PCState _pc,
134  const StaticInstPtr _macroStaticInst = NULL);
135 
136  virtual void dump() = 0;
137 
146 };
147 
148 
149 } // namespace Trace
150 } // namespace gem5
151 
152 #endif // __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
gem5::Trace::TarmacBaseRecord::TARMAC_INST
@ TARMAC_INST
Definition: tarmac_base.hh:70
gem5::Trace::TarmacBaseRecord::REG_S
@ REG_S
Definition: tarmac_base.hh:81
gem5::Trace::TarmacBaseRecord::TARMAC_MEM
@ TARMAC_MEM
Definition: tarmac_base.hh:72
gem5::Trace::TarmacBaseRecord::MemEntry::size
uint8_t size
Definition: tarmac_base.hh:126
insttracer.hh
gem5::Trace::TarmacBaseRecord
Definition: tarmac_base.hh:64
gem5::Trace::TarmacBaseRecord::InstEntry::opcode
ArmISA::MachInst opcode
Definition: tarmac_base.hh:94
gem5::Trace::InstRecord::thread
ThreadContext * thread
Definition: insttracer.hh:65
gem5::Trace::TarmacBaseRecord::dump
virtual void dump()=0
gem5::Trace::TarmacBaseRecord::REG_Z
@ REG_Z
Definition: tarmac_base.hh:81
std::vector< uint64_t >
gem5::Trace::TarmacBaseRecord::ISET_A64
@ ISET_A64
Definition: tarmac_base.hh:77
gem5::Trace::TarmacBaseRecord::RegEntry::Lo
@ Lo
Definition: tarmac_base.hh:105
gem5::Trace::TarmacBaseRecord::RegEntry::Max
@ Max
Definition: tarmac_base.hh:108
gem5::Trace::TarmacBaseRecord::InstEntry::isetstate
ISetState isetstate
Definition: tarmac_base.hh:96
gem5::RefCountingPtr< StaticInst >
gem5::Trace::TarmacBaseRecord::ISET_ARM
@ ISET_ARM
Definition: tarmac_base.hh:77
gem5::Trace::TarmacBaseRecord::MemEntry::addr
Addr addr
Definition: tarmac_base.hh:127
gem5::Trace::TarmacBaseRecord::RegEntry::values
std::vector< uint64_t > values
Definition: tarmac_base.hh:117
gem5::Trace::TarmacBaseRecord::TARMAC_REG
@ TARMAC_REG
Definition: tarmac_base.hh:71
gem5::Trace::TarmacBaseRecord::ISetState
ISetState
ARM instruction set state.
Definition: tarmac_base.hh:77
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Trace::TarmacBaseRecord::InstEntry
TARMAC instruction trace record.
Definition: tarmac_base.hh:84
gem5::Trace::TarmacBaseRecord::REG_Q
@ REG_Q
Definition: tarmac_base.hh:81
gem5::Trace::TarmacBaseRecord::ISET_THUMB
@ ISET_THUMB
Definition: tarmac_base.hh:77
gem5::Trace::TarmacBaseRecord::InstEntry::InstEntry
InstEntry()=default
gem5::Trace::InstRecord::pc
TheISA::PCState pc
Definition: insttracer.hh:69
gem5::Trace::InstRecord::staticInst
StaticInstPtr staticInst
Definition: insttracer.hh:68
gem5::ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:55
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Trace::TarmacBaseRecord::REG_MISC
@ REG_MISC
Definition: tarmac_base.hh:81
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Trace::TarmacBaseRecord::TarmacBaseRecord
TarmacBaseRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, ArmISA::PCState _pc, const StaticInstPtr _macroStaticInst=NULL)
Definition: tarmac_base.cc:55
gem5::Trace::TarmacBaseRecord::RegEntry::RegElement
RegElement
Definition: tarmac_base.hh:103
gem5::Trace::TarmacBaseRecord::RegEntry::isetstate
ISetState isetstate
Definition: tarmac_base.hh:116
gem5::Trace::TarmacBaseRecord::MemEntry::data
uint64_t data
Definition: tarmac_base.hh:128
gem5::Trace::TarmacBaseRecord::InstEntry::mode
ArmISA::OperatingMode mode
Definition: tarmac_base.hh:97
gem5::Trace::TarmacBaseRecord::REG_P
@ REG_P
Definition: tarmac_base.hh:81
gem5::Trace::TarmacBaseRecord::REG_D
@ REG_D
Definition: tarmac_base.hh:81
gem5::Trace::TarmacBaseRecord::RegEntry
TARMAC register trace record.
Definition: tarmac_base.hh:101
gem5::Trace::TarmacBaseRecord::REG_R
@ REG_R
Definition: tarmac_base.hh:81
static_inst.hh
gem5::Trace::TarmacBaseRecord::REG_X
@ REG_X
Definition: tarmac_base.hh:81
gem5::Trace::TarmacBaseRecord::TarmacRecordType
TarmacRecordType
TARMAC trace record type.
Definition: tarmac_base.hh:68
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Trace::TarmacBaseRecord::MemEntry::MemEntry
MemEntry()=default
gem5::Trace::TarmacBaseRecord::ISET_UNSUPPORTED
@ ISET_UNSUPPORTED
Definition: tarmac_base.hh:78
gem5::Trace::TarmacBaseRecord::RegEntry::Hi
@ Hi
Definition: tarmac_base.hh:106
gem5::Trace::TarmacBaseRecord::InstEntry::taken
bool taken
Definition: tarmac_base.hh:92
gem5::Trace::InstRecord::predicate
bool predicate
is the predicate for execution this inst true or false (not execed)?
Definition: insttracer.hh:148
types.hh
gem5::Trace::TarmacBaseRecord::pcToISetState
static ISetState pcToISetState(ArmISA::PCState pc)
Returns the Instruction Set State according to the current PCState.
Definition: tarmac_base.cc:103
gem5::Trace::TarmacBaseRecord::MemEntry
TARMAC memory access trace record (stores only).
Definition: tarmac_base.hh:121
gem5::Trace::TarmacBaseRecord::InstEntry::disassemble
std::string disassemble
Definition: tarmac_base.hh:95
trace.hh
gem5::Trace::TarmacBaseRecord::RegType
RegType
ARM register type.
Definition: tarmac_base.hh:81
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::Trace::TarmacBaseRecord::InstEntry::addr
Addr addr
Definition: tarmac_base.hh:93
gem5::Trace::TarmacBaseRecord::TARMAC_UNSUPPORTED
@ TARMAC_UNSUPPORTED
Definition: tarmac_base.hh:73
gem5::Trace::TarmacBaseRecord::RegEntry::type
RegType type
Definition: tarmac_base.hh:114
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Trace::TarmacBaseRecord::RegEntry::index
RegIndex index
Definition: tarmac_base.hh:115
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::Trace::TarmacBaseRecord::RegEntry::RegEntry
RegEntry()=default

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