insttracer.hh

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 * All rights reserved.
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 * met: redistributions of source code must retain the above copyright
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#ifndef __INSTRECORD_HH__
#define __INSTRECORD_HH__
 
#include <memory>
 
#include "arch/generic/pcstate.hh"
#include "base/types.hh"
#include "cpu/inst_res.hh"
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
#include "params/InstTracer.hh"
#include "sim/sim_object.hh"
 
namespace gem5
{
 
class ThreadContext;
 
namespace trace {
 
class InstRecord
{
  protected:
    Tick when;
 
    // The following fields are initialized by the constructor and
    // thus guaranteed to be valid.
    ThreadContext *thread;
    // need to make this ref-counted so it doesn't go away before we
    // dump the record
    StaticInstPtr staticInst;
    std::unique_ptr<PCStateBase> pc;
    StaticInstPtr macroStaticInst;
 
    // The remaining fields are only valid for particular instruction
    // types (e.g, addresses for memory ops) or when particular
    // options are enabled (e.g., tracing full register contents).
    // Each data field has an associated valid flag to indicate
    // whether the data field is valid.
 
    /*** @defgroup mem
     * @{
     * Memory request information in the instruction accessed memory.
     * @see mem_valid
     */
    Addr addr = 0; 
    Addr size = 0; 
    unsigned flags = 0; 
 
    union Data
    {
        ~Data() {}
        Data() {}
        uint64_t asInt = 0;
        double asDouble;
        InstResult asReg;
    } data;
 
    InstSeqNum fetch_seq = 0;
 
    InstSeqNum cp_seq = 0;
 
    enum DataStatus
    {
        DataInvalid = 0,
        DataInt8 = 1,   // set to equal number of bytes
        DataInt16 = 2,
        DataInt32 = 4,
        DataInt64 = 8,
        DataDouble = 3,
        DataReg = 5
    } dataStatus = DataInvalid;
 
    bool mem_valid = false;
 
    bool fetch_seq_valid = false;
    bool cp_seq_valid = false;
 
    bool predicate = true;
 
    bool faulting = false;
 
  public:
    InstRecord(Tick _when, ThreadContext *_thread,
               const StaticInstPtr _staticInst, const PCStateBase &_pc,
               const StaticInstPtr _macroStaticInst=nullptr)
        : when(_when), thread(_thread), staticInst(_staticInst),
        pc(_pc.clone()), macroStaticInst(_macroStaticInst)
    {}
 
    virtual ~InstRecord()
    {
        if (dataStatus == DataReg)
            data.asReg.~InstResult();
    }
 
    void setWhen(Tick new_when) { when = new_when; }
    void
    setMem(Addr a, Addr s, unsigned f)
    {
        addr = a;
        size = s;
        flags = f;
        mem_valid = true;
    }
 
    template <typename T, size_t N>
    void
    setData(std::array<T, N> d)
    {
        data.asInt = d[0];
        dataStatus = (DataStatus)sizeof(T);
        static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
                      sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
                      "Type T has an unrecognized size.");
    }
 
    void
    setData(uint64_t d)
    {
        data.asInt = d;
        dataStatus = DataInt64;
    }
    void
    setData(uint32_t d)
    {
        data.asInt = d;
        dataStatus = DataInt32;
    }
    void
    setData(uint16_t d)
    {
        data.asInt = d;
        dataStatus = DataInt16;
    }
    void
    setData(uint8_t d)
    {
        data.asInt = d;
        dataStatus = DataInt8;
    }
 
    void setData(int64_t d) { setData((uint64_t)d); }
    void setData(int32_t d) { setData((uint32_t)d); }
    void setData(int16_t d) { setData((uint16_t)d); }
    void setData(int8_t d)  { setData((uint8_t)d); }
 
    void
    setData(double d)
    {
        data.asDouble = d;
        dataStatus = DataDouble;
    }
 
    void
    setData(const RegClass &reg_class, RegVal val)
    {
        new(&data.asReg) InstResult(reg_class, val);
        switch (reg_class.type()) {
            case IntRegClass:
            case MiscRegClass:
            case CCRegClass:
                dataStatus = DataInt64;
                break;
            case FloatRegClass:
                dataStatus = DataDouble;
                break;
            default:
                dataStatus = DataReg;
                break;
        }
    }
 
    void
    setData(const RegClass &reg_class, const void *val)
    {
        new(&data.asReg) InstResult(reg_class, val);
        switch (reg_class.type()) {
            case IntRegClass:
            case MiscRegClass:
            case CCRegClass:
                dataStatus = DataInt64;
                break;
            case FloatRegClass:
                dataStatus = DataDouble;
                break;
            default:
                dataStatus = DataReg;
                break;
        }
    }
 
    void
    setFetchSeq(InstSeqNum seq)
    {
        fetch_seq = seq;
        fetch_seq_valid = true;
    }
 
    void
    setCPSeq(InstSeqNum seq)
    {
        cp_seq = seq;
        cp_seq_valid = true;
    }
 
    void setPredicate(bool val) { predicate = val; }
 
    void setFaulting(bool val) { faulting = val; }
 
    virtual void dump() = 0;
 
  public:
    Tick getWhen() const { return when; }
    ThreadContext *getThread() const { return thread; }
    StaticInstPtr getStaticInst() const { return staticInst; }
    const PCStateBase &getPCState() const { return *pc; }
    StaticInstPtr getMacroStaticInst() const { return macroStaticInst; }
 
    Addr getAddr() const { return addr; }
    Addr getSize() const { return size; }
    unsigned getFlags() const { return flags; }
    bool getMemValid() const { return mem_valid; }
 
    uint64_t getIntData() const { return data.asInt; }
    double getFloatData() const { return data.asDouble; }
    int getDataStatus() const { return dataStatus; }
 
    InstSeqNum getFetchSeq() const { return fetch_seq; }
    bool getFetchSeqValid() const { return fetch_seq_valid; }
 
    InstSeqNum getCpSeq() const { return cp_seq; }
    bool getCpSeqValid() const { return cp_seq_valid; }
 
    bool getFaulting() const { return faulting; }
};
 
class InstDisassembler : public SimObject
{
  public:
    InstDisassembler(const SimObjectParams &params)
      : SimObject(params)
    {}
 
    virtual std::string
    disassemble(StaticInstPtr inst,
                const PCStateBase &pc,
                const loader::SymbolTable *symtab) const
    {
        return inst->disassemble(pc.instAddr(), symtab);
    }
};
 
class InstTracer : public SimObject
{
  public:
    PARAMS(InstTracer);
    InstTracer(const Params &p)
      : SimObject(p), disassembler(p.disassembler)
    {}
 
    virtual ~InstTracer() {}
 
    virtual InstRecord *
        getInstRecord(Tick when, ThreadContext *tc,
                const StaticInstPtr staticInst, const PCStateBase &pc,
                const StaticInstPtr macroStaticInst=nullptr) = 0;
 
    std::string
    disassemble(StaticInstPtr inst,
                const PCStateBase &pc,
                const loader::SymbolTable *symtab=nullptr) const
    {
        return disassembler->disassemble(inst, pc, symtab);
    }
 
  private:
    InstDisassembler *disassembler;
};
 
} // namespace trace
} // namespace gem5
 
#endif // __INSTRECORD_HH__