gem5  v21.1.0.2
insttracer.hh
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40 
41 #ifndef __INSTRECORD_HH__
42 #define __INSTRECORD_HH__
43 
45 #include "arch/generic/vec_reg.hh"
46 #include "base/types.hh"
47 #include "cpu/inst_seq.hh"
48 #include "cpu/static_inst.hh"
49 #include "sim/sim_object.hh"
50 
51 namespace gem5
52 {
53 
54 class ThreadContext;
55 
56 namespace Trace {
57 
59 {
60  protected:
62 
63  // The following fields are initialized by the constructor and
64  // thus guaranteed to be valid.
66  // need to make this ref-counted so it doesn't go away before we
67  // dump the record
71 
72  // The remaining fields are only valid for particular instruction
73  // types (e.g, addresses for memory ops) or when particular
74  // options are enabled (e.g., tracing full register contents).
75  // Each data field has an associated valid flag to indicate
76  // whether the data field is valid.
77 
78  /*** @defgroup mem
79  * @{
80  * Memory request information in the instruction accessed memory.
81  * @see mem_valid
82  */
85  unsigned flags;
86 
97  union
98  {
99  uint64_t as_int;
100  double as_double;
103  } data;
104 
110 
116 
121  {
123  DataInt8 = 1, // set to equal number of bytes
128  DataVec = 5,
130  } data_status;
131 
135  bool mem_valid;
136 
145 
148  bool predicate;
149 
154  bool faulting;
155 
156  public:
157  InstRecord(Tick _when, ThreadContext *_thread,
158  const StaticInstPtr _staticInst,
159  TheISA::PCState _pc,
160  const StaticInstPtr _macroStaticInst = NULL)
161  : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
162  macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
164  fetch_seq_valid(false), cp_seq_valid(false), predicate(true),
165  faulting(false)
166  { }
167 
168  virtual ~InstRecord()
169  {
170  if (data_status == DataVec) {
171  assert(data.as_vec);
172  delete data.as_vec;
173  } else if (data_status == DataVecPred) {
174  assert(data.as_pred);
175  delete data.as_pred;
176  }
177  }
178 
179  void setWhen(Tick new_when) { when = new_when; }
180  void setMem(Addr a, Addr s, unsigned f)
181  {
182  addr = a; size = s; flags = f; mem_valid = true;
183  }
184 
185  template <typename T, size_t N>
186  void
187  setData(std::array<T, N> d)
188  {
189  data.as_int = d[0];
190  data_status = (DataStatus)sizeof(T);
191  static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
192  sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
193  "Type T has an unrecognized size.");
194  }
195 
196  void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
197  void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
198  void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
199  void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
200 
201  void setData(int64_t d) { setData((uint64_t)d); }
202  void setData(int32_t d) { setData((uint32_t)d); }
203  void setData(int16_t d) { setData((uint16_t)d); }
204  void setData(int8_t d) { setData((uint8_t)d); }
205 
206  void setData(double d) { data.as_double = d; data_status = DataDouble; }
207 
208  void
210  {
211  data.as_vec = new TheISA::VecRegContainer(d);
213  }
214 
215  void
217  {
218  data.as_pred = new TheISA::VecPredRegContainer(d);
220  }
221 
223  { fetch_seq = seq; fetch_seq_valid = true; }
224 
226  { cp_seq = seq; cp_seq_valid = true; }
227 
228  void setPredicate(bool val) { predicate = val; }
229 
230  void setFaulting(bool val) { faulting = val; }
231 
232  virtual void dump() = 0;
233 
234  public:
235  Tick getWhen() const { return when; }
236  ThreadContext *getThread() const { return thread; }
238  TheISA::PCState getPCState() const { return pc; }
240 
241  Addr getAddr() const { return addr; }
242  Addr getSize() const { return size; }
243  unsigned getFlags() const { return flags; }
244  bool getMemValid() const { return mem_valid; }
245 
246  uint64_t getIntData() const { return data.as_int; }
247  double getFloatData() const { return data.as_double; }
248  int getDataStatus() const { return data_status; }
249 
250  InstSeqNum getFetchSeq() const { return fetch_seq; }
251  bool getFetchSeqValid() const { return fetch_seq_valid; }
252 
253  InstSeqNum getCpSeq() const { return cp_seq; }
254  bool getCpSeqValid() const { return cp_seq_valid; }
255 
256  bool getFaulting() const { return faulting; }
257 };
258 
259 class InstTracer : public SimObject
260 {
261  public:
263  {}
264 
265  virtual ~InstTracer()
266  {};
267 
268  virtual InstRecord *
269  getInstRecord(Tick when, ThreadContext *tc,
270  const StaticInstPtr staticInst, TheISA::PCState pc,
271  const StaticInstPtr macroStaticInst = NULL) = 0;
272 };
273 
274 } // namespace Trace
275 } // namespace gem5
276 
277 #endif // __INSTRECORD_HH__
gem5::Trace::InstRecord::setFaulting
void setFaulting(bool val)
Definition: insttracer.hh:230
gem5::Trace::InstRecord::getAddr
Addr getAddr() const
Definition: insttracer.hh:241
gem5::Trace::InstRecord::cp_seq_valid
bool cp_seq_valid
Definition: insttracer.hh:144
gem5::Trace::InstRecord::getFetchSeqValid
bool getFetchSeqValid() const
Definition: insttracer.hh:251
gem5::Trace::InstRecord::as_int
uint64_t as_int
Definition: insttracer.hh:99
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::Trace::InstRecord::setMem
void setMem(Addr a, Addr s, unsigned f)
Definition: insttracer.hh:180
gem5::Trace::InstRecord::setWhen
void setWhen(Tick new_when)
Definition: insttracer.hh:179
gem5::Trace::InstRecord::as_vec
TheISA::VecRegContainer * as_vec
Definition: insttracer.hh:101
gem5::Trace::InstRecord::getFloatData
double getFloatData() const
Definition: insttracer.hh:247
gem5::Trace::InstRecord::getSize
Addr getSize() const
Definition: insttracer.hh:242
gem5::ArmISA::f
Bitfield< 6 > f
Definition: misc_types.hh:67
gem5::Trace::InstRecord::setData
void setData(int32_t d)
Definition: insttracer.hh:202
gem5::Trace::InstRecord::data
union gem5::Trace::InstRecord::@111 data
gem5::Trace::InstRecord::as_double
double as_double
Definition: insttracer.hh:100
gem5::Trace::InstRecord::setData
void setData(double d)
Definition: insttracer.hh:206
gem5::Trace::InstRecord::setFetchSeq
void setFetchSeq(InstSeqNum seq)
Definition: insttracer.hh:222
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::Trace::InstRecord::setCPSeq
void setCPSeq(InstSeqNum seq)
Definition: insttracer.hh:225
gem5::Trace::InstRecord::setData
void setData(std::array< T, N > d)
Definition: insttracer.hh:187
gem5::Trace::InstRecord::getIntData
uint64_t getIntData() const
Definition: insttracer.hh:246
gem5::Trace::InstRecord::thread
ThreadContext * thread
Definition: insttracer.hh:65
gem5::Trace::InstRecord::~InstRecord
virtual ~InstRecord()
Definition: insttracer.hh:168
gem5::Trace::InstRecord::getStaticInst
StaticInstPtr getStaticInst() const
Definition: insttracer.hh:237
gem5::Trace::InstRecord::setPredicate
void setPredicate(bool val)
Definition: insttracer.hh:228
gem5::Trace::InstRecord::fetch_seq_valid
bool fetch_seq_valid
Definition: insttracer.hh:140
gem5::Trace::InstRecord::DataVecPred
@ DataVecPred
Definition: insttracer.hh:129
gem5::Trace::InstRecord::getCpSeqValid
bool getCpSeqValid() const
Definition: insttracer.hh:254
gem5::Trace::InstRecord::setData
void setData(int16_t d)
Definition: insttracer.hh:203
gem5::Trace::InstRecord::setData
void setData(int64_t d)
Definition: insttracer.hh:201
gem5::Trace::InstRecord::getPCState
TheISA::PCState getPCState() const
Definition: insttracer.hh:238
gem5::Trace::InstRecord::DataInt8
@ DataInt8
Definition: insttracer.hh:123
gem5::RefCountingPtr< StaticInst >
gem5::Trace::InstRecord::mem_valid
bool mem_valid
Definition: insttracer.hh:135
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::Trace::InstRecord::setData
void setData(int8_t d)
Definition: insttracer.hh:204
gem5::Trace::InstRecord::getFetchSeq
InstSeqNum getFetchSeq() const
Definition: insttracer.hh:250
inst_seq.hh
gem5::Trace::InstRecord::setData
void setData(TheISA::VecRegContainer &d)
Definition: insttracer.hh:209
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Trace::InstRecord::getMemValid
bool getMemValid() const
Definition: insttracer.hh:244
sim_object.hh
gem5::Trace::InstRecord::pc
TheISA::PCState pc
Definition: insttracer.hh:69
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:63
gem5::Trace::InstRecord::staticInst
StaticInstPtr staticInst
Definition: insttracer.hh:68
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Trace::InstRecord::getMacroStaticInst
StaticInstPtr getMacroStaticInst() const
Definition: insttracer.hh:239
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::Trace::InstRecord::setData
void setData(uint64_t d)
Definition: insttracer.hh:196
gem5::Trace::InstTracer
Definition: insttracer.hh:259
gem5::Trace::InstRecord::data_status
enum gem5::Trace::InstRecord::DataStatus data_status
gem5::Trace::InstRecord::DataInt32
@ DataInt32
Definition: insttracer.hh:125
gem5::Trace::InstRecord::getThread
ThreadContext * getThread() const
Definition: insttracer.hh:236
gem5::Trace::InstRecord::DataInvalid
@ DataInvalid
Definition: insttracer.hh:122
gem5::Trace::InstRecord::as_pred
TheISA::VecPredRegContainer * as_pred
Definition: insttracer.hh:102
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
static_inst.hh
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Trace::InstTracer::getInstRecord
virtual InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, TheISA::PCState pc, const StaticInstPtr macroStaticInst=NULL)=0
gem5::Trace::InstRecord::fetch_seq
InstSeqNum fetch_seq
Definition: insttracer.hh:109
vec_pred_reg.hh
gem5::Trace::InstRecord::getCpSeq
InstSeqNum getCpSeq() const
Definition: insttracer.hh:253
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Trace::InstRecord::DataStatus
DataStatus
Definition: insttracer.hh:120
gem5::Trace::InstRecord::DataInt16
@ DataInt16
Definition: insttracer.hh:124
gem5::Trace::InstRecord::setData
void setData(uint16_t d)
Definition: insttracer.hh:198
gem5::Trace::InstRecord::dump
virtual void dump()=0
vec_reg.hh
gem5::Trace::InstRecord::DataInt64
@ DataInt64
Definition: insttracer.hh:126
gem5::Trace::InstRecord::setData
void setData(uint8_t d)
Definition: insttracer.hh:199
gem5::Trace::InstRecord::size
Addr size
The size of the memory request.
Definition: insttracer.hh:84
gem5::Trace::InstRecord::cp_seq
InstSeqNum cp_seq
Definition: insttracer.hh:115
gem5::Trace::InstRecord::DataVec
@ DataVec
Definition: insttracer.hh:128
gem5::Trace::InstRecord::setData
void setData(TheISA::VecPredRegContainer &d)
Definition: insttracer.hh:216
gem5::Trace::InstRecord::predicate
bool predicate
is the predicate for execution this inst true or false (not execed)?
Definition: insttracer.hh:148
types.hh
gem5::Trace::InstRecord::getFaulting
bool getFaulting() const
Definition: insttracer.hh:256
gem5::Trace::InstRecord::addr
Addr addr
The address that was accessed.
Definition: insttracer.hh:83
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::Trace::InstRecord::DataDouble
@ DataDouble
Definition: insttracer.hh:127
gem5::Trace::InstTracer::~InstTracer
virtual ~InstTracer()
Definition: insttracer.hh:265
gem5::Trace::InstRecord::setData
void setData(uint32_t d)
Definition: insttracer.hh:197
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::Trace::InstRecord::InstRecord
InstRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, TheISA::PCState _pc, const StaticInstPtr _macroStaticInst=NULL)
Definition: insttracer.hh:157
gem5::Trace::InstRecord::when
Tick when
Definition: insttracer.hh:61
gem5::Trace::InstRecord::macroStaticInst
StaticInstPtr macroStaticInst
Definition: insttracer.hh:70
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Trace::InstRecord::faulting
bool faulting
Did the execution of this instruction fault? (requires ExecFaulting to be enabled)
Definition: insttracer.hh:154
gem5::Trace::InstRecord::flags
unsigned flags
The flags that were assigned to the request.
Definition: insttracer.hh:85
gem5::Trace::InstRecord::getDataStatus
int getDataStatus() const
Definition: insttracer.hh:248
gem5::Trace::InstTracer::InstTracer
InstTracer(const Params &p)
Definition: insttracer.hh:262
gem5::Trace::InstRecord::getFlags
unsigned getFlags() const
Definition: insttracer.hh:243
gem5::Trace::InstRecord::getWhen
Tick getWhen() const
Definition: insttracer.hh:235

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