gem5  v21.2.1.1
insttracer.hh
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40 
41 #ifndef __INSTRECORD_HH__
42 #define __INSTRECORD_HH__
43 
44 #include <memory>
45 
46 #include "arch/generic/pcstate.hh"
48 #include "arch/generic/vec_reg.hh"
49 #include "base/types.hh"
50 #include "cpu/inst_seq.hh"
51 #include "cpu/static_inst.hh"
52 #include "sim/sim_object.hh"
53 
54 namespace gem5
55 {
56 
57 class ThreadContext;
58 
59 namespace Trace {
60 
62 {
63  protected:
65 
66  // The following fields are initialized by the constructor and
67  // thus guaranteed to be valid.
69  // need to make this ref-counted so it doesn't go away before we
70  // dump the record
72  std::unique_ptr<PCStateBase> pc;
74 
75  // The remaining fields are only valid for particular instruction
76  // types (e.g, addresses for memory ops) or when particular
77  // options are enabled (e.g., tracing full register contents).
78  // Each data field has an associated valid flag to indicate
79  // whether the data field is valid.
80 
81  /*** @defgroup mem
82  * @{
83  * Memory request information in the instruction accessed memory.
84  * @see mem_valid
85  */
88  unsigned flags;
89 
100  union
101  {
102  uint64_t as_int;
103  double as_double;
106  } data;
107 
113 
119 
124  {
126  DataInt8 = 1, // set to equal number of bytes
131  DataVec = 5,
133  } data_status;
134 
138  bool mem_valid;
139 
148 
151  bool predicate;
152 
157  bool faulting;
158 
159  public:
160  InstRecord(Tick _when, ThreadContext *_thread,
161  const StaticInstPtr _staticInst, const PCStateBase &_pc,
162  const StaticInstPtr _macroStaticInst=nullptr)
163  : when(_when), thread(_thread), staticInst(_staticInst),
164  pc(_pc.clone()), macroStaticInst(_macroStaticInst), addr(0), size(0),
166  mem_valid(false), fetch_seq_valid(false), cp_seq_valid(false),
167  predicate(true), faulting(false)
168  { }
169 
170  virtual ~InstRecord()
171  {
172  if (data_status == DataVec) {
173  assert(data.as_vec);
174  delete data.as_vec;
175  } else if (data_status == DataVecPred) {
176  assert(data.as_pred);
177  delete data.as_pred;
178  }
179  }
180 
181  void setWhen(Tick new_when) { when = new_when; }
182  void setMem(Addr a, Addr s, unsigned f)
183  {
184  addr = a; size = s; flags = f; mem_valid = true;
185  }
186 
187  template <typename T, size_t N>
188  void
189  setData(std::array<T, N> d)
190  {
191  data.as_int = d[0];
192  data_status = (DataStatus)sizeof(T);
193  static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
194  sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
195  "Type T has an unrecognized size.");
196  }
197 
198  void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
199  void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
200  void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
201  void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
202 
203  void setData(int64_t d) { setData((uint64_t)d); }
204  void setData(int32_t d) { setData((uint32_t)d); }
205  void setData(int16_t d) { setData((uint16_t)d); }
206  void setData(int8_t d) { setData((uint8_t)d); }
207 
208  void setData(double d) { data.as_double = d; data_status = DataDouble; }
209 
210  void
212  {
213  data.as_vec = new TheISA::VecRegContainer(d);
215  }
216 
217  void
219  {
220  data.as_pred = new TheISA::VecPredRegContainer(d);
222  }
223 
225  { fetch_seq = seq; fetch_seq_valid = true; }
226 
228  { cp_seq = seq; cp_seq_valid = true; }
229 
230  void setPredicate(bool val) { predicate = val; }
231 
232  void setFaulting(bool val) { faulting = val; }
233 
234  virtual void dump() = 0;
235 
236  public:
237  Tick getWhen() const { return when; }
238  ThreadContext *getThread() const { return thread; }
240  const PCStateBase &getPCState() const { return *pc; }
242 
243  Addr getAddr() const { return addr; }
244  Addr getSize() const { return size; }
245  unsigned getFlags() const { return flags; }
246  bool getMemValid() const { return mem_valid; }
247 
248  uint64_t getIntData() const { return data.as_int; }
249  double getFloatData() const { return data.as_double; }
250  int getDataStatus() const { return data_status; }
251 
252  InstSeqNum getFetchSeq() const { return fetch_seq; }
253  bool getFetchSeqValid() const { return fetch_seq_valid; }
254 
255  InstSeqNum getCpSeq() const { return cp_seq; }
256  bool getCpSeqValid() const { return cp_seq_valid; }
257 
258  bool getFaulting() const { return faulting; }
259 };
260 
261 class InstTracer : public SimObject
262 {
263  public:
265  {}
266 
267  virtual ~InstTracer()
268  {};
269 
270  virtual InstRecord *
271  getInstRecord(Tick when, ThreadContext *tc,
272  const StaticInstPtr staticInst, const PCStateBase &pc,
273  const StaticInstPtr macroStaticInst=nullptr) = 0;
274 };
275 
276 } // namespace Trace
277 } // namespace gem5
278 
279 #endif // __INSTRECORD_HH__
gem5::Trace::InstRecord::setFaulting
void setFaulting(bool val)
Definition: insttracer.hh:232
gem5::Trace::InstRecord::getAddr
Addr getAddr() const
Definition: insttracer.hh:243
gem5::Trace::InstRecord::getPCState
const PCStateBase & getPCState() const
Definition: insttracer.hh:240
gem5::Trace::InstRecord::cp_seq_valid
bool cp_seq_valid
Definition: insttracer.hh:147
gem5::Trace::InstRecord::getFetchSeqValid
bool getFetchSeqValid() const
Definition: insttracer.hh:253
gem5::Trace::InstRecord::as_int
uint64_t as_int
Definition: insttracer.hh:102
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::Trace::InstRecord::setMem
void setMem(Addr a, Addr s, unsigned f)
Definition: insttracer.hh:182
gem5::Trace::InstRecord::setWhen
void setWhen(Tick new_when)
Definition: insttracer.hh:181
gem5::Trace::InstRecord::as_vec
TheISA::VecRegContainer * as_vec
Definition: insttracer.hh:104
gem5::Trace::InstRecord::getFloatData
double getFloatData() const
Definition: insttracer.hh:249
gem5::Trace::InstRecord::InstRecord
InstRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, const PCStateBase &_pc, const StaticInstPtr _macroStaticInst=nullptr)
Definition: insttracer.hh:160
gem5::Trace::InstRecord::getSize
Addr getSize() const
Definition: insttracer.hh:244
gem5::ArmISA::f
Bitfield< 6 > f
Definition: misc_types.hh:68
gem5::Trace::InstRecord::setData
void setData(int32_t d)
Definition: insttracer.hh:204
gem5::Trace::InstRecord::as_double
double as_double
Definition: insttracer.hh:103
gem5::Trace::InstRecord::setData
void setData(double d)
Definition: insttracer.hh:208
gem5::Trace::InstRecord::setFetchSeq
void setFetchSeq(InstSeqNum seq)
Definition: insttracer.hh:224
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:66
gem5::Trace::InstRecord::setCPSeq
void setCPSeq(InstSeqNum seq)
Definition: insttracer.hh:227
gem5::Trace::InstRecord::setData
void setData(std::array< T, N > d)
Definition: insttracer.hh:189
gem5::Trace::InstRecord::getIntData
uint64_t getIntData() const
Definition: insttracer.hh:248
gem5::Trace::InstRecord::thread
ThreadContext * thread
Definition: insttracer.hh:68
gem5::Trace::InstRecord::~InstRecord
virtual ~InstRecord()
Definition: insttracer.hh:170
gem5::Trace::InstRecord::getStaticInst
StaticInstPtr getStaticInst() const
Definition: insttracer.hh:239
gem5::Trace::InstRecord::setPredicate
void setPredicate(bool val)
Definition: insttracer.hh:230
gem5::Trace::InstRecord::fetch_seq_valid
bool fetch_seq_valid
Definition: insttracer.hh:143
gem5::Trace::InstRecord::DataVecPred
@ DataVecPred
Definition: insttracer.hh:132
gem5::Trace::InstRecord::getCpSeqValid
bool getCpSeqValid() const
Definition: insttracer.hh:256
gem5::Trace::InstRecord::setData
void setData(int16_t d)
Definition: insttracer.hh:205
gem5::Trace::InstRecord::setData
void setData(int64_t d)
Definition: insttracer.hh:203
gem5::Trace::InstRecord::DataInt8
@ DataInt8
Definition: insttracer.hh:126
gem5::RefCountingPtr< StaticInst >
gem5::Trace::InstRecord::mem_valid
bool mem_valid
Definition: insttracer.hh:138
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::Trace::InstRecord::data
union gem5::Trace::InstRecord::@119 data
gem5::Trace::InstRecord::setData
void setData(int8_t d)
Definition: insttracer.hh:206
gem5::Trace::InstRecord::getFetchSeq
InstSeqNum getFetchSeq() const
Definition: insttracer.hh:252
inst_seq.hh
gem5::Trace::InstRecord::setData
void setData(TheISA::VecRegContainer &d)
Definition: insttracer.hh:211
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Trace::InstRecord::getMemValid
bool getMemValid() const
Definition: insttracer.hh:246
gem5::Trace::InstTracer::getInstRecord
virtual InstRecord * getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, const PCStateBase &pc, const StaticInstPtr macroStaticInst=nullptr)=0
sim_object.hh
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:64
gem5::Trace::InstRecord::staticInst
StaticInstPtr staticInst
Definition: insttracer.hh:71
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Trace::InstRecord::getMacroStaticInst
StaticInstPtr getMacroStaticInst() const
Definition: insttracer.hh:241
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:562
gem5::Trace::InstRecord::setData
void setData(uint64_t d)
Definition: insttracer.hh:198
gem5::Trace::InstTracer
Definition: insttracer.hh:261
gem5::Trace::InstRecord::data_status
enum gem5::Trace::InstRecord::DataStatus data_status
gem5::Trace::InstRecord::DataInt32
@ DataInt32
Definition: insttracer.hh:128
gem5::Trace::InstRecord::getThread
ThreadContext * getThread() const
Definition: insttracer.hh:238
gem5::Trace::InstRecord::DataInvalid
@ DataInvalid
Definition: insttracer.hh:125
gem5::Trace::InstRecord::as_pred
TheISA::VecPredRegContainer * as_pred
Definition: insttracer.hh:105
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
static_inst.hh
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Trace::InstRecord::fetch_seq
InstSeqNum fetch_seq
Definition: insttracer.hh:112
vec_pred_reg.hh
gem5::Trace::InstRecord::getCpSeq
InstSeqNum getCpSeq() const
Definition: insttracer.hh:255
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Trace::InstRecord::DataStatus
DataStatus
Definition: insttracer.hh:123
gem5::Trace::InstRecord::DataInt16
@ DataInt16
Definition: insttracer.hh:127
gem5::Trace::InstRecord::setData
void setData(uint16_t d)
Definition: insttracer.hh:200
gem5::Trace::InstRecord::pc
std::unique_ptr< PCStateBase > pc
Definition: insttracer.hh:72
gem5::Trace::InstRecord::dump
virtual void dump()=0
vec_reg.hh
gem5::Trace::InstRecord::DataInt64
@ DataInt64
Definition: insttracer.hh:129
pcstate.hh
gem5::Trace::InstRecord::setData
void setData(uint8_t d)
Definition: insttracer.hh:201
gem5::Trace::InstRecord::size
Addr size
The size of the memory request.
Definition: insttracer.hh:87
gem5::Trace::InstRecord::cp_seq
InstSeqNum cp_seq
Definition: insttracer.hh:118
gem5::Trace::InstRecord::DataVec
@ DataVec
Definition: insttracer.hh:131
gem5::Trace::InstRecord::setData
void setData(TheISA::VecPredRegContainer &d)
Definition: insttracer.hh:218
gem5::Trace::InstRecord::predicate
bool predicate
is the predicate for execution this inst true or false (not execed)?
Definition: insttracer.hh:151
types.hh
gem5::Trace::InstRecord::getFaulting
bool getFaulting() const
Definition: insttracer.hh:258
gem5::Trace::InstRecord::addr
Addr addr
The address that was accessed.
Definition: insttracer.hh:86
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::Trace::InstRecord::DataDouble
@ DataDouble
Definition: insttracer.hh:130
gem5::Trace::InstTracer::~InstTracer
virtual ~InstTracer()
Definition: insttracer.hh:267
gem5::Trace::InstRecord::setData
void setData(uint32_t d)
Definition: insttracer.hh:199
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::Trace::InstRecord::when
Tick when
Definition: insttracer.hh:64
gem5::Trace::InstRecord::macroStaticInst
StaticInstPtr macroStaticInst
Definition: insttracer.hh:73
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::Trace::InstRecord::faulting
bool faulting
Did the execution of this instruction fault? (requires ExecFaulting to be enabled)
Definition: insttracer.hh:157
gem5::Trace::InstRecord::flags
unsigned flags
The flags that were assigned to the request.
Definition: insttracer.hh:88
gem5::Trace::InstRecord::getDataStatus
int getDataStatus() const
Definition: insttracer.hh:250
gem5::Trace::InstTracer::InstTracer
InstTracer(const Params &p)
Definition: insttracer.hh:264
gem5::Trace::InstRecord::getFlags
unsigned getFlags() const
Definition: insttracer.hh:245
gem5::Trace::InstRecord::getWhen
Tick getWhen() const
Definition: insttracer.hh:237

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