gem5  v21.1.0.2
tarmac_base.cc
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37 
39 
40 #include <algorithm>
41 #include <string>
42 
43 #include "arch/arm/regs/misc.hh"
44 #include "cpu/reg_class.hh"
45 #include "cpu/static_inst.hh"
46 #include "cpu/thread_context.hh"
47 
48 namespace gem5
49 {
50 
51 using namespace ArmISA;
52 
53 namespace Trace {
54 
55 TarmacBaseRecord::TarmacBaseRecord(Tick _when, ThreadContext *_thread,
56  const StaticInstPtr _staticInst,
57  PCState _pc,
58  const StaticInstPtr _macroStaticInst)
59  : InstRecord(_when, _thread, _staticInst, _pc, _macroStaticInst)
60 {
61 }
62 
64  ThreadContext* thread,
65  PCState pc,
66  const StaticInstPtr staticInst,
67  bool predicate)
68  : taken(predicate) ,
69  addr(pc.instAddr()) ,
70  opcode(staticInst->getEMI() & 0xffffffff),
71  disassemble(staticInst->disassemble(addr)),
72  isetstate(pcToISetState(pc)),
74 {
75 
76  // Operating mode gained by reading the architectural register (CPSR)
77  const CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
78  mode = (OperatingMode) (uint8_t)cpsr.mode;
79 
80  // In Tarmac, instruction names are printed in capital
81  // letters.
82  std::for_each(disassemble.begin(), disassemble.end(),
83  [](char& c) { c = toupper(c); });
84 }
85 
87  : isetstate(pcToISetState(pc)),
88  values(2, 0)
89 {
90  // values vector is constructed with size = 2, for
91  // holding Lo and Hi values.
92 }
93 
95  uint8_t _size,
96  Addr _addr,
97  uint64_t _data)
98  : size(_size), addr(_addr), data(_data)
99 {
100 }
101 
104 {
105  TarmacBaseRecord::ISetState isetstate;
106 
107  if (pc.aarch64())
108  isetstate = TarmacBaseRecord::ISET_A64;
109  else if (!pc.thumb() && !pc.jazelle())
110  isetstate = TarmacBaseRecord::ISET_ARM;
111  else if (pc.thumb() && !pc.jazelle())
112  isetstate = TarmacBaseRecord::ISET_THUMB;
113  else
114  // No Jazelle state in TARMAC
116 
117  return isetstate;
118 }
119 
120 } // namespace Trace
121 } // namespace gem5
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:61
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Trace::InstRecord::thread
ThreadContext * thread
Definition: insttracer.hh:65
gem5::Trace::TarmacBaseRecord::ISET_A64
@ ISET_A64
Definition: tarmac_base.hh:77
tarmac_base.hh
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::RefCountingPtr< StaticInst >
gem5::Trace::TarmacBaseRecord::ISET_ARM
@ ISET_ARM
Definition: tarmac_base.hh:77
gem5::ArmISA::opcode
Bitfield< 24, 21 > opcode
Definition: types.hh:92
gem5::Trace::TarmacBaseRecord::ISetState
ISetState
ARM instruction set state.
Definition: tarmac_base.hh:77
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Trace::TarmacBaseRecord::ISET_THUMB
@ ISET_THUMB
Definition: tarmac_base.hh:77
gem5::Trace::TarmacBaseRecord::InstEntry::InstEntry
InstEntry()=default
gem5::Trace::InstRecord::pc
TheISA::PCState pc
Definition: insttracer.hh:69
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
static_inst.hh
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::MODE_USER
@ MODE_USER
Definition: types.hh:281
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Trace::TarmacBaseRecord::MemEntry::MemEntry
MemEntry()=default
gem5::Trace::TarmacBaseRecord::ISET_UNSUPPORTED
@ ISET_UNSUPPORTED
Definition: tarmac_base.hh:78
misc.hh
gem5::Trace::TarmacBaseRecord::pcToISetState
static ISetState pcToISetState(ArmISA::PCState pc)
Returns the Instruction Set State according to the current PCState.
Definition: tarmac_base.cc:103
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
reg_class.hh
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
thread_context.hh
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::Trace::TarmacBaseRecord::RegEntry::RegEntry
RegEntry()=default
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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