gem5 v24.0.0.0
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Predicate register view. More...
#include <vec_pred_reg.hh>
Public Types | |
using | Container |
Container type alias. | |
Public Member Functions | |
VecPredRegT (Container &c) | |
template<bool Condition = !Const> | |
std::enable_if_t< Condition > | reset () |
Reset the register to an all-false value. | |
template<bool Condition = !Const> | |
std::enable_if_t< Condition > | set () |
Reset the register to an all-true value. | |
template<bool Condition = !Const> | |
std::enable_if_t< Condition, MyClass & > | operator= (const MyClass &that) |
const bool & | operator[] (size_t idx) const |
template<bool Condition = !Const> | |
std::enable_if_t< Condition, bool & > | operator[] (size_t idx) |
uint8_t | getRaw (size_t idx) const |
Return an element of the predicate register as it appears in the raw (untyped) internal representation. | |
template<bool Condition = !Const> | |
std::enable_if_t< Condition > | setRaw (size_t idx, uint8_t val) |
Write a raw value in an element of the predicate register. | |
template<typename VE2 , size_t NE2, bool P2, bool C2> | |
bool | operator== (const VecPredRegT< VE2, NE2, P2, C2 > &that) const |
Equality operator, required to compare thread contexts. | |
template<typename VE2 , size_t NE2, bool P2, bool C2> | |
bool | operator!= (const VecPredRegT< VE2, NE2, P2, C2 > &that) const |
Inequality operator, required to compare thread contexts. | |
template<bool MC> | |
bool | firstActive (const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const |
Returns true if the first active element of the register is true. | |
template<bool MC> | |
bool | noneActive (const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const |
Returns true if there are no active elements in the register. | |
template<bool MC> | |
bool | lastActive (const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const |
Returns true if the last active element of the register is true. | |
Protected Types | |
using | MyClass = VecPredRegT<VecElem, NumElems, Packed, Const> |
Protected Attributes | |
Container & | container |
Container corresponding to this view. | |
Static Protected Attributes | |
static constexpr size_t | NUM_BITS |
Size of the register in bits. | |
Friends | |
std::ostream & | operator<< (std::ostream &os, const MyClass &p) |
Predicate register view.
This generic class implements the View in an MVC pattern, similarly to
VecElem | Type of the vector elements. |
NumElems | Number of vector elements making up the view. |
Packed | True if the predicate register relies on a packed representation, i.e. adjacent bits refer to different vector elements irrespective of the vector element size (e.g. this is the case for AVX-512). If false, the predicate register relies on an unpacked representation, where each bit refers to the corresponding byte in a vector register (e.g. this is the case for ARM SVE). |
Const | True if the underlying container can be modified through the view. |
Definition at line 73 of file vec_pred_reg.hh.
using gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::Container |
Container type alias.
Definition at line 82 of file vec_pred_reg.hh.
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protected |
Definition at line 89 of file vec_pred_reg.hh.
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inline |
Definition at line 94 of file vec_pred_reg.hh.
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inline |
Returns true if the first active element of the register is true.
mask | Input mask used to filter the predicates to be tested. |
actual_num_elems | Actual number of vector elements considered for the test (corresponding to the current vector length). |
Definition at line 175 of file vec_pred_reg.hh.
References gem5::ArmISA::i, and gem5::ArmISA::mask.
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inline |
Return an element of the predicate register as it appears in the raw (untyped) internal representation.
Definition at line 128 of file vec_pred_reg.hh.
References gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::container.
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inline |
Returns true if the last active element of the register is true.
mask | Input mask used to filter the predicates to be tested. |
actual_num_elems | Actual number of vector elements considered for the test (corresponding to the current vector length). |
Definition at line 211 of file vec_pred_reg.hh.
References gem5::ArmISA::i, gem5::ArmISA::mask, and gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::operator[]().
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inline |
Returns true if there are no active elements in the register.
mask | Input mask used to filter the predicates to be tested. |
actual_num_elems | Actual number of vector elements considered for the test (corresponding to the current vector length). |
Definition at line 193 of file vec_pred_reg.hh.
References gem5::ArmISA::i, and gem5::ArmISA::mask.
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inline |
Inequality operator, required to compare thread contexts.
Definition at line 154 of file vec_pred_reg.hh.
References gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::operator==().
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inline |
Definition at line 106 of file vec_pred_reg.hh.
References gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::container.
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inline |
Equality operator, required to compare thread contexts.
Definition at line 146 of file vec_pred_reg.hh.
References gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::container.
Referenced by gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::operator!=().
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inline |
Definition at line 120 of file vec_pred_reg.hh.
References gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::container.
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inline |
Definition at line 113 of file vec_pred_reg.hh.
References gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::container.
Referenced by gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::lastActive().
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inline |
Reset the register to an all-false value.
Definition at line 98 of file vec_pred_reg.hh.
References gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::container.
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inline |
Reset the register to an all-true value.
Definition at line 102 of file vec_pred_reg.hh.
References gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::container.
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inline |
Write a raw value in an element of the predicate register.
Definition at line 137 of file vec_pred_reg.hh.
References gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::container, and gem5::X86ISA::val.
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friend |
Definition at line 159 of file vec_pred_reg.hh.
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protected |
Container corresponding to this view.
Definition at line 91 of file vec_pred_reg.hh.
Referenced by gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::getRaw(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::operator=(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::operator==(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::operator[](), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::operator[](), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::reset(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::set(), and gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::setRaw().
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staticconstexprprotected |
Size of the register in bits.
Definition at line 77 of file vec_pred_reg.hh.