gem5  v21.1.0.2
vec.hh
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40 
41 #ifndef __ARCH_ARM_REGS_VEC_HH__
42 #define __ARCH_ARM_REGS_VEC_HH__
43 
44 #include "arch/arm/types.hh"
46 #include "arch/generic/vec_reg.hh"
47 
48 namespace gem5
49 {
50 
51 namespace ArmISA
52 {
53 
54 // Number of VecElem per Vector Register considering only pre-SVE
55 // Advanced SIMD registers.
56 constexpr unsigned NumVecElemPerNeonVecReg = 4;
57 // Number of VecElem per Vector Register, computed based on the vector length
59 
60 using VecElem = uint32_t;
61 using VecRegContainer =
63 
64 using VecPredReg =
66 using ConstVecPredReg =
69 
70 // Vec, PredVec
71 // NumFloatV7ArchRegs: This in theory should be 32.
72 // However in A32 gem5 is splitting double register accesses in two
73 // subsequent single register ones. This means we would use a index
74 // bigger than 31 when accessing D16-D31.
75 const int NumFloatV7ArchRegs = 64; // S0-S31, D0-D31
76 const int NumVecV7ArchRegs = 16; // Q0-Q15
77 const int NumVecV8ArchRegs = 32; // V0-V31
78 const int NumVecSpecialRegs = 8;
79 const int NumVecIntrlvRegs = 4;
81 const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0
82 
83 // Vec, PredVec indices
86 const int INTRLVREG1 = INTRLVREG0 + 1;
87 const int INTRLVREG2 = INTRLVREG0 + 2;
88 const int INTRLVREG3 = INTRLVREG0 + 3;
89 const int VECREG_UREG0 = 32;
90 const int PREDREG_FFR = 16;
91 const int PREDREG_UREG0 = 17;
92 
93 } // namespace ArmISA
94 } // namespace gem5
95 
96 #endif
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::ArmISA::NumVecElemPerNeonVecReg
constexpr unsigned NumVecElemPerNeonVecReg
Definition: vec.hh:56
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::ArmISA::NumVecRegs
const int NumVecRegs
Definition: vec.hh:80
gem5::ArmISA::INTRLVREG2
const int INTRLVREG2
Definition: vec.hh:87
gem5::ArmISA::MaxSveVecLenInWords
constexpr unsigned MaxSveVecLenInWords
Definition: types.hh:462
gem5::ArmISA::NumFloatV7ArchRegs
const int NumFloatV7ArchRegs
Definition: vec.hh:75
types.hh
gem5::ArmISA::VECREG_UREG0
const int VECREG_UREG0
Definition: vec.hh:89
gem5::ArmISA::PREDREG_FFR
const int PREDREG_FFR
Definition: vec.hh:90
gem5::ArmISA::NumVecV7ArchRegs
const int NumVecV7ArchRegs
Definition: vec.hh:76
gem5::ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: vec.hh:81
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)>
gem5::ArmISA::INTRLVREG1
const int INTRLVREG1
Definition: vec.hh:86
gem5::VecPredRegT
Predicate register view.
Definition: vec_pred_reg.hh:72
vec_pred_reg.hh
gem5::VecPredRegT::Container
typename std::conditional_t< Const, const VecPredRegContainer< NUM_BITS, Packed >, VecPredRegContainer< NUM_BITS, Packed > > Container
Container type alias.
Definition: vec_pred_reg.hh:84
gem5::ArmISA::VecSpecialElem
const int VecSpecialElem
Definition: vec.hh:84
gem5::ArmISA::PREDREG_UREG0
const int PREDREG_UREG0
Definition: vec.hh:91
vec_reg.hh
gem5::ArmISA::NumVecIntrlvRegs
const int NumVecIntrlvRegs
Definition: vec.hh:79
gem5::ArmISA::INTRLVREG0
const int INTRLVREG0
Definition: vec.hh:85
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::ArmISA::NumVecV8ArchRegs
const int NumVecV8ArchRegs
Definition: vec.hh:77
gem5::ArmISA::INTRLVREG3
const int INTRLVREG3
Definition: vec.hh:88
gem5::ArmISA::NumVecSpecialRegs
const int NumVecSpecialRegs
Definition: vec.hh:78
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

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