vfp.hh File Reference

#include <fenv.h>
#include <cmath>
#include "arch/arm/insts/misc.hh"
#include "arch/arm/pcstate.hh"
#include "arch/arm/regs/misc.hh"
#include "cpu/thread_context.hh"

Go to the source code of this file.

Classes
class	gem5::ArmISA::VfpMacroOp
class	gem5::ArmISA::FpOp
class	gem5::ArmISA::FpCondCompRegOp
class	gem5::ArmISA::FpCondSelOp
class	gem5::ArmISA::FpRegRegOp
class	gem5::ArmISA::FpRegImmOp
class	gem5::ArmISA::FpRegRegImmOp
class	gem5::ArmISA::FpRegRegRegOp
class	gem5::ArmISA::FpRegRegRegCondOp
class	gem5::ArmISA::FpRegRegRegRegOp
class	gem5::ArmISA::FpRegRegRegImmOp

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::ArmISA

Typedefs
typedef int	gem5::ArmISA::VfpSavedState

Enumerations
enum	gem5::ArmISA::VfpMicroMode { gem5::ArmISA::VfpNotAMicroop , gem5::ArmISA::VfpMicroop , gem5::ArmISA::VfpFirstMicroop , gem5::ArmISA::VfpLastMicroop }
enum	gem5::ArmISA::FeExceptionBit {   gem5::ArmISA::FeDivByZero = FE_DIVBYZERO , gem5::ArmISA::FeInexact = FE_INEXACT , gem5::ArmISA::FeInvalid = FE_INVALID , gem5::ArmISA::FeOverflow = FE_OVERFLOW ,   gem5::ArmISA::FeUnderflow = FE_UNDERFLOW , gem5::ArmISA::FeAllExceptions = FE_ALL_EXCEPT }
enum	gem5::ArmISA::FeRoundingMode { gem5::ArmISA::FeRoundDown = FE_DOWNWARD , gem5::ArmISA::FeRoundNearest = FE_TONEAREST , gem5::ArmISA::FeRoundZero = FE_TOWARDZERO , gem5::ArmISA::FeRoundUpward = FE_UPWARD }
enum	gem5::ArmISA::VfpRoundingMode {   gem5::ArmISA::VfpRoundNearest = 0 , gem5::ArmISA::VfpRoundUpward = 1 , gem5::ArmISA::VfpRoundDown = 2 , gem5::ArmISA::VfpRoundZero = 3 ,   gem5::ArmISA::VfpRoundAway = 4 }

Functions
template<class T >
static void	gem5::ArmISA::setVfpMicroFlags (VfpMicroMode mode, T &flags)
static float	gem5::ArmISA::bitsToFp (uint64_t, float)
static double	gem5::ArmISA::bitsToFp (uint64_t, double)
static uint32_t	gem5::ArmISA::fpToBits (float)
static uint64_t	gem5::ArmISA::fpToBits (double)
template<class fpType >
static bool	gem5::ArmISA::flushToZero (fpType &op)
template<class fpType >
static bool	gem5::ArmISA::flushToZero (fpType &op1, fpType &op2)
template<class fpType >
static void	gem5::ArmISA::vfpFlushToZero (FPSCR &fpscr, fpType &op)
template<class fpType >
static void	gem5::ArmISA::vfpFlushToZero (FPSCR &fpscr, fpType &op1, fpType &op2)
template<class fpType >
static bool	gem5::ArmISA::isSnan (fpType val)
VfpSavedState	gem5::ArmISA::prepFpState (uint32_t rMode)
void	gem5::ArmISA::finishVfp (FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
template<class fpType >
fpType	gem5::ArmISA::fixDest (FPSCR fpscr, fpType val, fpType op1)
template<class fpType >
fpType	gem5::ArmISA::fixDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
template<class fpType >
fpType	gem5::ArmISA::fixDivDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
float	gem5::ArmISA::fixFpDFpSDest (FPSCR fpscr, double val)
double	gem5::ArmISA::fixFpSFpDDest (FPSCR fpscr, float val)
uint16_t	gem5::ArmISA::vcvtFpSFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, float op)
uint16_t	gem5::ArmISA::vcvtFpDFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, double op)
float	gem5::ArmISA::vcvtFpHFpS (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
double	gem5::ArmISA::vcvtFpHFpD (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
static double	gem5::ArmISA::makeDouble (uint32_t low, uint32_t high)
static uint32_t	gem5::ArmISA::lowFromDouble (double val)
static uint32_t	gem5::ArmISA::highFromDouble (double val)
static void	gem5::ArmISA::setFPExceptions (int exceptions)
template<typename T >
uint64_t	gem5::ArmISA::vfpFpToFixed (T val, bool isSigned, uint8_t width, uint8_t imm, bool useRmode=true, VfpRoundingMode roundMode=VfpRoundZero, bool aarch64=false)
float	gem5::ArmISA::vfpUFixedToFpS (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
float	gem5::ArmISA::vfpSFixedToFpS (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
double	gem5::ArmISA::vfpUFixedToFpD (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
double	gem5::ArmISA::vfpSFixedToFpD (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
float	gem5::ArmISA::fprSqrtEstimate (FPSCR &fpscr, float op)
uint32_t	gem5::ArmISA::unsignedRSqrtEstimate (uint32_t op)
float	gem5::ArmISA::fpRecipEstimate (FPSCR &fpscr, float op)
uint32_t	gem5::ArmISA::unsignedRecipEstimate (uint32_t op)
FPSCR	gem5::ArmISA::fpStandardFPSCRValue (const FPSCR &fpscr)
template<typename T >
static T	gem5::ArmISA::fpAdd (T a, T b)
template<typename T >
static T	gem5::ArmISA::fpSub (T a, T b)
static float	gem5::ArmISA::fpAddS (float a, float b)
static double	gem5::ArmISA::fpAddD (double a, double b)
static float	gem5::ArmISA::fpSubS (float a, float b)
static double	gem5::ArmISA::fpSubD (double a, double b)
static float	gem5::ArmISA::fpDivS (float a, float b)
static double	gem5::ArmISA::fpDivD (double a, double b)
template<typename T >
static T	gem5::ArmISA::fpDiv (T a, T b)
template<typename T >
static T	gem5::ArmISA::fpMulX (T a, T b)
template<typename T >
static T	gem5::ArmISA::fpMul (T a, T b)
static float	gem5::ArmISA::fpMulS (float a, float b)
static double	gem5::ArmISA::fpMulD (double a, double b)
template<typename T >
static T	gem5::ArmISA::fpMulAdd (T op1, T op2, T addend)
template<typename T >
static T	gem5::ArmISA::fpRIntX (T a, FPSCR &fpscr)
template<typename T >
static T	gem5::ArmISA::fpMaxNum (T a, T b)
template<typename T >
static T	gem5::ArmISA::fpMax (T a, T b)
template<typename T >
static T	gem5::ArmISA::fpMinNum (T a, T b)
template<typename T >
static T	gem5::ArmISA::fpMin (T a, T b)
template<typename T >
static T	gem5::ArmISA::fpRSqrts (T a, T b)
template<typename T >
static T	gem5::ArmISA::fpRecps (T a, T b)
static float	gem5::ArmISA::fpRSqrtsS (float a, float b)
static float	gem5::ArmISA::fpRecpsS (float a, float b)
template<typename T >
static T	gem5::ArmISA::roundNEven (T a)