gem5  v21.1.0.2
vfp.hh
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37 
38 #ifndef __ARCH_ARM_INSTS_VFP_HH__
39 #define __ARCH_ARM_INSTS_VFP_HH__
40 
41 #include <fenv.h>
42 
43 #include <cmath>
44 
45 #include "arch/arm/insts/misc.hh"
46 #include "arch/arm/regs/misc.hh"
47 
48 namespace gem5
49 {
50 
51 namespace ArmISA
52 {
53 
55 {
60 };
61 
62 template<class T>
63 static inline void
65 {
66  switch (mode) {
67  case VfpMicroop:
68  flags[StaticInst::IsMicroop] = true;
69  break;
70  case VfpFirstMicroop:
71  flags[StaticInst::IsMicroop] =
72  flags[StaticInst::IsFirstMicroop] = true;
73  break;
74  case VfpLastMicroop:
75  flags[StaticInst::IsMicroop] =
76  flags[StaticInst::IsLastMicroop] = true;
77  break;
78  case VfpNotAMicroop:
79  break;
80  }
81  if (mode == VfpMicroop || mode == VfpFirstMicroop) {
82  flags[StaticInst::IsDelayedCommit] = true;
83  }
84 }
85 
87 {
88  FeDivByZero = FE_DIVBYZERO,
89  FeInexact = FE_INEXACT,
90  FeInvalid = FE_INVALID,
91  FeOverflow = FE_OVERFLOW,
92  FeUnderflow = FE_UNDERFLOW,
93  FeAllExceptions = FE_ALL_EXCEPT
94 };
95 
97 {
98  FeRoundDown = FE_DOWNWARD,
99  FeRoundNearest = FE_TONEAREST,
100  FeRoundZero = FE_TOWARDZERO,
101  FeRoundUpward = FE_UPWARD
102 };
103 
105 {
111 };
112 
113 static inline float bitsToFp(uint64_t, float);
114 static inline double bitsToFp(uint64_t, double);
115 static inline uint32_t fpToBits(float);
116 static inline uint64_t fpToBits(double);
117 
118 template <class fpType>
119 static inline bool
120 flushToZero(fpType &op)
121 {
122  fpType junk = 0.0;
123  if (std::fpclassify(op) == FP_SUBNORMAL) {
124  uint64_t bitMask = 0x1ULL << (sizeof(fpType) * 8 - 1);
125  op = bitsToFp(fpToBits(op) & bitMask, junk);
126  return true;
127  }
128  return false;
129 }
130 
131 template <class fpType>
132 static inline bool
133 flushToZero(fpType &op1, fpType &op2)
134 {
135  bool flush1 = flushToZero(op1);
136  bool flush2 = flushToZero(op2);
137  return flush1 || flush2;
138 }
139 
140 template <class fpType>
141 static inline void
142 vfpFlushToZero(FPSCR &fpscr, fpType &op)
143 {
144  if (fpscr.fz == 1 && flushToZero(op)) {
145  fpscr.idc = 1;
146  }
147 }
148 
149 template <class fpType>
150 static inline void
151 vfpFlushToZero(FPSCR &fpscr, fpType &op1, fpType &op2)
152 {
153  vfpFlushToZero(fpscr, op1);
154  vfpFlushToZero(fpscr, op2);
155 }
156 
157 static inline uint32_t
158 fpToBits(float fp)
159 {
160  union
161  {
162  float fp;
163  uint32_t bits;
164  } val;
165  val.fp = fp;
166  return val.bits;
167 }
168 
169 static inline uint64_t
170 fpToBits(double fp)
171 {
172  union
173  {
174  double fp;
175  uint64_t bits;
176  } val;
177  val.fp = fp;
178  return val.bits;
179 }
180 
181 static inline float
182 bitsToFp(uint64_t bits, float junk)
183 {
184  union
185  {
186  float fp;
187  uint32_t bits;
188  } val;
189  val.bits = bits;
190  return val.fp;
191 }
192 
193 static inline double
194 bitsToFp(uint64_t bits, double junk)
195 {
196  union
197  {
198  double fp;
199  uint64_t bits;
200  } val;
201  val.bits = bits;
202  return val.fp;
203 }
204 
205 template <class fpType>
206 static inline bool
207 isSnan(fpType val)
208 {
209  const bool single = (sizeof(fpType) == sizeof(float));
210  const uint64_t qnan =
211  single ? 0x7fc00000 : 0x7ff8000000000000ULL;
212  return std::isnan(val) && ((fpToBits(val) & qnan) != qnan);
213 }
214 
215 typedef int VfpSavedState;
216 
218 void finishVfp(FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask = FpscrExcMask);
219 
220 template <class fpType>
221 fpType fixDest(FPSCR fpscr, fpType val, fpType op1);
222 
223 template <class fpType>
224 fpType fixDest(FPSCR fpscr, fpType val, fpType op1, fpType op2);
225 
226 template <class fpType>
227 fpType fixDivDest(FPSCR fpscr, fpType val, fpType op1, fpType op2);
228 
229 float fixFpDFpSDest(FPSCR fpscr, double val);
230 double fixFpSFpDDest(FPSCR fpscr, float val);
231 
232 uint16_t vcvtFpSFpH(FPSCR &fpscr, bool flush, bool defaultNan,
233  uint32_t rMode, bool ahp, float op);
234 uint16_t vcvtFpDFpH(FPSCR &fpscr, bool flush, bool defaultNan,
235  uint32_t rMode, bool ahp, double op);
236 
237 float vcvtFpHFpS(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op);
238 double vcvtFpHFpD(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op);
239 
240 static inline double
241 makeDouble(uint32_t low, uint32_t high)
242 {
243  double junk = 0.0;
244  return bitsToFp((uint64_t)low | ((uint64_t)high << 32), junk);
245 }
246 
247 static inline uint32_t
249 {
250  return fpToBits(val);
251 }
252 
253 static inline uint32_t
255 {
256  return fpToBits(val) >> 32;
257 }
258 
259 static inline void
260 setFPExceptions(int exceptions) {
261  feclearexcept(FeAllExceptions);
262  feraiseexcept(exceptions);
263 }
264 
265 template <typename T>
266 uint64_t
267 vfpFpToFixed(T val, bool isSigned, uint8_t width, uint8_t imm, bool
268  useRmode = true, VfpRoundingMode roundMode = VfpRoundZero,
269  bool aarch64 = false)
270 {
271  int rmode;
272  bool roundAwayFix = false;
273 
274  if (!useRmode) {
275  rmode = fegetround();
276  } else {
277  switch (roundMode)
278  {
279  case VfpRoundNearest:
280  rmode = FeRoundNearest;
281  break;
282  case VfpRoundUpward:
283  rmode = FeRoundUpward;
284  break;
285  case VfpRoundDown:
286  rmode = FeRoundDown;
287  break;
288  case VfpRoundZero:
289  rmode = FeRoundZero;
290  break;
291  case VfpRoundAway:
292  // There is no equivalent rounding mode, use round down and we'll
293  // fix it later
294  rmode = FeRoundDown;
295  roundAwayFix = true;
296  break;
297  default:
298  panic("Unsupported roundMode %d\n", roundMode);
299  }
300  }
301  __asm__ __volatile__("" : "=m" (rmode) : "m" (rmode));
302  fesetround(FeRoundNearest);
303  val = val * pow(2.0, imm);
304  __asm__ __volatile__("" : "=m" (val) : "m" (val));
305  fesetround(rmode);
306  feclearexcept(FeAllExceptions);
307  __asm__ __volatile__("" : "=m" (val) : "m" (val));
308  T origVal = val;
309  val = rint(val);
310  __asm__ __volatile__("" : "=m" (val) : "m" (val));
311 
312  int exceptions = fetestexcept(FeAllExceptions);
313 
314  int fpType = std::fpclassify(val);
315  if (fpType == FP_SUBNORMAL || fpType == FP_NAN) {
316  if (fpType == FP_NAN) {
317  exceptions |= FeInvalid;
318  }
319  val = 0.0;
320  } else if (origVal != val) {
321  switch (rmode) {
322  case FeRoundNearest:
323  if (origVal - val > 0.5)
324  val += 1.0;
325  else if (val - origVal > 0.5)
326  val -= 1.0;
327  break;
328  case FeRoundDown:
329  if (roundAwayFix) {
330  // The ordering on the subtraction looks a bit odd in that we
331  // don't do the obvious origVal - val, instead we do
332  // -(val - origVal). This is required to get the corruct bit
333  // exact behaviour when very close to the 0.5 threshold.
334  volatile T error = val;
335  error -= origVal;
336  error = -error;
337  if ( (error > 0.5) ||
338  ((error == 0.5) && (val >= 0)) )
339  val += 1.0;
340  } else {
341  if (origVal < val)
342  val -= 1.0;
343  }
344  break;
345  case FeRoundUpward:
346  if (origVal > val)
347  val += 1.0;
348  break;
349  }
350  exceptions |= FeInexact;
351  }
352 
353  __asm__ __volatile__("" : "=m" (val) : "m" (val));
354 
355  if (isSigned) {
356  bool outOfRange = false;
357  int64_t result = (int64_t) val;
358  uint64_t finalVal;
359 
360  if (!aarch64) {
361  if (width == 16) {
362  finalVal = (int16_t)val;
363  } else if (width == 32) {
364  finalVal =(int32_t)val;
365  } else if (width == 64) {
366  finalVal = result;
367  } else {
368  panic("Unsupported width %d\n", width);
369  }
370 
371  // check if value is in range
372  int64_t minVal = ~mask(width-1);
373  if ((double)val < minVal) {
374  outOfRange = true;
375  finalVal = minVal;
376  }
377  int64_t maxVal = mask(width-1);
378  if ((double)val > maxVal) {
379  outOfRange = true;
380  finalVal = maxVal;
381  }
382  } else {
383  bool isNeg = val < 0;
384  finalVal = result & mask(width);
385  // If the result is supposed to be less than 64 bits check that the
386  // upper bits that got thrown away are just sign extension bits
387  if (width != 64) {
388  outOfRange = ((uint64_t) result >> (width - 1)) !=
389  (isNeg ? mask(64-width+1) : 0);
390  }
391  // Check if the original floating point value doesn't matches the
392  // integer version we are also out of range. So create a saturated
393  // result.
394  if (isNeg) {
395  outOfRange |= val < result;
396  if (outOfRange) {
397  finalVal = 1LL << (width-1);
398  }
399  } else {
400  outOfRange |= val > result;
401  if (outOfRange) {
402  finalVal = mask(width-1);
403  }
404  }
405  }
406 
407  // Raise an exception if the value was out of range
408  if (outOfRange) {
409  exceptions |= FeInvalid;
410  exceptions &= ~FeInexact;
411  }
412  setFPExceptions(exceptions);
413  return finalVal;
414  } else {
415  if ((double)val < 0) {
416  exceptions |= FeInvalid;
417  exceptions &= ~FeInexact;
418  setFPExceptions(exceptions);
419  return 0;
420  }
421 
422  uint64_t result = ((uint64_t) val) & mask(width);
423  if (val > result) {
424  exceptions |= FeInvalid;
425  exceptions &= ~FeInexact;
426  setFPExceptions(exceptions);
427  return mask(width);
428  }
429 
430  setFPExceptions(exceptions);
431  return result;
432  }
433 };
434 
435 
436 float vfpUFixedToFpS(bool flush, bool defaultNan,
437  uint64_t val, uint8_t width, uint8_t imm);
438 float vfpSFixedToFpS(bool flush, bool defaultNan,
439  int64_t val, uint8_t width, uint8_t imm);
440 
441 double vfpUFixedToFpD(bool flush, bool defaultNan,
442  uint64_t val, uint8_t width, uint8_t imm);
443 double vfpSFixedToFpD(bool flush, bool defaultNan,
444  int64_t val, uint8_t width, uint8_t imm);
445 
446 float fprSqrtEstimate(FPSCR &fpscr, float op);
447 uint32_t unsignedRSqrtEstimate(uint32_t op);
448 
449 float fpRecipEstimate(FPSCR &fpscr, float op);
450 uint32_t unsignedRecipEstimate(uint32_t op);
451 
452 FPSCR
453 fpStandardFPSCRValue(const FPSCR &fpscr);
454 
455 class VfpMacroOp : public PredMacroOp
456 {
457  public:
458  static bool
459  inScalarBank(IntRegIndex idx)
460  {
461  return (idx % 32) < 8;
462  }
463 
464  protected:
465  bool wide;
466 
467  VfpMacroOp(const char *mnem, ExtMachInst _machInst,
468  OpClass __opClass, bool _wide) :
469  PredMacroOp(mnem, _machInst, __opClass), wide(_wide)
470  {}
471 
472  IntRegIndex addStride(IntRegIndex idx, unsigned stride);
473  void nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2);
474  void nextIdxs(IntRegIndex &dest, IntRegIndex &op1);
475  void nextIdxs(IntRegIndex &dest);
476 };
477 
478 template <typename T>
479 static inline T
480 fpAdd(T a, T b)
481 {
482  return a + b;
483 };
484 
485 template <typename T>
486 static inline T
487 fpSub(T a, T b)
488 {
489  return a - b;
490 };
491 
492 static inline float
493 fpAddS(float a, float b)
494 {
495  return a + b;
496 }
497 
498 static inline double
499 fpAddD(double a, double b)
500 {
501  return a + b;
502 }
503 
504 static inline float
505 fpSubS(float a, float b)
506 {
507  return a - b;
508 }
509 
510 static inline double
511 fpSubD(double a, double b)
512 {
513  return a - b;
514 }
515 
516 static inline float
517 fpDivS(float a, float b)
518 {
519  return a / b;
520 }
521 
522 static inline double
523 fpDivD(double a, double b)
524 {
525  return a / b;
526 }
527 
528 template <typename T>
529 static inline T
530 fpDiv(T a, T b)
531 {
532  return a / b;
533 };
534 
535 template <typename T>
536 static inline T
537 fpMulX(T a, T b)
538 {
539  uint64_t opData;
540  uint32_t sign1;
541  uint32_t sign2;
542  const bool single = (sizeof(T) == sizeof(float));
543  if (single) {
544  opData = (fpToBits(a));
545  sign1 = opData>>31;
546  opData = (fpToBits(b));
547  sign2 = opData>>31;
548  } else {
549  opData = (fpToBits(a));
550  sign1 = opData>>63;
551  opData = (fpToBits(b));
552  sign2 = opData>>63;
553  }
554  bool inf1 = (std::fpclassify(a) == FP_INFINITE);
555  bool inf2 = (std::fpclassify(b) == FP_INFINITE);
556  bool zero1 = (std::fpclassify(a) == FP_ZERO);
557  bool zero2 = (std::fpclassify(b) == FP_ZERO);
558  if ((inf1 && zero2) || (zero1 && inf2)) {
559  if (sign1 ^ sign2)
560  return (T)(-2.0);
561  else
562  return (T)(2.0);
563  } else {
564  return (a * b);
565  }
566 };
567 
568 
569 template <typename T>
570 static inline T
571 fpMul(T a, T b)
572 {
573  return a * b;
574 };
575 
576 static inline float
577 fpMulS(float a, float b)
578 {
579  return a * b;
580 }
581 
582 static inline double
583 fpMulD(double a, double b)
584 {
585  return a * b;
586 }
587 
588 template <typename T>
589 static inline T
590 // @todo remove this when all calls to it have been replaced with the new fplib implementation
591 fpMulAdd(T op1, T op2, T addend)
592 {
593  T result;
594 
595  if (sizeof(T) == sizeof(float))
596  result = fmaf(op1, op2, addend);
597  else
598  result = fma(op1, op2, addend);
599 
600  // ARM doesn't generate signed nan's from this opperation, so fix up the result
601  if (std::isnan(result) && !std::isnan(op1) &&
602  !std::isnan(op2) && !std::isnan(addend))
603  {
604  uint64_t bitMask = 0x1ULL << ((sizeof(T) * 8) - 1);
605  result = bitsToFp(fpToBits(result) & ~bitMask, op1);
606  }
607  return result;
608 }
609 
610 template <typename T>
611 static inline T
612 fpRIntX(T a, FPSCR &fpscr)
613 {
614  T rVal;
615 
616  rVal = rint(a);
617  if (rVal != a && !std::isnan(a))
618  fpscr.ixc = 1;
619  return (rVal);
620 };
621 
622 template <typename T>
623 static inline T
624 fpMaxNum(T a, T b)
625 {
626  const bool single = (sizeof(T) == sizeof(float));
627  const uint64_t qnan = single ? 0x7fc00000 : 0x7ff8000000000000ULL;
628 
629  if (std::isnan(a))
630  return ((fpToBits(a) & qnan) == qnan) ? b : a;
631  if (std::isnan(b))
632  return ((fpToBits(b) & qnan) == qnan) ? a : b;
633  // Handle comparisons of +0 and -0.
634  if (!std::signbit(a) && std::signbit(b))
635  return a;
636  return fmax(a, b);
637 };
638 
639 template <typename T>
640 static inline T
641 fpMax(T a, T b)
642 {
643  if (std::isnan(a))
644  return a;
645  if (std::isnan(b))
646  return b;
647  return fpMaxNum<T>(a, b);
648 };
649 
650 template <typename T>
651 static inline T
652 fpMinNum(T a, T b)
653 {
654  const bool single = (sizeof(T) == sizeof(float));
655  const uint64_t qnan = single ? 0x7fc00000 : 0x7ff8000000000000ULL;
656 
657  if (std::isnan(a))
658  return ((fpToBits(a) & qnan) == qnan) ? b : a;
659  if (std::isnan(b))
660  return ((fpToBits(b) & qnan) == qnan) ? a : b;
661  // Handle comparisons of +0 and -0.
662  if (std::signbit(a) && !std::signbit(b))
663  return a;
664  return fmin(a, b);
665 };
666 
667 template <typename T>
668 static inline T
669 fpMin(T a, T b)
670 {
671  if (std::isnan(a))
672  return a;
673  if (std::isnan(b))
674  return b;
675  return fpMinNum<T>(a, b);
676 };
677 
678 template <typename T>
679 static inline T
680 fpRSqrts(T a, T b)
681 {
682  int fpClassA = std::fpclassify(a);
683  int fpClassB = std::fpclassify(b);
684  T aXb;
685  int fpClassAxB;
686 
687  if ((fpClassA == FP_ZERO && fpClassB == FP_INFINITE) ||
688  (fpClassA == FP_INFINITE && fpClassB == FP_ZERO)) {
689  return 1.5;
690  }
691  aXb = a*b;
692  fpClassAxB = std::fpclassify(aXb);
693  if (fpClassAxB == FP_SUBNORMAL) {
694  feraiseexcept(FeUnderflow);
695  return 1.5;
696  }
697  return (3.0 - (a * b)) / 2.0;
698 };
699 
700 template <typename T>
701 static inline T
702 fpRecps(T a, T b)
703 {
704  int fpClassA = std::fpclassify(a);
705  int fpClassB = std::fpclassify(b);
706  T aXb;
707  int fpClassAxB;
708 
709  if ((fpClassA == FP_ZERO && fpClassB == FP_INFINITE) ||
710  (fpClassA == FP_INFINITE && fpClassB == FP_ZERO)) {
711  return 2.0;
712  }
713  aXb = a*b;
714  fpClassAxB = std::fpclassify(aXb);
715  if (fpClassAxB == FP_SUBNORMAL) {
716  feraiseexcept(FeUnderflow);
717  return 2.0;
718  }
719  return 2.0 - (a * b);
720 };
721 
722 
723 static inline float
724 fpRSqrtsS(float a, float b)
725 {
726  int fpClassA = std::fpclassify(a);
727  int fpClassB = std::fpclassify(b);
728  float aXb;
729  int fpClassAxB;
730 
731  if ((fpClassA == FP_ZERO && fpClassB == FP_INFINITE) ||
732  (fpClassA == FP_INFINITE && fpClassB == FP_ZERO)) {
733  return 1.5;
734  }
735  aXb = a*b;
736  fpClassAxB = std::fpclassify(aXb);
737  if (fpClassAxB == FP_SUBNORMAL) {
738  feraiseexcept(FeUnderflow);
739  return 1.5;
740  }
741  return (3.0 - (a * b)) / 2.0;
742 }
743 
744 static inline float
745 fpRecpsS(float a, float b)
746 {
747  int fpClassA = std::fpclassify(a);
748  int fpClassB = std::fpclassify(b);
749  float aXb;
750  int fpClassAxB;
751 
752  if ((fpClassA == FP_ZERO && fpClassB == FP_INFINITE) ||
753  (fpClassA == FP_INFINITE && fpClassB == FP_ZERO)) {
754  return 2.0;
755  }
756  aXb = a*b;
757  fpClassAxB = std::fpclassify(aXb);
758  if (fpClassAxB == FP_SUBNORMAL) {
759  feraiseexcept(FeUnderflow);
760  return 2.0;
761  }
762  return 2.0 - (a * b);
763 }
764 
765 template <typename T>
766 static inline T
768  T val;
769 
770  val = round(a);
771  if (a - val == 0.5) {
772  if ( (((int) a) & 1) == 0 ) val += 1.0;
773  }
774  else if (a - val == -0.5) {
775  if ( (((int) a) & 1) == 0 ) val -= 1.0;
776  }
777  return val;
778 }
779 
780 
781 
782 class FpOp : public PredOp
783 {
784  protected:
785  FpOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
786  PredOp(mnem, _machInst, __opClass)
787  {}
788 
789  virtual float
790  doOp(float op1, float op2) const
791  {
792  panic("Unimplemented version of doOp called.\n");
793  }
794 
795  virtual float
796  doOp(float op1) const
797  {
798  panic("Unimplemented version of doOp called.\n");
799  }
800 
801  virtual double
802  doOp(double op1, double op2) const
803  {
804  panic("Unimplemented version of doOp called.\n");
805  }
806 
807  virtual double
808  doOp(double op1) const
809  {
810  panic("Unimplemented version of doOp called.\n");
811  }
812 
813  double
814  dbl(uint32_t low, uint32_t high) const
815  {
816  double junk = 0.0;
817  return bitsToFp((uint64_t)low | ((uint64_t)high << 32), junk);
818  }
819 
820  uint32_t
821  dblLow(double val) const
822  {
823  return fpToBits(val);
824  }
825 
826  uint32_t
827  dblHi(double val) const
828  {
829  return fpToBits(val) >> 32;
830  }
831 
832  template <class fpType>
833  fpType
834  processNans(FPSCR &fpscr, bool &done, bool defaultNan,
835  fpType op1, fpType op2) const;
836 
837  template <class fpType>
838  fpType
839  ternaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType op3,
840  fpType (*func)(fpType, fpType, fpType),
841  bool flush, bool defaultNan, uint32_t rMode) const;
842 
843  template <class fpType>
844  fpType
845  binaryOp(FPSCR &fpscr, fpType op1, fpType op2,
846  fpType (*func)(fpType, fpType),
847  bool flush, bool defaultNan, uint32_t rMode) const;
848 
849  template <class fpType>
850  fpType
851  unaryOp(FPSCR &fpscr, fpType op1,
852  fpType (*func)(fpType),
853  bool flush, uint32_t rMode) const;
854 
855  void
856  advancePC(PCState &pcState) const override
857  {
858  if (flags[IsLastMicroop]) {
859  pcState.uEnd();
860  } else if (flags[IsMicroop]) {
861  pcState.uAdvance();
862  } else {
863  pcState.advance();
864  }
865  }
866 
867  float
868  fpSqrt (FPSCR fpscr,float x) const
869  {
870 
871  return unaryOp(fpscr,x,sqrtf,fpscr.fz,fpscr.rMode);
872 
873  }
874 
875  double
876  fpSqrt (FPSCR fpscr,double x) const
877  {
878 
879  return unaryOp(fpscr,x,sqrt,fpscr.fz,fpscr.rMode);
880 
881  }
882 };
883 
884 class FpCondCompRegOp : public FpOp
885 {
886  protected:
887  IntRegIndex op1, op2;
889  uint8_t defCc;
890 
891  FpCondCompRegOp(const char *mnem, ExtMachInst _machInst,
892  OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2,
893  ConditionCode _condCode, uint8_t _defCc) :
894  FpOp(mnem, _machInst, __opClass),
895  op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
896  {}
897 
898  std::string generateDisassembly(
899  Addr pc, const loader::SymbolTable *symtab) const override;
900 };
901 
902 class FpCondSelOp : public FpOp
903 {
904  protected:
905  IntRegIndex dest, op1, op2;
907 
908  FpCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
909  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
910  ConditionCode _condCode) :
911  FpOp(mnem, _machInst, __opClass),
912  dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
913  {}
914 
915  std::string generateDisassembly(
916  Addr pc, const loader::SymbolTable *symtab) const override;
917 };
918 
919 class FpRegRegOp : public FpOp
920 {
921  protected:
922  IntRegIndex dest;
923  IntRegIndex op1;
924 
925  FpRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
926  IntRegIndex _dest, IntRegIndex _op1,
928  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
929  {
931  }
932 
933  std::string generateDisassembly(
934  Addr pc, const loader::SymbolTable *symtab) const override;
935 };
936 
937 class FpRegImmOp : public FpOp
938 {
939  protected:
940  IntRegIndex dest;
941  uint64_t imm;
942 
943  FpRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
944  IntRegIndex _dest, uint64_t _imm,
946  FpOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
947  {
949  }
950 
951  std::string generateDisassembly(
952  Addr pc, const loader::SymbolTable *symtab) const override;
953 };
954 
955 class FpRegRegImmOp : public FpOp
956 {
957  protected:
958  IntRegIndex dest;
959  IntRegIndex op1;
960  uint64_t imm;
961 
962  FpRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
963  IntRegIndex _dest, IntRegIndex _op1,
964  uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop) :
965  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), imm(_imm)
966  {
968  }
969 
970  std::string generateDisassembly(
971  Addr pc, const loader::SymbolTable *symtab) const override;
972 };
973 
974 class FpRegRegRegOp : public FpOp
975 {
976  protected:
977  IntRegIndex dest;
978  IntRegIndex op1;
979  IntRegIndex op2;
980 
981  FpRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
982  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
984  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2)
985  {
987  }
988 
989  std::string generateDisassembly(
990  Addr pc, const loader::SymbolTable *symtab) const override;
991 };
992 
993 class FpRegRegRegCondOp : public FpOp
994 {
995  protected:
996  IntRegIndex dest;
997  IntRegIndex op1;
998  IntRegIndex op2;
1000 
1001  FpRegRegRegCondOp(const char *mnem, ExtMachInst _machInst,
1002  OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
1003  IntRegIndex _op2, ConditionCode _cond,
1005  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2),
1006  cond(_cond)
1007  {
1009  }
1010 
1011  std::string generateDisassembly(
1012  Addr pc, const loader::SymbolTable *symtab) const override;
1013 };
1014 
1015 class FpRegRegRegRegOp : public FpOp
1016 {
1017  protected:
1018  IntRegIndex dest;
1019  IntRegIndex op1;
1020  IntRegIndex op2;
1021  IntRegIndex op3;
1022 
1023  FpRegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
1024  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
1025  IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop) :
1026  FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2),
1027  op3(_op3)
1028  {
1030  }
1031 
1032  std::string generateDisassembly(
1033  Addr pc, const loader::SymbolTable *symtab) const override;
1034 };
1035 
1036 class FpRegRegRegImmOp : public FpOp
1037 {
1038  protected:
1039  IntRegIndex dest;
1040  IntRegIndex op1;
1041  IntRegIndex op2;
1042  uint64_t imm;
1043 
1044  FpRegRegRegImmOp(const char *mnem, ExtMachInst _machInst,
1045  OpClass __opClass, IntRegIndex _dest,
1046  IntRegIndex _op1, IntRegIndex _op2,
1047  uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop) :
1048  FpOp(mnem, _machInst, __opClass),
1049  dest(_dest), op1(_op1), op2(_op2), imm(_imm)
1050  {
1052  }
1053 
1054  std::string generateDisassembly(
1055  Addr pc, const loader::SymbolTable *symtab) const override;
1056 };
1057 
1058 } // namespace ArmISA
1059 } // namespace gem5
1060 
1061 #endif //__ARCH_ARM_INSTS_VFP_HH__
gem5::ArmISA::unsignedRSqrtEstimate
uint32_t unsignedRSqrtEstimate(uint32_t op)
Definition: vfp.cc:814
gem5::ArmISA::VfpRoundNearest
@ VfpRoundNearest
Definition: vfp.hh:106
gem5::ArmISA::FpOp::binaryOp
fpType binaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType(*func)(fpType, fpType), bool flush, bool defaultNan, uint32_t rMode) const
Definition: vfp.cc:1039
gem5::ArmISA::FpOp::FpOp
FpOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: vfp.hh:785
gem5::ArmISA::VfpMacroOp
Definition: vfp.hh:455
gem5::ArmISA::FpRegRegRegRegOp::op1
IntRegIndex op1
Definition: vfp.hh:1019
gem5::ArmISA::fpDiv
static T fpDiv(T a, T b)
Definition: vfp.hh:530
gem5::ArmISA::FpRegRegRegOp
Definition: vfp.hh:974
gem5::ArmISA::fpMinNum
static T fpMinNum(T a, T b)
Definition: vfp.hh:652
gem5::ArmISA::FpRegRegRegRegOp::dest
IntRegIndex dest
Definition: vfp.hh:1018
gem5::ArmISA::FeExceptionBit
FeExceptionBit
Definition: vfp.hh:86
gem5::ArmISA::fpRecps
static T fpRecps(T a, T b)
Definition: vfp.hh:702
misc.hh
gem5::ArmISA::bitsToFp
static float bitsToFp(uint64_t, float)
Definition: vfp.hh:182
gem5::ArmISA::vfpUFixedToFpS
float vfpUFixedToFpS(bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
Definition: vfp.cc:675
gem5::ArmISA::fixFpDFpSDest
float fixFpDFpSDest(FPSCR fpscr, double val)
Definition: vfp.cc:337
gem5::ArmISA::FpOp::fpSqrt
double fpSqrt(FPSCR fpscr, double x) const
Definition: vfp.hh:876
gem5::ArmISA::fprSqrtEstimate
float fprSqrtEstimate(FPSCR &fpscr, float op)
Definition: vfp.cc:771
gem5::ArmISA::FpRegRegRegRegOp
Definition: vfp.hh:1015
gem5::ArmISA::FpOp
Definition: vfp.hh:782
gem5::ArmISA::FpCondSelOp::dest
IntRegIndex dest
Definition: vfp.hh:905
gem5::ArmISA::setVfpMicroFlags
static void setVfpMicroFlags(VfpMicroMode mode, T &flags)
Definition: vfp.hh:64
gem5::ArmISA::fpRSqrtsS
static float fpRSqrtsS(float a, float b)
Definition: vfp.hh:724
gem5::ArmISA::FpOp::dbl
double dbl(uint32_t low, uint32_t high) const
Definition: vfp.hh:814
gem5::ArmISA::aarch64
Bitfield< 34 > aarch64
Definition: types.hh:81
gem5::ArmISA::fpMaxNum
static T fpMaxNum(T a, T b)
Definition: vfp.hh:624
gem5::ArmISA::FpRegRegImmOp::FpRegRegImmOp
FpRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:962
gem5::ArmISA::FpCondCompRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:52
gem5::ArmISA::VfpRoundDown
@ VfpRoundDown
Definition: vfp.hh:108
gem5::ArmISA::fpMulS
static float fpMulS(float a, float b)
Definition: vfp.hh:577
gem5::ArmISA::FpRegRegRegCondOp
Definition: vfp.hh:993
gem5::ArmISA::fpSubD
static double fpSubD(double a, double b)
Definition: vfp.hh:511
gem5::ArmISA::fpAdd
static T fpAdd(T a, T b)
Definition: vfp.hh:480
gem5::ArmISA::FeRoundDown
@ FeRoundDown
Definition: vfp.hh:98
gem5::ArmISA::FeOverflow
@ FeOverflow
Definition: vfp.hh:91
gem5::ArmISA::FpRegRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:165
gem5::ArmISA::FpOp::dblHi
uint32_t dblHi(double val) const
Definition: vfp.hh:827
gem5::ArmISA::FpCondSelOp::op2
IntRegIndex op2
Definition: vfp.hh:905
gem5::ArmISA::VfpFirstMicroop
@ VfpFirstMicroop
Definition: vfp.hh:58
gem5::ArmISA::FeUnderflow
@ FeUnderflow
Definition: vfp.hh:92
gem5::ArmISA::fpRSqrts
static T fpRSqrts(T a, T b)
Definition: vfp.hh:680
gem5::ArmISA::FpRegRegRegCondOp::cond
ConditionCode cond
Definition: vfp.hh:999
gem5::ArmISA::FeRoundingMode
FeRoundingMode
Definition: vfp.hh:96
gem5::ArmISA::FpCondCompRegOp::op2
IntRegIndex op2
Definition: vfp.hh:887
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::setFPExceptions
static void setFPExceptions(int exceptions)
Definition: vfp.hh:260
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::ArmISA::vfpFpToFixed
uint64_t vfpFpToFixed(T val, bool isSigned, uint8_t width, uint8_t imm, bool useRmode=true, VfpRoundingMode roundMode=VfpRoundZero, bool aarch64=false)
Definition: vfp.hh:267
gem5::ArmISA::fpAddD
static double fpAddD(double a, double b)
Definition: vfp.hh:499
gem5::ArmISA::FpCondCompRegOp::op1
IntRegIndex op1
Definition: vfp.hh:887
gem5::ArmISA::FpRegRegRegCondOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:133
gem5::ArmISA::FeDivByZero
@ FeDivByZero
Definition: vfp.hh:88
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::FpCondCompRegOp::defCc
uint8_t defCc
Definition: vfp.hh:889
gem5::ArmISA::vfpFlushToZero
static void vfpFlushToZero(FPSCR &fpscr, fpType &op)
Definition: vfp.hh:142
gem5::ArmISA::ahp
Bitfield< 26 > ahp
Definition: misc_types.hh:450
gem5::ArmISA::FpRegRegRegOp::dest
IntRegIndex dest
Definition: vfp.hh:977
gem5::ArmISA::FpRegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:119
gem5::ArmISA::FpRegRegRegOp::FpRegRegRegOp
FpRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:981
gem5::ArmISA::FpOp::advancePC
void advancePC(PCState &pcState) const override
Definition: vfp.hh:856
gem5::ArmISA::FeAllExceptions
@ FeAllExceptions
Definition: vfp.hh:93
gem5::ArmISA::fpSubS
static float fpSubS(float a, float b)
Definition: vfp.hh:505
gem5::ArmISA::VfpMacroOp::wide
bool wide
Definition: vfp.hh:465
gem5::ArmISA::vfpSFixedToFpS
float vfpSFixedToFpS(bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
Definition: vfp.cc:693
gem5::ArmISA::fp
Bitfield< 19, 16 > fp
Definition: misc_types.hh:176
gem5::ArmISA::FpRegRegImmOp::op1
IntRegIndex op1
Definition: vfp.hh:959
gem5::ArmISA::FpscrExcMask
static const uint32_t FpscrExcMask
Definition: misc.hh:2213
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::FpRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:83
gem5::ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp
FpRegRegRegCondOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _cond, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:1001
gem5::ArmISA::FpOp::doOp
virtual float doOp(float op1) const
Definition: vfp.hh:796
gem5::ArmISA::FpRegRegImmOp
Definition: vfp.hh:955
gem5::ArmISA::FpRegImmOp::imm
uint64_t imm
Definition: vfp.hh:941
gem5::ArmISA::FpOp::processNans
fpType processNans(FPSCR &fpscr, bool &done, bool defaultNan, fpType op1, fpType op2) const
Definition: vfp.cc:917
gem5::ArmISA::FeRoundUpward
@ FeRoundUpward
Definition: vfp.hh:101
gem5::ArmISA::FpRegImmOp::FpRegImmOp
FpRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:943
gem5::ArmISA::VfpRoundingMode
VfpRoundingMode
Definition: vfp.hh:104
gem5::ArmISA::finishVfp
void finishVfp(FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
Definition: vfp.cc:205
gem5::ArmISA::VfpMacroOp::VfpMacroOp
VfpMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, bool _wide)
Definition: vfp.hh:467
gem5::ArmISA::FpCondSelOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:67
gem5::ArmISA::FpRegRegImmOp::imm
uint64_t imm
Definition: vfp.hh:960
gem5::ArmISA::fpDivS
static float fpDivS(float a, float b)
Definition: vfp.hh:517
gem5::ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp
FpRegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:1023
gem5::ArmISA::FpCondSelOp::op1
IntRegIndex op1
Definition: vfp.hh:905
gem5::ArmISA::fpMax
static T fpMax(T a, T b)
Definition: vfp.hh:641
gem5::ArmISA::FeInexact
@ FeInexact
Definition: vfp.hh:89
gem5::high
high
Definition: intmath.hh:176
gem5::ArmISA::makeDouble
static double makeDouble(uint32_t low, uint32_t high)
Definition: vfp.hh:241
gem5::ArmISA::vfpUFixedToFpD
double vfpUFixedToFpD(bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
Definition: vfp.cc:713
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
gem5::ArmISA::fpMin
static T fpMin(T a, T b)
Definition: vfp.hh:669
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:71
gem5::ArmISA::vcvtFpSFpH
uint16_t vcvtFpSFpH(FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, float op)
Definition: vfp.cc:577
gem5::ArmISA::FpCondCompRegOp::FpCondCompRegOp
FpCondCompRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode, uint8_t _defCc)
Definition: vfp.hh:891
gem5::ArmISA::FpCondSelOp
Definition: vfp.hh:902
gem5::ArmISA::FpRegRegRegCondOp::op1
IntRegIndex op1
Definition: vfp.hh:997
gem5::ArmISA::FpRegRegRegOp::op1
IntRegIndex op1
Definition: vfp.hh:978
gem5::ArmISA::VfpMicroop
@ VfpMicroop
Definition: vfp.hh:57
gem5::ArmISA::vcvtFpHFpS
float vcvtFpHFpS(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
Definition: vfp.cc:665
gem5::ArmISA::FpOp::doOp
virtual float doOp(float op1, float op2) const
Definition: vfp.hh:790
gem5::ArmISA::FpCondSelOp::FpCondSelOp
FpCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode)
Definition: vfp.hh:908
gem5::ArmISA::fpMulAdd
static T fpMulAdd(T op1, T op2, T addend)
Definition: vfp.hh:591
gem5::ArmISA::FpRegRegRegRegOp::op3
IntRegIndex op3
Definition: vfp.hh:1021
gem5::ArmISA::FpCondSelOp::condCode
ConditionCode condCode
Definition: vfp.hh:906
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::ArmISA::VfpMacroOp::addStride
IntRegIndex addStride(IntRegIndex idx, unsigned stride)
Definition: vfp.cc:1167
gem5::ArmISA::VfpRoundUpward
@ VfpRoundUpward
Definition: vfp.hh:107
gem5::ArmISA::FpOp::dblLow
uint32_t dblLow(double val) const
Definition: vfp.hh:821
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::fpAddS
static float fpAddS(float a, float b)
Definition: vfp.hh:493
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::vfpSFixedToFpD
double vfpSFixedToFpD(bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
Definition: vfp.cc:732
gem5::ArmISA::VfpMacroOp::nextIdxs
void nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2)
Definition: vfp.cc:1180
gem5::ArmISA::fpRIntX
static T fpRIntX(T a, FPSCR &fpscr)
Definition: vfp.hh:612
gem5::ArmISA::VfpSavedState
int VfpSavedState
Definition: vfp.hh:215
gem5::ArmISA::FpRegRegRegImmOp::imm
uint64_t imm
Definition: vfp.hh:1042
gem5::ArmISA::FpRegRegRegRegOp::op2
IntRegIndex op2
Definition: vfp.hh:1020
gem5::ArmISA::FeInvalid
@ FeInvalid
Definition: vfp.hh:90
gem5::ArmISA::VfpRoundAway
@ VfpRoundAway
Definition: vfp.hh:110
gem5::ArmISA::vcvtFpHFpD
double vcvtFpHFpD(FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
Definition: vfp.cc:655
gem5::ArmISA::fpToBits
static uint32_t fpToBits(float)
Definition: vfp.hh:158
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::VfpLastMicroop
@ VfpLastMicroop
Definition: vfp.hh:59
gem5::ArmISA::FpRegRegRegImmOp::op2
IntRegIndex op2
Definition: vfp.hh:1041
gem5::ArmISA::fpMul
static T fpMul(T a, T b)
Definition: vfp.hh:571
gem5::ArmISA::roundNEven
static T roundNEven(T a)
Definition: vfp.hh:767
gem5::ArmISA::FpRegRegRegCondOp::op2
IntRegIndex op2
Definition: vfp.hh:998
gem5::ArmISA::VfpMicroMode
VfpMicroMode
Definition: vfp.hh:54
gem5::ArmISA::FpRegRegRegCondOp::dest
IntRegIndex dest
Definition: vfp.hh:996
gem5::ArmISA::VfpMacroOp::inScalarBank
static bool inScalarBank(IntRegIndex idx)
Definition: vfp.hh:459
gem5::ArmISA::PredMacroOp
Base class for predicated macro-operations.
Definition: pred_inst.hh:340
gem5::ArmISA::FpOp::doOp
virtual double doOp(double op1) const
Definition: vfp.hh:808
gem5::ArmISA::fixDivDest
fpType fixDivDest(bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
Definition: vfp.cc:302
gem5::GenericISA::SimplePCState::advance
void advance()
Definition: types.hh:181
gem5::ArmISA::FpRegRegRegOp::op2
IntRegIndex op2
Definition: vfp.hh:979
gem5::ArmISA::FpRegRegRegImmOp::dest
IntRegIndex dest
Definition: vfp.hh:1039
gem5::ArmISA::FpRegRegOp
Definition: vfp.hh:919
gem5::ArmISA::fpMulX
static T fpMulX(T a, T b)
Definition: vfp.hh:537
gem5::ArmISA::FpOp::doOp
virtual double doOp(double op1, double op2) const
Definition: vfp.hh:802
gem5::ArmISA::fpRecipEstimate
float fpRecipEstimate(FPSCR &fpscr, float op)
Definition: vfp.cc:853
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::highFromDouble
static uint32_t highFromDouble(double val)
Definition: vfp.hh:254
gem5::ArmISA::FpRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:106
gem5::ArmISA::prepFpState
VfpSavedState prepFpState(uint32_t rMode)
Definition: vfp.cc:183
gem5::ArmISA::FpRegRegRegImmOp
Definition: vfp.hh:1036
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::ArmISA::flushToZero
flushToZero
Definition: misc_types.hh:476
gem5::ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp
FpRegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:1044
gem5::ArmISA::fpSub
static T fpSub(T a, T b)
Definition: vfp.hh:487
gem5::ArmISA::FeRoundNearest
@ FeRoundNearest
Definition: vfp.hh:99
gem5::ArmISA::FpRegRegOp::dest
IntRegIndex dest
Definition: vfp.hh:922
gem5::ArmISA::FpRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:95
gem5::ArmISA::VfpRoundZero
@ VfpRoundZero
Definition: vfp.hh:109
gem5::ArmISA::fpMulD
static double fpMulD(double a, double b)
Definition: vfp.hh:583
misc.hh
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
gem5::ArmISA::FpOp::unaryOp
fpType unaryOp(FPSCR &fpscr, fpType op1, fpType(*func)(fpType), bool flush, uint32_t rMode) const
Definition: vfp.cc:1110
gem5::ArmISA::FeRoundZero
@ FeRoundZero
Definition: vfp.hh:100
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::fpStandardFPSCRValue
FPSCR fpStandardFPSCRValue(const FPSCR &fpscr)
Definition: vfp.cc:905
gem5::ArmISA::FpCondCompRegOp::condCode
ConditionCode condCode
Definition: vfp.hh:888
gem5::ArmISA::FpRegRegRegImmOp::op1
IntRegIndex op1
Definition: vfp.hh:1040
gem5::ArmISA::VfpNotAMicroop
@ VfpNotAMicroop
Definition: vfp.hh:56
gem5::ArmISA::FpOp::ternaryOp
fpType ternaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType op3, fpType(*func)(fpType, fpType, fpType), bool flush, bool defaultNan, uint32_t rMode) const
Definition: vfp.cc:961
gem5::ArmISA::unsignedRecipEstimate
uint32_t unsignedRecipEstimate(uint32_t op)
Definition: vfp.cc:889
gem5::ArmISA::fpRecpsS
static float fpRecpsS(float a, float b)
Definition: vfp.hh:745
gem5::ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:214
gem5::ArmISA::FpRegRegOp::op1
IntRegIndex op1
Definition: vfp.hh:923
gem5::ArmISA::FpRegImmOp::dest
IntRegIndex dest
Definition: vfp.hh:940
gem5::ArmISA::fixDest
fpType fixDest(bool flush, bool defaultNan, fpType val, fpType op1)
Definition: vfp.cc:231
gem5::ArmISA::isSnan
static bool isSnan(fpType val)
Definition: vfp.hh:207
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::lowFromDouble
static uint32_t lowFromDouble(double val)
Definition: vfp.hh:248
gem5::ArmISA::FpOp::fpSqrt
float fpSqrt(FPSCR fpscr, float x) const
Definition: vfp.hh:868
gem5::ArmISA::stride
Bitfield< 21, 20 > stride
Definition: misc_types.hh:446
gem5::ArmISA::FpRegRegImmOp::dest
IntRegIndex dest
Definition: vfp.hh:958
gem5::ArmISA::FpRegRegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: vfp.cc:149
gem5::X86ISA::op
Bitfield< 4 > op
Definition: types.hh:83
gem5::ArmISA::FpRegRegOp::FpRegRegOp
FpRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode=VfpNotAMicroop)
Definition: vfp.hh:925
gem5::ArmISA::vcvtFpDFpH
uint16_t vcvtFpDFpH(FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, double op)
Definition: vfp.cc:585
gem5::ArmISA::FpRegImmOp
Definition: vfp.hh:937
gem5::ArmISA::rMode
Bitfield< 23, 22 > rMode
Definition: misc_types.hh:447
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::ArmISA::FpCondCompRegOp
Definition: vfp.hh:884
gem5::ArmISA::fpDivD
static double fpDivD(double a, double b)
Definition: vfp.hh:523
gem5::ArmISA::fixFpSFpDDest
double fixFpSFpDDest(FPSCR fpscr, float val)
Definition: vfp.cc:373
error
std::string error
Definition: remote_gdb.cc:208

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