gem5  v21.1.0.2
misc.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __ARCH_ARM_INSTS_MISC_HH__
39 #define __ARCH_ARM_INSTS_MISC_HH__
40 
42 
43 namespace gem5
44 {
45 
46 class MrsOp : public ArmISA::PredOp
47 {
48  protected:
49  ArmISA::IntRegIndex dest;
50 
51  MrsOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
52  ArmISA::IntRegIndex _dest) :
53  ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest)
54  {}
55 
56  std::string generateDisassembly(
57  Addr pc, const loader::SymbolTable *symtab) const override;
58 };
59 
60 class MsrBase : public ArmISA::PredOp
61 {
62  protected:
63  uint8_t byteMask;
64 
65  MsrBase(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
66  uint8_t _byteMask) :
67  ArmISA::PredOp(mnem, _machInst, __opClass), byteMask(_byteMask)
68  {}
69 
70  void printMsrBase(std::ostream &os) const;
71 };
72 
73 class MsrImmOp : public MsrBase
74 {
75  protected:
76  uint32_t imm;
77 
78  MsrImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
79  OpClass __opClass, uint32_t _imm, uint8_t _byteMask) :
80  MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
81  {}
82 
83  std::string generateDisassembly(
84  Addr pc, const loader::SymbolTable *symtab) const override;
85 };
86 
87 class MsrRegOp : public MsrBase
88 {
89  protected:
90  ArmISA::IntRegIndex op1;
91 
92  MsrRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
93  OpClass __opClass, ArmISA::IntRegIndex _op1, uint8_t _byteMask) :
94  MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
95  {}
96 
97  std::string generateDisassembly(
98  Addr pc, const loader::SymbolTable *symtab) const override;
99 };
100 
101 class MrrcOp : public ArmISA::PredOp
102 {
103  protected:
105  ArmISA::IntRegIndex dest;
106  ArmISA::IntRegIndex dest2;
107  uint32_t imm;
108 
109  MrrcOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
110  ArmISA::MiscRegIndex _op1, ArmISA::IntRegIndex _dest,
111  ArmISA::IntRegIndex _dest2, uint32_t _imm) :
112  ArmISA::PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
113  dest2(_dest2), imm(_imm)
114  {}
115 
116  std::string generateDisassembly(
117  Addr pc, const loader::SymbolTable *symtab) const override;
118 };
119 
120 class McrrOp : public ArmISA::PredOp
121 {
122  protected:
123  ArmISA::IntRegIndex op1;
124  ArmISA::IntRegIndex op2;
126  uint32_t imm;
127 
128  McrrOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
129  ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
130  ArmISA::MiscRegIndex _dest, uint32_t _imm) :
131  ArmISA::PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
132  dest(_dest), imm(_imm)
133  {}
134 
135  std::string generateDisassembly(
136  Addr pc, const loader::SymbolTable *symtab) const override;
137 };
138 
139 class ImmOp : public ArmISA::PredOp
140 {
141  protected:
142  uint64_t imm;
143 
144  ImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
145  uint64_t _imm) :
146  ArmISA::PredOp(mnem, _machInst, __opClass), imm(_imm)
147  {}
148 
149  std::string generateDisassembly(
150  Addr pc, const loader::SymbolTable *symtab) const override;
151 };
152 
153 class RegImmOp : public ArmISA::PredOp
154 {
155  protected:
156  ArmISA::IntRegIndex dest;
157  uint64_t imm;
158 
159  RegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
160  OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm) :
161  ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
162  {}
163 
164  std::string generateDisassembly(
165  Addr pc, const loader::SymbolTable *symtab) const override;
166 };
167 
168 class RegRegOp : public ArmISA::PredOp
169 {
170  protected:
171  ArmISA::IntRegIndex dest;
172  ArmISA::IntRegIndex op1;
173 
174  RegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
175  OpClass __opClass, ArmISA::IntRegIndex _dest,
176  ArmISA::IntRegIndex _op1) :
177  ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
178  {}
179 
180  std::string generateDisassembly(
181  Addr pc, const loader::SymbolTable *symtab) const override;
182 };
183 
184 class RegOp : public ArmISA::PredOp
185 {
186  protected:
187  ArmISA::IntRegIndex dest;
188 
189  RegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
190  ArmISA::IntRegIndex _dest) :
191  ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest)
192  {}
193 
194  std::string generateDisassembly(
195  Addr pc, const loader::SymbolTable *symtab) const override;
196 };
197 
199 {
200  protected:
201  ArmISA::IntRegIndex dest;
202  uint64_t imm;
203  ArmISA::IntRegIndex op1;
204 
205  RegImmRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
206  OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm,
207  ArmISA::IntRegIndex _op1) :
208  ArmISA::PredOp(mnem, _machInst, __opClass),
209  dest(_dest), imm(_imm), op1(_op1)
210  {}
211 
212  std::string generateDisassembly(
213  Addr pc, const loader::SymbolTable *symtab) const override;
214 };
215 
217 {
218  protected:
219  ArmISA::IntRegIndex dest;
220  ArmISA::IntRegIndex op1;
221  ArmISA::IntRegIndex op2;
222  uint64_t imm;
223 
224  RegRegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
225  OpClass __opClass, ArmISA::IntRegIndex _dest,
226  ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
227  uint64_t _imm) :
228  ArmISA::PredOp(mnem, _machInst, __opClass),
229  dest(_dest), op1(_op1), op2(_op2), imm(_imm)
230  {}
231 
232  std::string generateDisassembly(
233  Addr pc, const loader::SymbolTable *symtab) const override;
234 };
235 
237 {
238  protected:
239  ArmISA::IntRegIndex dest;
240  ArmISA::IntRegIndex op1;
241  ArmISA::IntRegIndex op2;
242  ArmISA::IntRegIndex op3;
243 
244  RegRegRegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
245  OpClass __opClass, ArmISA::IntRegIndex _dest,
246  ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
247  ArmISA::IntRegIndex _op3) :
248  ArmISA::PredOp(mnem, _machInst, __opClass),
249  dest(_dest), op1(_op1), op2(_op2), op3(_op3)
250  {}
251 
252  std::string generateDisassembly(
253  Addr pc, const loader::SymbolTable *symtab) const override;
254 };
255 
257 {
258  protected:
259  ArmISA::IntRegIndex dest;
260  ArmISA::IntRegIndex op1;
261  ArmISA::IntRegIndex op2;
262 
263  RegRegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
264  OpClass __opClass, ArmISA::IntRegIndex _dest,
265  ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2) :
266  ArmISA::PredOp(mnem, _machInst, __opClass),
267  dest(_dest), op1(_op1), op2(_op2)
268  {}
269 
270  std::string generateDisassembly(
271  Addr pc, const loader::SymbolTable *symtab) const override;
272 };
273 
275 {
276  protected:
277  ArmISA::IntRegIndex dest;
278  ArmISA::IntRegIndex op1;
279  uint64_t imm;
280 
281  RegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
282  OpClass __opClass, ArmISA::IntRegIndex _dest,
283  ArmISA::IntRegIndex _op1, uint64_t _imm) :
284  ArmISA::PredOp(mnem, _machInst, __opClass),
285  dest(_dest), op1(_op1), imm(_imm)
286  {}
287 
288  std::string generateDisassembly(
289  Addr pc, const loader::SymbolTable *symtab) const override;
290 };
291 
293 {
294  protected:
296  ArmISA::IntRegIndex op1;
297  uint64_t imm;
298 
299  MiscRegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
300  OpClass __opClass, ArmISA::MiscRegIndex _dest,
301  ArmISA::IntRegIndex _op1, uint64_t _imm) :
302  ArmISA::PredOp(mnem, _machInst, __opClass),
303  dest(_dest), op1(_op1), imm(_imm)
304  {}
305 
306  std::string generateDisassembly(
307  Addr pc, const loader::SymbolTable *symtab) const override;
308 };
309 
311 {
312  protected:
313  ArmISA::IntRegIndex dest;
315  uint64_t imm;
316 
317  RegMiscRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
318  OpClass __opClass, ArmISA::IntRegIndex _dest,
319  ArmISA::MiscRegIndex _op1, uint64_t _imm) :
320  ArmISA::PredOp(mnem, _machInst, __opClass),
321  dest(_dest), op1(_op1), imm(_imm)
322  {}
323 
324  std::string generateDisassembly(
325  Addr pc, const loader::SymbolTable *symtab) const override;
326 };
327 
329 {
330  protected:
331  ArmISA::IntRegIndex dest;
332  uint64_t imm1;
333  uint64_t imm2;
334 
335  RegImmImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
336  OpClass __opClass, ArmISA::IntRegIndex _dest,
337  uint64_t _imm1, uint64_t _imm2) :
338  ArmISA::PredOp(mnem, _machInst, __opClass),
339  dest(_dest), imm1(_imm1), imm2(_imm2)
340  {}
341 
342  std::string generateDisassembly(
343  Addr pc, const loader::SymbolTable *symtab) const override;
344 };
345 
347 {
348  protected:
349  ArmISA::IntRegIndex dest;
350  ArmISA::IntRegIndex op1;
351  uint64_t imm1;
352  uint64_t imm2;
353 
354  RegRegImmImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
355  OpClass __opClass, ArmISA::IntRegIndex _dest,
356  ArmISA::IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2) :
357  ArmISA::PredOp(mnem, _machInst, __opClass),
358  dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
359  {}
360 
361  std::string generateDisassembly(
362  Addr pc, const loader::SymbolTable *symtab) const override;
363 };
364 
366 {
367  protected:
368  ArmISA::IntRegIndex dest;
369  uint64_t imm;
370  ArmISA::IntRegIndex op1;
371  int32_t shiftAmt;
372  ArmISA::ArmShiftType shiftType;
373 
374  RegImmRegShiftOp(const char *mnem, ArmISA::ExtMachInst _machInst,
375  OpClass __opClass, ArmISA::IntRegIndex _dest,
376  uint64_t _imm, ArmISA::IntRegIndex _op1,
377  int32_t _shiftAmt, ArmISA::ArmShiftType _shiftType) :
378  ArmISA::PredOp(mnem, _machInst, __opClass),
379  dest(_dest), imm(_imm), op1(_op1),
380  shiftAmt(_shiftAmt), shiftType(_shiftType)
381  {}
382 
383  std::string generateDisassembly(
384  Addr pc, const loader::SymbolTable *symtab) const override;
385 };
386 
387 class UnknownOp : public ArmISA::PredOp
388 {
389  protected:
390 
391  UnknownOp(const char *mnem, ArmISA::ExtMachInst _machInst,
392  OpClass __opClass) :
393  ArmISA::PredOp(mnem, _machInst, __opClass)
394  {}
395 
396  std::string generateDisassembly(
397  Addr pc, const loader::SymbolTable *symtab) const override;
398 };
399 
407 {
408  protected:
409  uint64_t iss;
411 
412  public:
413  McrMrcMiscInst(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
414  uint64_t _iss, ArmISA::MiscRegIndex _miscReg);
415 
417  Trace::InstRecord *traceData) const override;
418 
419  std::string generateDisassembly(
420  Addr pc, const loader::SymbolTable *symtab) const override;
421 
422 };
423 
429 {
430  public:
431  McrMrcImplDefined(const char *_mnemonic, ArmISA::ExtMachInst _machInst,
432  uint64_t _iss, ArmISA::MiscRegIndex _miscReg);
433 
435  Trace::InstRecord *traceData) const override;
436 
437  std::string generateDisassembly(
438  Addr pc, const loader::SymbolTable *symtab) const override;
439 
440 };
441 
442 } // namespace gem5
443 
444 #endif
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::RegImmRegOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:201
gem5::RegImmRegShiftOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:334
gem5::RegImmRegShiftOp
Definition: misc.hh:365
gem5::RegRegImmOp
Definition: misc.hh:274
gem5::RegRegRegImmOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:220
gem5::UnknownOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:347
gem5::MsrBase::byteMask
uint8_t byteMask
Definition: misc.hh:63
gem5::RegRegOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:172
gem5::RegImmRegOp::RegImmRegOp
RegImmRegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm, ArmISA::IntRegIndex _op1)
Definition: misc.hh:205
gem5::McrMrcMiscInst::iss
uint64_t iss
Definition: misc.hh:409
gem5::RegImmRegOp
Definition: misc.hh:198
gem5::RegMiscRegImmOp::imm
uint64_t imm
Definition: misc.hh:315
gem5::RegMiscRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:286
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::RegImmRegShiftOp::RegImmRegShiftOp
RegImmRegShiftOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm, ArmISA::IntRegIndex _op1, int32_t _shiftAmt, ArmISA::ArmShiftType _shiftType)
Definition: misc.hh:374
gem5::RegRegImmImmOp::RegRegImmImmOp
RegRegImmImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2)
Definition: misc.hh:354
gem5::MsrImmOp
Definition: misc.hh:73
gem5::RegOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:187
gem5::RegRegOp::RegRegOp
RegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1)
Definition: misc.hh:174
gem5::MsrRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:141
gem5::RegRegImmImmOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:350
gem5::RegMiscRegImmOp
Definition: misc.hh:310
gem5::MsrBase::printMsrBase
void printMsrBase(std::ostream &os) const
Definition: misc.cc:79
gem5::UnknownOp
Definition: misc.hh:387
gem5::RegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:247
gem5::MsrImmOp::imm
uint32_t imm
Definition: misc.hh:76
gem5::RegImmOp::imm
uint64_t imm
Definition: misc.hh:157
gem5::ImmOp::imm
uint64_t imm
Definition: misc.hh:142
gem5::RegRegRegRegOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:240
gem5::RegImmRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:322
gem5::MrrcOp::dest2
ArmISA::IntRegIndex dest2
Definition: misc.hh:106
gem5::RegOp
Definition: misc.hh:184
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::RegMiscRegImmOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:313
gem5::MsrRegOp::MsrRegOp
MsrRegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _op1, uint8_t _byteMask)
Definition: misc.hh:92
gem5::RegMiscRegImmOp::RegMiscRegImmOp
RegMiscRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::MiscRegIndex _op1, uint64_t _imm)
Definition: misc.hh:317
gem5::RegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:207
gem5::MsrRegOp
Definition: misc.hh:87
gem5::RegRegImmOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:277
gem5::MiscRegRegImmOp
Definition: misc.hh:292
gem5::MrrcOp::op1
ArmISA::MiscRegIndex op1
Definition: misc.hh:104
gem5::RegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:261
gem5::McrrOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:164
gem5::RegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:196
gem5::RegMiscRegImmOp::op1
ArmISA::MiscRegIndex op1
Definition: misc.hh:314
gem5::RegImmImmOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:331
gem5::RegRegRegRegOp::op3
ArmISA::IntRegIndex op3
Definition: misc.hh:242
gem5::RegRegRegRegOp::op2
ArmISA::IntRegIndex op2
Definition: misc.hh:241
gem5::RegImmOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:156
gem5::RegImmRegOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:203
gem5::RegImmImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:298
gem5::UnknownOp::UnknownOp
UnknownOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass)
Definition: misc.hh:391
gem5::ImmOp
Definition: misc.hh:139
gem5::RegImmImmOp::imm2
uint64_t imm2
Definition: misc.hh:333
gem5::RegRegImmImmOp::imm2
uint64_t imm2
Definition: misc.hh:352
gem5::MrsOp
Definition: misc.hh:46
gem5::McrrOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:123
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::RegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:186
gem5::ImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:177
gem5::McrMrcImplDefined::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: misc.cc:389
gem5::McrMrcMiscInst::McrMrcMiscInst
McrMrcMiscInst(const char *_mnemonic, ArmISA::ExtMachInst _machInst, uint64_t _iss, ArmISA::MiscRegIndex _miscReg)
Definition: misc.cc:353
gem5::ImmOp::ImmOp
ImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, uint64_t _imm)
Definition: misc.hh:144
gem5::McrMrcMiscInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:376
gem5::RegRegImmImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:309
gem5::MiscRegRegImmOp::MiscRegRegImmOp
MiscRegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _dest, ArmISA::IntRegIndex _op1, uint64_t _imm)
Definition: misc.hh:299
gem5::MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:43
gem5::RegImmRegShiftOp::shiftType
ArmISA::ArmShiftType shiftType
Definition: misc.hh:372
gem5::RegImmImmOp::imm1
uint64_t imm1
Definition: misc.hh:332
gem5::RegRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:216
gem5::MsrImmOp::MsrImmOp
MsrImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, uint32_t _imm, uint8_t _byteMask)
Definition: misc.hh:78
gem5::RegRegRegOp
Definition: misc.hh:256
gem5::RegRegImmOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:278
gem5::McrrOp::imm
uint32_t imm
Definition: misc.hh:126
gem5::RegImmImmOp::RegImmImmOp
RegImmImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2)
Definition: misc.hh:335
gem5::RegImmRegShiftOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:370
gem5::RegRegImmImmOp
Definition: misc.hh:346
gem5::McrrOp::McrrOp
McrrOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2, ArmISA::MiscRegIndex _dest, uint32_t _imm)
Definition: misc.hh:128
gem5::MiscRegRegImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:274
gem5::RegRegImmImmOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:349
gem5::RegRegRegOp::RegRegRegOp
RegRegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2)
Definition: misc.hh:263
gem5::McrMrcImplDefined
This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc behaviour is trappable ev...
Definition: misc.hh:428
gem5::MiscRegRegImmOp::dest
ArmISA::MiscRegIndex dest
Definition: misc.hh:295
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RegImmRegOp::imm
uint64_t imm
Definition: misc.hh:202
pred_inst.hh
gem5::MrrcOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:105
gem5::McrrOp
Definition: misc.hh:120
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::McrrOp::dest
ArmISA::MiscRegIndex dest
Definition: misc.hh:125
gem5::MrrcOp
Definition: misc.hh:101
gem5::McrMrcImplDefined::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:403
gem5::RegRegRegImmOp::RegRegRegImmOp
RegRegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2, uint64_t _imm)
Definition: misc.hh:224
gem5::RegRegOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:171
gem5::RegRegRegRegOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:239
gem5::RegRegRegImmOp::op2
ArmISA::IntRegIndex op2
Definition: misc.hh:221
gem5::RegRegRegOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:260
gem5::MiscRegRegImmOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:296
gem5::MsrImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:132
gem5::RegImmImmOp
Definition: misc.hh:328
gem5::MsrRegOp::op1
ArmISA::IntRegIndex op1
Definition: misc.hh:90
gem5::RegImmOp
Definition: misc.hh:153
gem5::McrMrcMiscInst::execute
Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const override
Definition: misc.cc:363
gem5::MrsOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:49
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::RegRegRegRegOp::RegRegRegRegOp
RegRegRegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2, ArmISA::IntRegIndex _op3)
Definition: misc.hh:244
gem5::RegImmOp::RegImmOp
RegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm)
Definition: misc.hh:159
gem5::McrMrcImplDefined::McrMrcImplDefined
McrMrcImplDefined(const char *_mnemonic, ArmISA::ExtMachInst _machInst, uint64_t _iss, ArmISA::MiscRegIndex _miscReg)
Definition: misc.cc:382
gem5::RegRegOp
Definition: misc.hh:168
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::RegRegRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:231
gem5::RegRegImmOp::RegRegImmOp
RegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _op1, uint64_t _imm)
Definition: misc.hh:281
gem5::RegImmRegShiftOp::imm
uint64_t imm
Definition: misc.hh:369
gem5::RegRegRegImmOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:219
gem5::ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:214
gem5::RegRegImmImmOp::imm1
uint64_t imm1
Definition: misc.hh:351
gem5::MrrcOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:151
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::RegRegRegOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:259
gem5::RegRegImmOp::imm
uint64_t imm
Definition: misc.hh:279
gem5::RegImmRegShiftOp::shiftAmt
int32_t shiftAmt
Definition: misc.hh:371
gem5::MrsOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: misc.cc:49
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RegRegRegImmOp
Definition: misc.hh:216
gem5::RegRegRegImmOp::imm
uint64_t imm
Definition: misc.hh:222
gem5::McrMrcMiscInst::miscReg
ArmISA::MiscRegIndex miscReg
Definition: misc.hh:410
gem5::RegImmRegShiftOp::dest
ArmISA::IntRegIndex dest
Definition: misc.hh:368
gem5::MsrBase::MsrBase
MsrBase(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, uint8_t _byteMask)
Definition: misc.hh:65
gem5::MrrcOp::imm
uint32_t imm
Definition: misc.hh:107
gem5::RegOp::RegOp
RegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest)
Definition: misc.hh:189
gem5::RegRegRegOp::op2
ArmISA::IntRegIndex op2
Definition: misc.hh:261
gem5::RegRegRegRegOp
Definition: misc.hh:236
gem5::MrsOp::MrsOp
MrsOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::IntRegIndex _dest)
Definition: misc.hh:51
gem5::MsrBase
Definition: misc.hh:60
gem5::McrMrcMiscInst
Certain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is ...
Definition: misc.hh:406
gem5::MiscRegRegImmOp::imm
uint64_t imm
Definition: misc.hh:297
gem5::McrrOp::op2
ArmISA::IntRegIndex op2
Definition: misc.hh:124
gem5::MrrcOp::MrrcOp
MrrcOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass, ArmISA::MiscRegIndex _op1, ArmISA::IntRegIndex _dest, ArmISA::IntRegIndex _dest2, uint32_t _imm)
Definition: misc.hh:109

Generated on Tue Sep 21 2021 12:24:35 for gem5 by doxygen 1.8.17