vgic.hh File Reference

Implementiation of a GIC-400 List Register-based VGIC interface. More...

#include <algorithm>
#include <array>
#include "base/addr_range.hh"
#include "base/bitunion.hh"
#include "dev/io_device.hh"
#include "dev/platform.hh"
#include "params/VGic.hh"

Go to the source code of this file.

Classes
class	gem5::VGic

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.

Detailed Description

Implementiation of a GIC-400 List Register-based VGIC interface.

The VGIC is, in this implementation, completely separate from the GIC itself. Only a VIRQ line to the CPU and a PPI line to the GIC (for a HV maintenance IRQ) is required.

The mode in which the List Registers may flag (via LR.HW) that a hardware EOI is to be performed is NOT supported. (This requires tighter integration with the GIC.)

Definition in file vgic.hh.