gem5  v21.1.0.2
Classes | Namespaces
vgic.hh File Reference
#include <algorithm>
#include <array>
#include "base/addr_range.hh"
#include "base/bitunion.hh"
#include "dev/io_device.hh"
#include "dev/platform.hh"
#include "params/VGic.hh"

Go to the source code of this file.


class  gem5::VGic


 Reference material can be found at the JEDEC website: UFS standard UFS HCI specification

Detailed Description

Implementiation of a GIC-400 List Register-based VGIC interface. The VGIC is, in this implementation, completely separate from the GIC itself. Only a VIRQ line to the CPU and a PPI line to the GIC (for a HV maintenance IRQ) is required.

The mode in which the List Registers may flag (via LR.HW) that a hardware EOI is to be performed is NOT supported. (This requires tighter integration with the GIC.)

Definition in file vgic.hh.

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