gem5  v21.1.0.2
vgic.hh
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37 
38 
50 #ifndef __DEV_ARM_VGIC_H__
51 #define __DEV_ARM_VGIC_H__
52 
53 #include <algorithm>
54 #include <array>
55 
56 #include "base/addr_range.hh"
57 #include "base/bitunion.hh"
58 #include "dev/io_device.hh"
59 #include "dev/platform.hh"
60 #include "params/VGic.hh"
61 
62 namespace gem5
63 {
64 
65 class VGic : public PioDevice
66 {
67  private:
68  static const int VGIC_CPU_MAX = 256;
69  static const int NUM_LR = 4;
70 
71  static const int GICH_SIZE = 0x200;
72  static const int GICH_REG_SIZE = 0x2000;
73 
74  static const int GICH_HCR = 0x000;
75  static const int GICH_VTR = 0x004;
76  static const int GICH_VMCR = 0x008;
77  static const int GICH_MISR = 0x010;
78  static const int GICH_EISR0 = 0x020;
79  static const int GICH_EISR1 = 0x024;
80  static const int GICH_ELSR0 = 0x030;
81  static const int GICH_ELSR1 = 0x034;
82  static const int GICH_APR0 = 0x0f0;
83  static const int GICH_LR0 = 0x100;
84  static const int GICH_LR1 = 0x104;
85  static const int GICH_LR2 = 0x108;
86  static const int GICH_LR3 = 0x10c;
87 
88  static const int GICV_SIZE = 0x2000;
89  static const int GICV_CTLR = 0x000;
90  static const int GICV_PMR = 0x004;
91  static const int GICV_BPR = 0x008;
92  static const int GICV_IAR = 0x00c;
93  static const int GICV_EOIR = 0x010;
94  static const int GICV_RPR = 0x014;
95  static const int GICV_HPPIR = 0x018;
96  static const int GICV_ABPR = 0x01c;
97  static const int GICV_AIAR = 0x020;
98  static const int GICV_AEOIR = 0x024;
99  static const int GICV_AHPPIR = 0x028;
100  static const int GICV_APR0 = 0x0d0;
101  static const int GICV_IIDR = 0x0fc;
102  static const int GICV_DIR = 0x1000;
103 
104  static const uint32_t LR_PENDING = 1;
105  static const uint32_t LR_ACTIVE = 2;
106  const uint32_t gicvIIDR;
107 
109  void processPostVIntEvent(uint32_t cpu);
110 
114 
117 
121  int maintInt;
122 
123  BitUnion32(ListReg)
124  Bitfield<31> HW;
125  Bitfield<30> Grp1;
126  Bitfield<29,28> State;
127  Bitfield<27,23> Priority;
128  Bitfield<19> EOI;
129  Bitfield<12,10> CpuID;
130  Bitfield<9,0> VirtualID;
131  EndBitUnion(ListReg)
132 
133  BitUnion32(HCR)
134  Bitfield<31,27> EOICount;
135  Bitfield<7> VGrp1DIE;
136  Bitfield<6> VGrp1EIE;
137  Bitfield<5> VGrp0DIE;
138  Bitfield<4> VGrp0EIE;
139  Bitfield<3> NPIE;
140  Bitfield<2> LRENPIE;
141  Bitfield<1> UIE;
142  Bitfield<0> En;
143  EndBitUnion(HCR)
144 
145  BitUnion32(VCTLR)
146  Bitfield<9> EOImode;
147  Bitfield<4> CPBR;
148  Bitfield<3> FIQEn;
149  Bitfield<2> AckCtl;
150  Bitfield<1> EnGrp1;
151  Bitfield<0> En; // This gets written to enable, not group 1.
152  EndBitUnion(VCTLR)
153 
154  /* State per CPU. EVERYTHING should be in this struct and simply replicated
155  * N times.
156  */
157  struct vcpuIntData : public Serializable
158  {
159  vcpuIntData()
160  : vctrl(0), hcr(0), eisr(0), VMGrp0En(0), VMGrp1En(0),
161  VMAckCtl(0), VMFiqEn(0), VMCBPR(0), VEM(0), VMABP(0), VMBP(0),
162  VMPriMask(0)
163  {
164  std::fill(LR.begin(), LR.end(), 0);
165  }
166  virtual ~vcpuIntData() {}
167 
168  std::array<ListReg, NUM_LR> LR;
169  VCTLR vctrl;
170 
171  HCR hcr;
172  uint64_t eisr;
173 
174  /* Host info, guest info (should be 100% accessible via GICH_* regs!) */
175  uint8_t VMGrp0En;
176  uint8_t VMGrp1En;
177  uint8_t VMAckCtl;
178  uint8_t VMFiqEn;
179  uint8_t VMCBPR;
180  uint8_t VEM;
181  uint8_t VMABP;
182  uint8_t VMBP;
183  uint8_t VMPriMask;
184 
185  void serialize(CheckpointOut &cp) const override;
186  void unserialize(CheckpointIn &cp) override;
187  };
188 
189  struct std::array<vcpuIntData, VGIC_CPU_MAX> vcpuData;
190 
191  public:
192  using Params = VGicParams;
193  VGic(const Params &p);
194  ~VGic();
195 
196  AddrRangeList getAddrRanges() const override;
197 
198  Tick read(PacketPtr pkt) override;
199  Tick write(PacketPtr pkt) override;
200 
201  void serialize(CheckpointOut &cp) const override;
202  void unserialize(CheckpointIn &cp) override;
203 
204  private:
205  Tick readVCpu(PacketPtr pkt);
206  Tick readCtrl(PacketPtr pkt);
207 
208  Tick writeVCpu(PacketPtr pkt);
209  Tick writeCtrl(PacketPtr pkt);
210 
211  void updateIntState(ContextID ctx_id);
212  uint32_t getMISR(struct vcpuIntData *vid);
213  void postVInt(uint32_t cpu, Tick when);
214  void unPostVInt(uint32_t cpu);
215  void postMaintInt(uint32_t cpu);
216  void unPostMaintInt(uint32_t cpu);
217 
218  unsigned int lrPending(struct vcpuIntData *vid)
219  {
220  unsigned int pend = 0;
221  for (int i = 0; i < NUM_LR; i++) {
222  if (vid->LR[i].State & LR_PENDING)
223  pend++;
224  }
225  return pend;
226  }
227  unsigned int lrValid(struct vcpuIntData *vid)
228  {
229  unsigned int valid = 0;
230  for (int i = 0; i < NUM_LR; i++) {
231  if (vid->LR[i].State)
232  valid++;
233  }
234  return valid;
235  }
236 
238  int findHighestPendingLR(struct vcpuIntData *vid)
239  {
240  unsigned int prio = 0xff;
241  int p = -1;
242  for (int i = 0; i < NUM_LR; i++) {
243  if ((vid->LR[i].State & LR_PENDING) && (vid->LR[i].Priority < prio)) {
244  p = i;
245  prio = vid->LR[i].Priority;
246  }
247  }
248  return p;
249  }
250 
251  int findLRForVIRQ(struct vcpuIntData *vid, int virq, int vcpu)
252  {
253  for (int i = 0; i < NUM_LR; i++) {
254  if (vid->LR[i].State &&
255  vid->LR[i].VirtualID == virq &&
256  vid->LR[i].CpuID == vcpu)
257  return i;
258  }
259  return -1;
260  }
261 };
262 
263 } // namespace gem5
264 
265 #endif
gem5::VGic::unPostVInt
void unPostVInt(uint32_t cpu)
Definition: vgic.cc:375
gem5::scmi::Platform
Definition: scmi_platform.hh:264
gem5::VGic::readVCpu
Tick readVCpu(PacketPtr pkt)
Definition: vgic.cc:100
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
io_device.hh
gem5::VGic::Priority
Bitfield< 27, 23 > Priority
Definition: vgic.hh:127
gem5::VGic::postVInt
void postVInt(uint32_t cpu, Tick when)
Definition: vgic.cc:367
gem5::VGic::GICH_LR3
static const int GICH_LR3
Definition: vgic.hh:86
gem5::VGic::platform
Platform * platform
Definition: vgic.hh:115
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
gem5::VGic::GICH_LR2
static const int GICH_LR2
Definition: vgic.hh:85
gem5::VGic::En
Bitfield< 0 > En
Definition: vgic.hh:142
gem5::VGic::GICH_HCR
static const int GICH_HCR
Definition: vgic.hh:74
gem5::VGic::maintIntPosted
bool maintIntPosted[VGIC_CPU_MAX]
Definition: vgic.hh:112
gem5::VGic::EOI
Bitfield< 19 > EOI
Definition: vgic.hh:128
gem5::VGic::GICV_HPPIR
static const int GICV_HPPIR
Definition: vgic.hh:95
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::VGic::processPostVIntEvent
void processPostVIntEvent(uint32_t cpu)
Post interrupt to CPU.
Definition: vgic.cc:383
gem5::VGic::GICV_APR0
static const int GICV_APR0
Definition: vgic.hh:100
gem5::VGic::GICH_SIZE
static const int GICH_SIZE
Definition: vgic.hh:71
gem5::VGic::VGrp0EIE
Bitfield< 4 > VGrp0EIE
Definition: vgic.hh:138
gem5::VGic::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: vgic.cc:463
gem5::VGic::EndBitUnion
EndBitUnion(ListReg) BitUnion32(HCR) Bitfield< 31
gem5::VGic::NPIE
Bitfield< 3 > NPIE
Definition: vgic.hh:139
gem5::VGic::updateIntState
void updateIntState(ContextID ctx_id)
Definition: vgic.cc:409
gem5::VGic::LRENPIE
Bitfield< 2 > LRENPIE
Definition: vgic.hh:140
gem5::VGic::LR_ACTIVE
static const uint32_t LR_ACTIVE
Definition: vgic.hh:105
gem5::VGic::getMISR
uint32_t getMISR(struct vcpuIntData *vid)
Definition: vgic.cc:354
gem5::VGic::FIQEn
Bitfield< 3 > FIQEn
Definition: vgic.hh:148
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::VGic::GICH_VTR
static const int GICH_VTR
Definition: vgic.hh:75
gem5::VGic::AckCtl
Bitfield< 2 > AckCtl
Definition: vgic.hh:149
gem5::VGic::GICV_AEOIR
static const int GICV_AEOIR
Definition: vgic.hh:98
gem5::VGic::VGic
VGic(const Params &p)
Definition: vgic.cc:52
gem5::VGic::lrValid
unsigned int lrValid(struct vcpuIntData *vid)
Definition: vgic.hh:227
gem5::VGic::GICV_AIAR
static const int GICV_AIAR
Definition: vgic.hh:97
gem5::VGic::VirtualID
Bitfield< 9, 0 > VirtualID
Definition: vgic.hh:130
gem5::VGic::GICH_LR1
static const int GICH_LR1
Definition: vgic.hh:84
gem5::VGic::VGIC_CPU_MAX
static const int VGIC_CPU_MAX
Definition: vgic.hh:68
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::VGic::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: vgic.cc:521
gem5::BaseGic
Definition: base_gic.hh:72
gem5::VGic::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: vgic.cc:454
gem5::VGic::GICV_AHPPIR
static const int GICV_AHPPIR
Definition: vgic.hh:99
gem5::VGic::GICV_EOIR
static const int GICV_EOIR
Definition: vgic.hh:93
gem5::VGic::LR_PENDING
static const uint32_t LR_PENDING
Definition: vgic.hh:104
gem5::VGic::State
Bitfield< 29, 28 > State
Definition: vgic.hh:126
gem5::VGic::NUM_LR
static const int NUM_LR
Definition: vgic.hh:69
gem5::VGic::GICH_LR0
static const int GICH_LR0
Definition: vgic.hh:83
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::VGic::VGrp1EIE
Bitfield< 6 > VGrp1EIE
Definition: vgic.hh:136
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::VGic::Grp1
Bitfield< 30 > Grp1
Definition: vgic.hh:125
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
bitunion.hh
gem5::VGic::GICH_EISR1
static const int GICH_EISR1
Definition: vgic.hh:79
gem5::VGic::GICH_EISR0
static const int GICH_EISR0
Definition: vgic.hh:78
gem5::VGic::GICH_ELSR0
static const int GICH_ELSR0
Definition: vgic.hh:80
gem5::VGic::GICV_PMR
static const int GICV_PMR
Definition: vgic.hh:90
gem5::VGic::EOICount
EOICount
Definition: vgic.hh:134
gem5::VGic::gic
BaseGic * gic
Definition: vgic.hh:116
gem5::VGic::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: vgic.cc:87
gem5::VGic::findLRForVIRQ
int findLRForVIRQ(struct vcpuIntData *vid, int virq, int vcpu)
Definition: vgic.hh:251
gem5::VGic::GICH_VMCR
static const int GICH_VMCR
Definition: vgic.hh:76
gem5::VGic::vcpuAddr
Addr vcpuAddr
Definition: vgic.hh:118
platform.hh
gem5::VGic::gicvIIDR
const uint32_t gicvIIDR
Definition: vgic.hh:106
gem5::VGic::GICV_IAR
static const int GICV_IAR
Definition: vgic.hh:92
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::VGic::writeVCpu
Tick writeVCpu(PacketPtr pkt)
Definition: vgic.cc:241
gem5::VGic::pioDelay
Tick pioDelay
Definition: vgic.hh:120
gem5::VGic::GICH_MISR
static const int GICH_MISR
Definition: vgic.hh:77
gem5::VGic::GICH_ELSR1
static const int GICH_ELSR1
Definition: vgic.hh:81
gem5::VGic::hvAddr
Addr hvAddr
Definition: vgic.hh:119
gem5::VGic::GICV_RPR
static const int GICV_RPR
Definition: vgic.hh:94
gem5::VGic::unPostMaintInt
void unPostMaintInt(uint32_t cpu)
Definition: vgic.cc:399
gem5::VGic::GICV_SIZE
static const int GICV_SIZE
Definition: vgic.hh:88
addr_range.hh
gem5::VGic::EnGrp1
Bitfield< 1 > EnGrp1
Definition: vgic.hh:150
gem5::VGic::readCtrl
Tick readCtrl(PacketPtr pkt)
Definition: vgic.cc:147
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::VGic::maintInt
int maintInt
Definition: vgic.hh:121
gem5::VGic::lrPending
unsigned int lrPending(struct vcpuIntData *vid)
Definition: vgic.hh:218
gem5::VGic::~VGic
~VGic()
Definition: vgic.cc:67
gem5::VGic::GICH_REG_SIZE
static const int GICH_REG_SIZE
Definition: vgic.hh:72
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::VGic::findHighestPendingLR
int findHighestPendingLR(struct vcpuIntData *vid)
Returns LR index or -1 if none pending.
Definition: vgic.hh:238
gem5::VGic::VGrp1DIE
Bitfield< 7 > VGrp1DIE
Definition: vgic.hh:135
gem5::VGic::writeCtrl
Tick writeCtrl(PacketPtr pkt)
Definition: vgic.cc:290
gem5::VGic::vIntPosted
bool vIntPosted[VGIC_CPU_MAX]
Definition: vgic.hh:113
gem5::VGic::GICV_IIDR
static const int GICV_IIDR
Definition: vgic.hh:101
gem5::VGic::GICV_ABPR
static const int GICV_ABPR
Definition: vgic.hh:96
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::VGic::UIE
Bitfield< 1 > UIE
Definition: vgic.hh:141
gem5::VGic::GICV_CTLR
static const int GICV_CTLR
Definition: vgic.hh:89
std::list< AddrRange >
gem5::VGic::vcpuData
EndBitUnion(VCTLR) struct vcpuIntData struct std::array< vcpuIntData, VGIC_CPU_MAX > vcpuData
Definition: vgic.hh:189
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::VGic
Definition: vgic.hh:65
gem5::VGic::GICH_APR0
static const int GICH_APR0
Definition: vgic.hh:82
gem5::VGic::Params
VGicParams Params
Definition: vgic.hh:192
gem5::VGic::postMaintInt
void postMaintInt(uint32_t cpu)
Definition: vgic.cc:391
gem5::VGic::GICV_DIR
static const int GICV_DIR
Definition: vgic.hh:102
gem5::VGic::BitUnion32
BitUnion32(ListReg) Bitfield< 31 > HW
gem5::VGic::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: vgic.cc:74
gem5::VGic::CPBR
Bitfield< 4 > CPBR
Definition: vgic.hh:147
gem5::VGic::postVIntEvent
EventFunctionWrapper * postVIntEvent[VGIC_CPU_MAX]
Definition: vgic.hh:111
gem5::VGic::CpuID
Bitfield< 12, 10 > CpuID
Definition: vgic.hh:129
gem5::VGic::GICV_BPR
static const int GICV_BPR
Definition: vgic.hh:91
gem5::VGic::VGrp0DIE
Bitfield< 5 > VGrp0DIE
Definition: vgic.hh:137

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