Here is a list of all class members with links to the classes they belong to:

- i -

• i : KvmFPReg
• i2cAddr : I2CBus , I2CDevice
• I2CBus() : I2CBus
• I2CDevice() : I2CDevice
• i2cStart() : I2CDevice
• I2CState : I2CBus
• I386 : ObjectFile
• I386LinuxProcess() : X86ISA::I386LinuxProcess
• I386Process() : X86ISA::I386Process
• I8042() : X86ISA::I8042
• I82094AA() : X86ISA::I82094AA
• I8237() : X86ISA::I8237
• I8254() : X86ISA::I8254
• I8259() : X86ISA::I8259
• I_ALU : Wavefront
• I_FLAT : Wavefront
• I_GLOBAL : Wavefront
• I_PRIVATE : Wavefront
• I_SHARED : Wavefront
• iam : iGbReg::Regs
• iauxBase : ecoff_fdr
• iauxMax : ecoff_symhdr
• ibrd : Pl011
• ic : Iob
• IcacheAccessComplete : DefaultFetch< Impl >
• icacheGen : TraceCPU
• IcacheNeedsRetry : Minor::Fetch1
• icacheNextEvent : TraceCPU
• icachePort : AtomicSimpleCPU , CheckerCPU , DefaultFetch< Impl >
• IcachePort() : DefaultFetch< Impl >::IcachePort
• icachePort : Minor::Fetch1
• IcachePort() : Minor::Fetch1::IcachePort
• icachePort : TimingSimpleCPU
• IcachePort() : TimingSimpleCPU::IcachePort
• icachePort : TraceCPU
• IcachePort() : TraceCPU::IcachePort
• IcacheRetry : BaseSimpleCPU
• icacheRetryRecvd() : TraceCPU
• IcacheRunning : Minor::Fetch1
• icacheStallCycles : DefaultFetch< Impl > , SimpleExecContext
• icacheState : Minor::Fetch1
• IcacheState : Minor::Fetch1
• IcacheWaitResponse : BaseSimpleCPU , DefaultFetch< Impl >
• IcacheWaitRetry : DefaultFetch< Impl >
• IcacheWaitSwitch : BaseSimpleCPU
• iccrpr : GicV2
• ICH_LR_EL2_STATE_ACTIVE : Gicv3CPUInterface
• ICH_LR_EL2_STATE_ACTIVE_PENDING : Gicv3CPUInterface
• ICH_LR_EL2_STATE_PENDING : Gicv3CPUInterface
• icid : Gicv3Its
• icountRscId : Iris::ThreadContext
• icr : iGbReg::Regs
• id : AbstractController::SenderState , ArmKvmCPU::KvmCoreMiscRegInfo , ArmKvmCPU::KvmIntRegInfo , BasicBlock , GarnetSyntheticTraffic , iGbReg::RxDesc , Iris::ThreadContext::BpInfo , MemDepUnit< MemDepPred, Impl > , MemTest , Minor::Fetch1::FetchRequest , Minor::ForwardLineData , Minor::MinorDynInst , Net::IpHdr , Network::AddrMapNode , Packet , Port , sc_gem5::ReportMsgInfo , SimpleCache::CPUSidePort , SimPoint::BBInfo , Stats::Info , ThermalNode , TimeBuffer< T >
• ID : tlm::tlm_extension< T >
• id : vring_used_elem , X86ISA::I82094AA , X86ISA::IntelMP::IOAPIC
• ID_9P : VirtIO9PBase
• ID_BLOCK : VirtIOBlock
• ID_CONSOLE : VirtIOConsole
• id_count : Stats::Info
• ID_INVALID : VirtIODummyDevice
• IDbits : Gicv3CPUInterface
• IDBITS : Gicv3Distributor
• idBits : Gicv3Its
• idcode : ArmISA::PMU
• ideConfig : IdeController
• IdeController() : IdeController
• IdeDisk() : IdeDisk
• ident : Net::ip6_opt_fragment
• identification : Brig::BrigModuleHeader
• Idle : BaseKvmCPU , BaseSimpleCPU
• IDLE : BaseXBar::Layer< SrcType, DstType >
• Idle : CopyEngine::CopyEngineChannel , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl >
• IDLE : I2CBus
• Idle : Iob , ROB< Impl >
• idle_dur : ExecStage
• idleCycles : FullO3CPU< Impl > , Ticked
• idleDur : ExecStage
• idleFraction : SimpleExecContext
• IdleGen() : IdleGen
• idlePhaseStart : UFSHostDevice
• idleProcess : AlphaISA::Kernel::Statistics
• idleRate : DefaultFetch< Impl >
• IdleStartEvent() : IdleStartEvent
• idleStartEvent : LinuxAlphaSystem
• idleTimes : UFSHostDevice::UFSHostDeviceStats
• idnMax : ecoff_symhdr
• idOutOfRange() : Gicv3Its , ItsCommand
• idr0 : SMMURegs
• idr1 : SMMURegs
• idr2 : SMMURegs
• idr3 : SMMURegs
• idr4 : SMMURegs
• idr5 : SMMURegs
• IdRange : PhysRegFile
• IdReg : RealViewCtrl
• idRegs : CustomNoMaliGpu
• idx : ArmKvmCPU::KvmCoreMiscRegInfo , ArmKvmCPU::KvmIntRegInfo , ArmV8KvmCPU::IntRegInfo , ArmV8KvmCPU::MiscRegInfo , BankedArray::AccessRecord , CircularQueue< T >::iterator , FUPool::FUIdxQueue , LSQUnit< Impl >::LQSenderState , LSQUnit< Impl >::SQSenderState , vring_avail , vring_used
• idx1 : IndirectMemoryPrefetcher::IndirectPatternDetectorEntry
• idx2 : IndirectMemoryPrefetcher::IndirectPatternDetectorEntry
• idxMask : DefaultBTB
• IdxNameMap : Iris::ThreadContext
• ie : RiscvISA::Interrupts , SparcISA::PageTableEntry
• ier : dp_regs
• IER : Uart8250
• IEW : DefaultCommit< Impl > , DefaultRename< Impl >
• iew : DefaultRename< Impl >::Stalls , FullO3CPU< Impl >
• IEW : InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl > , SimpleCPUPolicy< Impl >
• iew_ptr : DefaultRename< Impl >
• iewBlock : TimeBufStruct< Impl >
• iewBlockCycles : DefaultIEW< Impl >
• iewDispatchedInsts : DefaultIEW< Impl >
• iewDispLoadInsts : DefaultIEW< Impl >
• iewDispNonSpecInsts : DefaultIEW< Impl >
• iewDispSquashedInsts : DefaultIEW< Impl >
• iewDispStoreInsts : DefaultIEW< Impl >
• iewExecLoadInsts : DefaultIEW< Impl >
• iewExecRate : DefaultIEW< Impl >
• iewExecSquashedInsts : DefaultIEW< Impl >
• iewExecStoreInsts : DefaultIEW< Impl >
• iewExecutedBranches : DefaultIEW< Impl >
• iewExecutedInsts : DefaultIEW< Impl >
• iewExecutedNop : DefaultIEW< Impl >
• iewExecutedRefs : DefaultIEW< Impl >
• iewExecutedSwp : DefaultIEW< Impl >
• iewIdleCycles : DefaultIEW< Impl >
• IEWIdx : FullO3CPU< Impl >
• iewInfo : TimeBufStruct< Impl >
• iewInstsToCommit : DefaultIEW< Impl >
• iewIQFullEvents : DefaultIEW< Impl >
• iewLSQFullEvents : DefaultIEW< Impl >
• iewQueue : DefaultCommit< Impl > , DefaultIEW< Impl > , FullO3CPU< Impl >
• iewSquashCycles : DefaultIEW< Impl >
• iewStage : DefaultCommit< Impl > , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl >
• IEWStruct : DefaultCommit< Impl > , DefaultIEW< Impl > , FullO3CPU< Impl > , SimpleCPUPolicy< Impl >
• iewToCommitDelay : DefaultCommit< Impl >
• iewToDecodeDelay : DefaultDecode< Impl >
• iewToFetchDelay : DefaultFetch< Impl >
• iewToRenameDelay : DefaultRename< Impl >
• iewUnblock : TimeBufStruct< Impl >
• iewUnblockCycles : DefaultIEW< Impl >
• iextMax : ecoff_symhdr
• if_type : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > >
• iface : sc_gem5::TraceVal<::sc_core::sc_signal_in_if< T >, Base >
• iface_ : sc_gem5::ScInterfaceWrapper< IF >
• ifc : SMMUAction , SMMUATSMasterPort , SMMUATSSlavePort , SMMUSlavePort , SMMUTranslationProcess
• ifcSmmuLat : SMMUv3
• ifcSmmuSem : SMMUv3
• ifcTLBLookup() : SMMUTranslationProcess
• ifcTLBUpdate() : SMMUTranslationProcess
• ifd : ecoff_extsym , MemoryImage::Segment
• ifdMax : ecoff_symhdr
• ifetch_pkt : TimingSimpleCPU
• ifetch_req : AtomicSimpleCPU
• ifls : Pl011
• igbe : IGbE::DescCache< T >
• IGbE() : IGbE
• IGbEInt() : IGbEInt
• igehl : StatisticalCorrector
• Ignore : ArmISA::TableWalker::L1Descriptor
• ignore : Trace::Logger
• ignoredAddrRange : Trace::TarmacParser
• ihr : dp_regs
• ihs : Pl111
• iidr : SMMURegs
• iline : pdr
• ilineBase : ecoff_fdr
• ilineMax : ecoff_symhdr
• IllegalAsi : SparcISA::TLB
• IllegalExecInst() : IllegalExecInst
• IllegalFrmFault() : RiscvISA::IllegalFrmFault
• IllegalInstFault() : RiscvISA::IllegalInstFault
• IllegalInstSetStateFault() : ArmISA::IllegalInstSetStateFault
• im : StatisticalCorrector
• image : CowDiskCallback , ElfObject , IdeDisk , MmDisk , Process , SimpleDisk , VirtIOBlock
• imageData : ImageFile
• ImageFile() : ImageFile
• ImageFileData() : ImageFileData
• imageQuery : Brig::BrigInstQueryImage
• imageSegmentMemoryScope : Brig::BrigInstMemFence
• imageType : Brig::BrigInstImage , Brig::BrigInstQueryImage
• imask : ArchTimer
• imb : PAL
• imcrPresent : X86ISA::IntelMP::FloatingPointer
• imDe : Gicv3Its
• imgehl : TAGE_SC_L_64KB_StatisticalCorrector
• imgFormat : HDLcd , VncInput
• imgWriter : HDLcd
• ImgWriter() : ImgWriter
• imHist : TAGE_SC_L_64KB_StatisticalCorrector::SC_64KB_ThreadHistory
• IMLI() : MultiperspectivePerceptron::IMLI
• imli_counter : MultiperspectivePerceptron::ThreadData
• imli_counter_bits : MultiperspectivePerceptron
• imli_mask1 : MultiperspectivePerceptron
• imli_mask4 : MultiperspectivePerceptron
• imliCount : StatisticalCorrector::SCThreadHistory
• imm : ArmISA::BranchImm64 , ArmISA::BranchImm , ArmISA::BranchImmReg64 , ArmISA::BranchImmReg , ArmISA::DataImmOp , ArmISA::DataX1RegImmOp , ArmISA::DataX2RegImmOp , ArmISA::DataXCondCompImmOp , ArmISA::DataXImmOnlyOp , ArmISA::DataXImmOp , ArmISA::FpRegImmOp , ArmISA::FpRegRegImmOp , ArmISA::FpRegRegRegImmOp , ArmISA::MemoryImm64 , ArmISA::MemoryImm , ArmISA::MemoryLiteral64 , ArmISA::MicroIntImmOp , ArmISA::MicroIntImmXOp , ArmISA::MicroMemPairOp , ArmISA::MicroNeonMemOp , ArmISA::PredImmOp , ArmISA::SveBinImmIdxUnpredOp , ArmISA::SveBinImmPredOp , ArmISA::SveBinImmUnpredConstrOp , ArmISA::SveBinImmUnpredDestrOp , ArmISA::SveBinWideImmUnpredOp , ArmISA::SveCmpImmOp , ArmISA::SveComplexIdxOp , ArmISA::SveContigMemSI , ArmISA::SveDotProdIdxOp , ArmISA::SveElemCountOp , ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType > , ArmISA::SveIntCmpImmOp , ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType > , ArmISA::SveMemPredFillSpill , ArmISA::SveMemVecFillSpill , ArmISA::SvePtrueOp , ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType > , ArmISA::SveTerImmUnpredOp , ArmISA::SveUnaryWideImmPredOp , ArmISA::SveUnaryWideImmUnpredOp , ArmISA::SysDC64 , ImmOp64 , ImmOp , McrrOp , MiscRegImmOp64 , MiscRegImplDefined64 , MiscRegRegImmOp64 , MiscRegRegImmOp , MrrcOp , MsrImmOp , PowerISA::IntImmOp , RegImmOp , RegImmRegOp , RegImmRegShiftOp , RegMiscRegImmOp64 , RegMiscRegImmOp , RegRegImmOp , RegRegRegImmOp64 , RegRegRegImmOp , RiscvISA::ImmOp< I > , SparcISA::BlockMemImmMicro , SparcISA::BranchImm13 , SparcISA::IntOpImm , SparcISA::MemImm , SparcISA::PrivImm , TAGE_SC_L_64KB_StatisticalCorrector
• imm1 : ArmISA::BranchImmImmReg64 , ArmISA::DataX1Reg2ImmOp , ArmISA::SveIndexIIOp , ArmISA::SveIndexIROp , RegImmImmOp , RegRegImmImmOp64 , RegRegImmImmOp
• imm2 : ArmISA::BranchImmImmReg64 , ArmISA::DataX1Reg2ImmOp , ArmISA::SveIndexIIOp , ArmISA::SveIndexRIOp , RegImmImmOp , RegRegImmImmOp64 , RegRegImmImmOp
• imm8 : X86ISA::MediaOpImm , X86ISA::RegOpImm
• imm_op : RegOrImmOperand< RegOperand, T >
• immediate : X86ISA::ExtMachInst
• immediateCollected : X86ISA::Decoder
• immediateSize : X86ISA::Decoder
• ImmediateState : X86ISA::Decoder
• ImmediateTypeOneByte : X86ISA::Decoder
• ImmediateTypeThreeByte0F38 : X86ISA::Decoder
• ImmediateTypeThreeByte0F3A : X86ISA::Decoder
• ImmediateTypeTwoByte : X86ISA::Decoder
• ImmediateTypeVex : X86ISA::Decoder
• ImmOp() : ImmOp , RiscvISA::ImmOp< I >
• ImmOp64() : ImmOp64
• imnb : TAGE_SC_L_64KB_StatisticalCorrector
• imp : ArmISA::PMU
• impdefAsNop : ArmISA::ISA
• Impl : BitfieldROType< Base > , BitfieldType< Base > , BitfieldWOType< Base >
• impl_kern_boundary_sync : Shader
• ImplBits : AlphaISA::VAddr , PowerISA::VAddr
• ImplCPU : BaseDynInst< Impl >
• implemented() : ArmISA::ISA::MiscRegLUTEntryInitializer
• implemented32() : ArmSemihosting::SemiCall
• implemented64() : ArmSemihosting::SemiCall
• implicitCast() : sc_core::sc_vector_base
• ImplMask : AlphaISA::VAddr , PowerISA::VAddr
• ImplState : BaseDynInst< Impl > , FullO3CPU< Impl >
• importer : EmbeddedPython
• importerModule : EmbeddedPython
• imr : dp_regs , iGbReg::Regs
• IMR : X86ISA::I8259
• imsc : Pl011
• in_hierarchy() : sc_core::sc_event
• in_if_type : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > >
• in_port_type : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > >
• in_valid : a_new_struct
• in_valid1 : memory
• in_value1 : a_new_struct , memory
• in_value2 : a_new_struct
• Inactive : DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• inAddrMap : AbstractMemory , BackingStoreEntry
• inAllCachesMask : FALRU::CacheTracking
• inArgCount : Brig::BrigDirectiveExecutable
• inb : StatisticalCorrector
• inBuffer : PS2Device
• inc() : Stats::AvgStor , Stats::StatStor , tlm_utils::tlm_quantumkeeper
• inc_use_count() : tlm_utils::instance_specific_extension_container
• incAccessDepth() : Request
• inCache() : BaseCache , BasePrefetcher
• inCachesMask : FALRUBlk
• incHitCount() : BaseCache
• incLoadVRFBankConflictCycles() : GlobalMemPipeline , LocalMemPipeline
• includeSquashInst : DefaultIEWDefaultCommit< Impl >
• incMissCount() : BaseCache
• incoming_link : Message
• incomingData() : BaseRemoteGDB
• increase() : CircularQueue< T >
• increasedIndirectCounter : IndirectMemoryPrefetcher::PrefetchTableEntry
• increasePatternEntryCounter() : SignaturePathPrefetcher , SignaturePathPrefetcherV2
• increaseRefCounter() : LdsState
• inCreditLink : NetworkInterface
• incref() : RefCounted , sc_gem5::Process
• increment() : ArmISA::PMU::PMUEvent
• increment_credit() : InputUnit , OutputUnit , OutVcState
• increment_flit_network_latency() : GarnetNetwork
• increment_flit_queueing_latency() : GarnetNetwork
• increment_hops() : flit
• increment_injected_flits() : GarnetNetwork
• increment_injected_packets() : GarnetNetwork
• increment_packet_network_latency() : GarnetNetwork
• increment_packet_queueing_latency() : GarnetNetwork
• increment_read_pos() : tlm::circular_buffer< T >
• increment_received_flits() : GarnetNetwork
• increment_received_packets() : GarnetNetwork
• increment_total_hops() : GarnetNetwork
• increment_write_pos() : tlm::circular_buffer< T >
• IncrementAfter : ArmISA::RfeOp , ArmISA::SrsOp
• incremental : VncInput::FrameBufferUpdateReq
• IncrementBefore : ArmISA::RfeOp , ArmISA::SrsOp
• incrementCheckCompletions() : RubyTester
• incrementCycleCompletions() : RubyDirectedTester
• incrementReadPointer() : Gicv3Its
• incrementStats() : NetworkInterface
• incrFullStat() : DefaultRename< Impl >
• incrNumPinnedWrites() : PhysRegId
• incrNumPinnedWritesToComplete() : PhysRegId
• incrTos() : ReturnAddrStack
• incWorkItemsBegin() : System
• incWorkItemsEnd() : System
• ind() : QTIsaac< ALPHA >
• inDelta() : sc_gem5::Scheduler
• index() : AlphaISA::TLB , ArmISA::MemoryReg , ArmISA::SveBinIdxUnpredOp , ArmISA::VldSingleOp64 , ArmISA::VstSingleOp64 , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::SQCPort , DataTranslation< ExecContextPtr > , DNR , ecoff_sym , IndirectMemoryPrefetcher::PrefetchTableEntry , LinkedFiber
• Index : Minor::Scoreboard
• index() : MipsISA::TLB , MultiCompressor::MultiCompData , MultiperspectivePerceptron::LocalHistories , PageTableOps , PIFPrefetcher , PowerISA::TLB , RegId , RiscvISA::TLB , RNDXR , SBOOEPrefetcher::Sandbox , StackDistCalc , Stats::DistProxy< Stat > , Stats::ScalarProxy< Stat > , TimeBuffer< T > , TimeBuffer< T >::wire , TimingExprRef , TimingExprSrcReg , TimingSimpleCPU::SplitFragmentSenderState , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , Trace::TarmacBaseRecord::RegEntry , TreePLRURP::TreePLRUReplData , V7LPageTableOps , V8PageTableOps16k , V8PageTableOps4k , V8PageTableOps64k , VirtDescriptor
• Index : VirtDescriptor
• index : VirtQueue::VirtRing< T >::Header
• Index : VirtQueue::VirtRing< T >
• index : X86ISA::EmulEnv , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort , X86ISA::MemOp
• indexingPolicy : AssociativeSet< Entry > , BaseTags
• indexMask : LocalBP , StoreSet
• IndexNodeMap : StackDistCalc
• indirect : Gicv3Its
• indirectCounter : IndirectMemoryPrefetcher::PrefetchTableEntry
• indirectHistory : BPredUnit::PredictorHistory
• indirectHits : BPredUnit
• indirectLookups : BPredUnit
• IndirectMemoryPrefetcher() : IndirectMemoryPrefetcher
• indirectMispredicted : BPredUnit
• indirectMisses : BPredUnit
• IndirectPatternDetectorEntry() : IndirectMemoryPrefetcher::IndirectPatternDetectorEntry
• IndirectPredictor() : IndirectPredictor
• inDrain() : CopyEngine::CopyEngineChannel
• inEvaluate() : sc_gem5::Scheduler
• inExpectedData() : MemChecker::ByteTracker
• inf() : sc_dt::scfx_ieee_double
• infiniteSD : StackDistProbe
• infinity : sc_dt::scfx_rep
• Infinity : StackDistCalc
• inflight : X86ISA::Walker::WalkerState
• inFlightInsts : Minor::Execute::ExecuteThreadInfo
• inflightLoads : GlobalMemPipeline
• inFlightNodes : TraceCPU::ElasticDataGen::HardwareResource
• inflightStores : GlobalMemPipeline
• info : ArmISA::ISA::MiscRegLUTEntryInitializer , BmpWriter::CompleteV1Header
• INFO : Logger
• Info : Stats::DataWrap< Derived, InfoProxyType >
• info() : Stats::DataWrap< Derived, InfoProxyType >
• Info : Stats::DataWrapVec2d< Derived, InfoProxyType > , Stats::DataWrapVec< Derived, InfoProxyType > , Stats::DistBase< Derived, Stor > , Stats::Info
• info() : Stats::InfoAccess
• Info : Stats::SparseHistBase< Derived, Stor > , Stats::Vector2dBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor >
• info : X86ISA::IntelMP::BusHierarchy
• InfoAccess() : Stats::InfoAccess
• InfoProxy() : Stats::InfoProxy< Stat, Base >
• inFUMemInsts : Minor::Execute::ExecuteThreadInfo
• inHierarchy() : sc_gem5::Event
• iniFile : CxxIniFile
• IniFile() : IniFile
• init() : AbstractController , AbstractMemory , AddrMapper , ArmISA::TableWalker , ArmISA::TLB , AtomicSimpleCPU , BaseCache , BaseCPU , BaseGic , BaseKvmCPU , BaseRegOperand , BaseSimpleCPU , BaseTrafficGen , BasicLink , BasicRouter , Bridge , Brig::BrigDirectiveVariable , CacheMemory , CheckerCPU , CoherentXBar , CommMonitor , ComputeUnit , ConditionRegisterState , CpuLocalTimer , CRegOperand , CrossbarSwitch , DirectoryMemory , DistEtherLink , DistIface , DistIface::RecvScheduler , DistIface::Sync , DmaDevice , DMASequencer , DRAMCtrl , DRAMSim2 , DRegOperand , EmbeddedPyBind , EnergyCtrl , EtherDump , ExecStage , ExternalMaster , ExternalSlave , FALRU::CacheTracking , FetchStage , FetchUnit , FullO3CPU< Impl > , FunctionRefOperand , GarnetExtLink , GarnetIntLink , GarnetNetwork , GarnetSyntheticTraffic , Gicv3 , Gicv3CPUInterface , Gicv3Distributor , Gicv3Redistributor , GlobalMemPipeline , GuestABI::PositionInitializer< ABI, Enabled > , GuestABI::PositionInitializer< ABI, typename std::enable_if< std::is_constructible< typename ABI::Position, const ThreadContext * >::value >::type > , HsailCode , IGbE , ImmOperand< T > , Iris::BaseCPU , LabelOperand , ListOperand , LocalMemPipeline , LoopPredictor , LSQUnit< Impl > , LTAGE , MemCheckerMonitor , MemDelay , MemDepUnit< MemDepPred, Impl > , Minor::MinorDynInst , MinorCPU , MSHR::TargetList , MultiperspectivePerceptron , MultiperspectivePerceptronTAGE , Network , NetworkInterface , NoMaliGpu , NoRegAddrOperand , Pc , PerfectSwitch , PioDevice , Process , QoS::FixedPriorityPolicy , QoS::MemCtrl , QoS::MemSinkCtrl , QoS::Policy , Random , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T > , RenameMode< ISA > , RenameMode< ArmISA::ISA > , ReturnAddrStack , Router , RubyDirectedTester , RubyPort , RubyPortProxy , RubyTester , sc_core::sc_vector< T > , sc_dt::sc_bv_base , sc_dt::sc_lv_base , sc_gem5::Kernel , ScheduleStage , ScoreboardCheckStage , SerialLink , Shader , SimObject , SimpleMemory , SimpleNetwork , SimpleRenameMap , SimPoint , SMMUv3 , SRegOperand , StatisticalCorrector , Stats::DistPrint , Stats::Distribution , Stats::Histogram , Stats::SparseHistogram , Stats::SparseHistPrint , Stats::Vector2dBase< Derived, Stor > , Stats::VectorAverageDeviation , Stats::VectorBase< Derived, Stor > , Stats::VectorDistribution , Stats::VectorStandardDeviation , StatTest , StoreSet , Switch , SwitchAllocator , System , TAGEBase::FoldedHistory , TAGEBase , Throttle , TimingSimpleCPU , tlm::circular_buffer< T > , tlm::tlm_dmi , tlm::tlm_fifo< T > , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TraceCPU , TraceGen::InputStream , TrafficGen , Tsunami , UnifiedRenameMap , VecRegisterState , WaitClass , Wavefront , WireBuffer , X86ISA::I82094AA , X86ISA::I8259 , X86ISA::Interrupts
• init_addr() : HsailISA::MemInst
• init_from_vect() : BaseRegOperand , CRegOperand , DRegOperand , ImmOperand< T > , RegOrImmOperand< RegOperand, T > , SRegOperand
• init_net_ptr() : NetworkInterface , Router , Switch
• init_param : System
• initAll() : EmbeddedPyBind , EmbeddedPython
• initBias() : MPP_StatisticalCorrector , StatisticalCorrector
• initCallArgMem() : Wavefront
• initControlWord : X86ISA::I8259
• initDone : sc_gem5::Scheduler
• initEventStreamId : Iris::ThreadContext
• initFoldedHistories() : TAGE_SC_L_TAGE_8KB , TAGEBase
• initFreeList() : PhysRegFile
• initFromIrisInstance() : FastModel::CortexA76TC , Iris::ThreadContext
• initFunc : EmbeddedPyBind
• initGEHLTable() : StatisticalCorrector
• initial_count : Intel8254Timer::Counter
• initialApicId : X86ISA::I82094AA , X86ISA::Interrupts
• InitializationPhase : VncServer
• initialize() : sc_core::sc_byte_heap , sc_core::sc_inout< T > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_int_sigref , sc_core::sc_signed_sigref , sc_core::sc_uint_sigref , sc_core::sc_unsigned_sigref , sc_dp::sc_barrier , sc_dt::sc_concatref , sc_dt::sc_int_bitref_r , sc_dt::sc_int_subref_r , sc_dt::sc_signed_bitref_r , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_bitref_r , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned_bitref_r , sc_dt::sc_unsigned_subref_r , sc_gem5::VcdTraceFile
• initialized : DiskImage , Event
• Initialized : EventBase
• initialized : sc_gem5::VcdTraceFile , TAGEBase
• initializeFlash() : FlashDevice
• initializeMemory() : AbstractNVM , FlashDevice
• initializeMiscRegMetadata() : ArmISA::ISA
• initializeStream() : Prefetcher
• initialLoopAge : LoopPredictor
• initialLoopIter : LoopPredictor
• initialTCounterValue : TAGEBase
• initialTemperature() : ThermalDomain
• initialVal : SatCounter
• initiate() : Check , DirectedGenerator , InvalidateGenerator , SeriesRequestGenerator
• initiateAcc() : BaseO3DynInst< Impl > , GPUDynInst , GPUStaticInst , HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::MemFence , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , RiscvISA::RiscvMacroInst , SparcISA::SparcMacroInst , StaticInst
• initiateAction() : Check
• initiateCheck() : Check
• initiateFetch() : ComputeUnit , FetchUnit
• initiateFlush() : Check
• initiateMemAMO() : BaseDynInst< Impl > , BaseSimpleCPU , ExecContext , Minor::ExecContext , SimpleExecContext , TimingSimpleCPU
• initiateMemRead() : BaseDynInst< Impl > , BaseSimpleCPU , ExecContext , Minor::ExecContext , SimpleExecContext , TimingSimpleCPU
• initiatePrefetch() : Check
• initiateTranslation() : LSQ< Impl >::LSQRequest , LSQ< Impl >::SingleDataRequest , LSQ< Impl >::SplitDataRequest
• initiator() : sc_gem5::TlmInitiatorBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL >
• initiator_payload_type : adapt_ext2gp< BUSWIDTH > , adapt_gp2ext< BUSWIDTH >
• initiator_port : tlm::tlm_slave_to_transport< REQ, RSP >
• initiator_socket : adapt_ext2gp< BUSWIDTH > , adapt_gp2ext< BUSWIDTH > , MultiSocketSimpleSwitchAT , SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
• initiator_socket_type : adapt_ext2gp< BUSWIDTH > , adapt_gp2ext< BUSWIDTH > , CoreDecouplingLTInitiator , MultiSocketSimpleSwitchAT , SimpleATInitiator1 , SimpleATInitiator2 , SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleInitiatorWrapper , SimpleLTInitiator1 , SimpleLTInitiator1_dmi , SimpleLTInitiator2 , SimpleLTInitiator2_dmi , SimpleLTInitiator3 , SimpleLTInitiator3_dmi , SimpleLTInitiator_ext
• initiatorBTransport() : SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
• initiatorNBTransport() : MultiSocketSimpleSwitchAT , SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >
• initiatorNBTransport_core() : MultiSocketSimpleSwitchAT
• Initiators : FastModel::SCGIC::Terminator
• InitiatorSocket : sc_gem5::TlmInitiatorBaseWrapper< BUSWIDTH, FW_IF, BW_IF, N, POL >
• initID32() : ArmISA::ISA
• initID64() : ArmISA::ISA
• InitInterrupt() : X86ISA::InitInterrupt
• initList : sc_gem5::Scheduler
• initLocalHistory() : StatisticalCorrector::SCThreadHistory
• InitMask : EventBase
• initMask : Wavefront
• initMaster() : QoS::PropFairPolicy
• initMasterName() : QoS::FixedPriorityPolicy , QoS::PropFairPolicy
• initMasterObj() : QoS::FixedPriorityPolicy , QoS::PropFairPolicy
• initMemProxies() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• initNetQueues() : AbstractController
• initNetworkPtr() : AbstractController
• initPhase() : sc_gem5::Scheduler
• InitrdSize() : LinuxAlphaSystem , LinuxMipsSystem
• InitrdStart() : LinuxAlphaSystem , LinuxMipsSystem
• InitReg() : ArmISA::ISA
• initSectorTable() : CowDiskImage
• InitStack() : LinuxAlphaSystem , LinuxMipsSystem
• initState() : AlphaProcess , AlphaSystem , ArmFreebsdProcess32 , ArmFreebsdProcess64 , ArmLinuxProcess32 , ArmLinuxProcess64 , ArmProcess32 , ArmProcess64 , ArmSystem , BareMetalRiscvSystem , CxxConfigManager , EmulationPageTable , FastModel::CortexA76 , FreebsdArmSystem , GenericArmSystem , LinuxAlphaSystem , LinuxArmSystem , LinuxX86System , MipsProcess , MultiLevelPageTable< EntryTypes > , PowerLinuxProcess , PowerProcess , Process , RiscvProcess32 , RiscvProcess64 , SimObject , Sparc32Process , Sparc64Process , SparcProcess , SparcSystem , System , TrafficGen , X86ISA::I386Process , X86ISA::Walker::WalkerState , X86ISA::X86_64Process , X86System
• initStatistics() : ExecStage , ScoreboardCheckStage
• initSummary() : StoreTrace
• InitTc : Intel8254Timer
• initTrafficType() : GarnetSyntheticTraffic
• initTransaction() : CoreDecouplingLTInitiator , SimpleATInitiator1 , SimpleATInitiator2 , SimpleLTInitiator1 , SimpleLTInitiator1_dmi , SimpleLTInitiator2 , SimpleLTInitiator2_dmi , SimpleLTInitiator3 , SimpleLTInitiator3_dmi , SimpleLTInitiator_ext
• initTransport() : DistIface , TCPIface
• initValue : sc_core::sc_inout< T > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_logic >
• initVars() : BaseDynInst< Impl > , BaseO3DynInst< Impl >
• initVector : X86ISA::Interrupts
• initVirtMem : Process
• initWithStrOffset() : BaseRegOperand , CRegOperand , DRegOperand , SRegOperand
• injectException() : sc_gem5::Process
• injectGlobalMemFence() : ComputeUnit
• injRate : GarnetSyntheticTraffic
• injVnet : GarnetSyntheticTraffic
• inLowPowerState : DRAMCtrl::Rank
• inLSQ : Minor::MinorDynInst
• inMacroop : Minor::Decode::DecodeThreadInfo
• inMemorySystemLimit : Minor::LSQ
• inMissQueue() : BaseCache , BasePrefetcher
• innerAttrs : ArmISA::TlbEntry
• innerCache : Gicv3Its
• inNetLink : NetworkInterface
• inNode_ptr : NetworkInterface
• ino_t : RiscvLinux64 , Solaris
• inout_if_type : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_out< sc_dt::sc_bigint< W > > , sc_core::sc_out< sc_dt::sc_biguint< W > > , sc_core::sc_out< sc_dt::sc_int< W > > , sc_core::sc_out< sc_dt::sc_uint< W > >
• inout_port_type : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_out< sc_dt::sc_bigint< W > > , sc_core::sc_out< sc_dt::sc_biguint< W > > , sc_core::sc_out< sc_dt::sc_int< W > > , sc_core::sc_out< sc_dt::sc_uint< W > >
• inp : Minor::Decode , Minor::Execute , Minor::Fetch1 , Minor::Fetch2
• input() : Minor::Latch< Data >
• Input() : Minor::Latch< Data >::Input
• inputBuffer : Minor::Decode , Minor::Execute , Minor::Fetch2
• InputBuffer() : Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits >
• inputChar : AlphaAccess , MipsAccess
• inputFull : X86ISA::I8042
• inputIndex : Minor::Decode::DecodeThreadInfo , Minor::Execute::ExecuteThreadInfo , Minor::Fetch2::Fetch2ThreadInfo
• inputParam1 : UFSHostDevice::UTPUPIUTaskReq
• inputParam2 : UFSHostDevice::UTPUPIUTaskReq
• inputParam3 : UFSHostDevice::UTPUPIUTaskReq
• inputs : sc_core::sc_signal_resolved , sc_core::sc_signal_rv< W > , X86ISA::I82094AA , X86ISA::I8259
• InputStream() : TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream
• InputUnit() : InputUnit
• inputWire : Minor::Latch< Data >::Input
• inPwrIdleState() : DRAMCtrl::Rank
• inRange() : BaseCache
• inRefIdleState() : DRAMCtrl::Rank
• inReset() : sc_gem5::Process
• inRetry : DmaPort
• inSameSpatialRegion() : PIFPrefetcher::CompactorEntry
• inScalarBank() : ArmISA::VfpMacroOp
• inSecureBlock() : SMMUv3
• inSecureState() : Gicv3CPUInterface
• insert() : AddrRangeMap< V, max_cache_size > , AlphaISA::TLB , ArmISA::TLB , CacheBlk , DependencyGraph< DynInstPtr > , EventQueue , flitBuffer , InstructionQueue< Impl > , LSQUnit< Impl > , MemDepUnit< MemDepPred, Impl > , Minor::LSQ::StoreBuffer , MipsISA::TLB , MultiperspectivePerceptron , PowerISA::TLB , QueuedPrefetcher , RiscvISA::TLB , SBOOEPrefetcher::Sandbox , sc_core::sc_event_and_expr , sc_core::sc_event_and_list , sc_core::sc_event_or_expr , sc_core::sc_event_or_list , SectorSubBlk , SimpleAddressMap , SimpleCache , SparcISA::TLB , SparcISA::TlbMap , SymbolTable , TempCacheBlk , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list , tlm_utils::time_ordered_list< PAYLOAD > , Trie< Key, Value > , X86ISA::GpuTLB , X86ISA::TLB
• insert_flit() : OutputUnit
• insert_in_cache() : tlm::tlm_array< T >
• insertAddr() : MemFootprintProbe
• insertAt() : MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• insertBarrier() : InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl >
• insertBefore() : Event
• insertBlock() : BaseSetAssoc , BaseTags , CompressedTags , FALRU , SectorTags
• insertCRField() : PowerISA::PowerStaticInst
• insertedLoads : MemDepUnit< MemDepPred, Impl >
• insertedStores : MemDepUnit< MemDepPred, Impl >
• insertEntry() : AssociativeSet< Entry >
• insertFlit() : VirtualChannel
• insertHardBreak() : BaseRemoteGDB
• insertInst() : ROB< Impl >
• insertIntoDelayQueue() : BOPPrefetcher
• insertIntoRR() : BOPPrefetcher
• insertions : SMMUv3BaseCache
• insertionsByStageLevel : WalkCache
• insertKernel() : GPUCoalescer
• insertLoad() : LSQ< Impl > , LSQUnit< Impl > , StoreSet
• insertModhistSpec() : MultiperspectivePerceptron
• insertModpathSpec() : MultiperspectivePerceptron
• insertNonSpec() : InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl >
• insertRecency() : MultiperspectivePerceptron::ThreadData
• insertRequest() : GPUCoalescer , Sequencer
• inserts : ArmISA::TLB
• insertScheduledWakeupTime() : Consumer
• insertSoftBreak() : BaseRemoteGDB
• insertStore() : LSQ< Impl > , LSQUnit< Impl > , StoreSet
• insertTableEntry() : ArmISA::TableWalker
• insertThread() : FullO3CPU< Impl >
• inService : QueueEntry
• inst : BaseSimpleCPU , BPredUnit::PredictorHistory , DependencyEntry< DynInstPtr > , InstructionQueue< Impl >::FUCompletion , LSQ< Impl >::LSQSenderState , LSQUnit< Impl >::LSQEntry , LSQUnit< Impl >::WritebackEvent , MemDepUnit< MemDepPred, Impl >::MemDepEntry , Minor::BranchData , Minor::ExecContext , Minor::LSQ::LSQRequest , Minor::QueuedInst , TimingExprEvalContext , Trace::TarmacParserRecord::TarmacParserRecordEvent
• INST_FETCH : Request
• instAccesses : ArmISA::TLB
• instAddr() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , DefaultCommit< Impl > , FullO3CPU< Impl > , GenericISA::PCStateBase , GPUStaticInst , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , StridePrefetcher::StrideEntry , ThreadContext
• install() : LSQ< Impl >::LSQRequest , sc_gem5::Reset
• installBp() : Iris::ThreadContext
• installGlobals() : SparcISA::ISA
• installWindow() : SparcISA::ISA
• instance() : DrainManager , Event , GpuDispatcher , Kvm , RubyDummyPort , sc_dt::sc_global< T > , tlm::tlm_global_quantum , tlm_utils::instance_specific_extension_container_pool
• instance_specific_extension_accessor() : tlm_utils::instance_specific_extension_accessor , tlm_utils::instance_specific_extension_carrier , tlm_utils::instance_specific_extension_container
• instance_specific_extension_carrier() : tlm_utils::instance_specific_extension_carrier , tlm_utils::instance_specific_extension_container
• instance_specific_extension_container() : tlm_utils::instance_specific_extension_container
• instance_specific_extension_container_pool : tlm_utils::instance_specific_extension_container , tlm_utils::instance_specific_extension_container_pool
• instance_specific_extensions_per_accessor : tlm_utils::instance_specific_extension_container , tlm_utils::instance_specific_extensions_per_accessor
• instanceCounter : Event
• instanceRegistryChanged() : Iris::ThreadContext
• instantiate() : CxxConfigManager
• instantiateEntry() : BaseReplacementPolicy , BRRIPRP , FIFORP , LFURP , LRURP , MRURP , RandomRP , SecondChanceRP , TreePLRURP , WeightedLRUPolicy
• instBytes : X86ISA::Decoder
• InstBytes() : X86ISA::Decoder::InstBytes
• InstCacheMap : X86ISA::Decoder
• instCacheMap : X86ISA::Decoder
• instcfg : StreamTableEntry
• instCnt : BaseCPU
• instCount() : BaseCPU
• instcount : FullO3CPU< Impl >
• instCount : Trace::TarmacTracerRecord::TraceInstEntry
• instCyclesSALU : ComputeUnit
• instCyclesVALU : ComputeUnit
• instDone : AlphaISA::Decoder , ArmISA::Decoder , FullO3CPU< Impl > , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• InstEntry() : Trace::TarmacBaseRecord::InstEntry
• InstExecInfo() : ElasticTrace::InstExecInfo
• InstFault() : RiscvISA::InstFault
• instFetchInstReturned : FetchStage
• instFlags : BaseDynInst< Impl >
• instHits : ArmISA::TLB
• InstId() : Minor::InstId
• InstIntRegOffsets : SparcISA::ISA
• instIsHeadInst() : Minor::Execute
• instIsRightStream() : Minor::Execute
• InstIt : ROB< Impl >
• instLastTick : TraceCPU::FixedRetryGen
• instList : Checker< Impl > , FullO3CPU< Impl > , InstructionQueue< Impl > , MemDepUnit< MemDepPred, Impl > , ROB< Impl >
• instListIt : BaseDynInst< Impl >
• InstListIt : Checker< Impl >
• instMap : GenericISA::BasicDecodeCache , RiscvISA::Decoder , X86ISA::Decoder
• instMasterId() : BaseCPU
• instMasterID : TraceCPU
• instMisses : ArmISA::TLB
• instMnem : X86ISA::X86MicroopBase
• instName : RiscvISA::UnimplementedFault
• instNum : ElasticTrace::TraceInfo , GPUStaticInst
• inStoreBuffer : Minor::MinorDynInst
• InstPBTrace() : Trace::InstPBTrace
• InstPBTraceRecord : Trace::InstPBTrace , Trace::InstPBTraceRecord
• instPort : BaseKvmCPU , SimpleMemobj
• InstPtr : Trace::TarmacTracer , Trace::TarmacTracerRecord
• instQueue : DefaultIEW< Impl >
• InstQueue : DefaultRename< Impl >
• instQueue : Trace::TarmacTracer
• instrAnnotate() : ArmISA::ArmFault
• instReady() : AlphaISA::Decoder , ArmISA::Decoder , MipsISA::Decoder , PowerISA::Decoder , RiscvISA::Decoder , SparcISA::Decoder , X86ISA::Decoder
• InstRecord() : Trace::InstRecord
• instRecord : Trace::TarmacParserRecord
• InstRegIndex() : X86ISA::InstRegIndex
• instResult : BaseDynInst< Impl >
• InstResult() : InstResult
• instrExecuted : ExecStage
• instruction() : LSQ< Impl >::LSQRequest , LSQUnit< Impl >::LSQEntry
• instructionBuffer : Wavefront
• instructionBufferHasBranch() : Wavefront
• InstructionCacheMaintenance : ArmISA::ArmFault
• InstructionQueue() : InstructionQueue< Impl >
• instructions : ControlFlowInfo
• insts : DefaultDecode< Impl > , DefaultDecodeDefaultRename< Impl > , DefaultFetchDefaultDecode< Impl > , DefaultIEW< Impl > , DefaultIEWDefaultCommit< Impl > , DefaultRename< Impl > , DefaultRenameDefaultIEW< Impl > , HsaCode , IssueStruct< Impl > , Minor::ForwardInstData , SimPoint::BBInfo
• instsBeingCommitted : Minor::Execute::ExecuteThreadInfo
• instsCommitted : DefaultCommit< Impl >
• instSeqNum : DefaultRename< Impl >::RenameHistory
• instShift : SimpleIndirectPredictor
• instShiftAmt : BPredUnit , DefaultBTB , TAGEBase
• instsInProgress : DefaultRename< Impl >
• instSize() : ArmISA::ArmStaticInst , DefaultFetch< Impl > , GPUStaticInst , HsailISA::HsailGPUStaticInst , KernelLaunchStaticInst , Trace::TarmacTracerRecord::TraceInstEntry
• instsToExecute : InstructionQueue< Impl >
• instsToReplay : MemDepUnit< MemDepPred, Impl >
• instToCommit() : DefaultIEW< Impl >
• instToWaitFor : Minor::MinorDynInst
• instTraceFile : TraceCPU
• InstTracer() : Trace::InstTracer
• instTraceStream : ElasticTrace
• INT : ItsCommand
• int : sc_dt::sc_fxnum_fast , sc_dt::sc_fxval_fast
• INT_ACTIVE : Gicv3
• INT_ACTIVE_PENDING : Gicv3
• INT_BITS_MAX : GicV2
• INT_BUS_ERROR : HDLcd
• Int_Clear : HDLcd
• INT_CONFIG : MmioVirtIO
• INT_EDGE_TRIGGERED : Gicv3
• INT_INACTIVE : Gicv3
• INT_LEVEL_SENSITIVE : Gicv3
• INT_LINES_MAX : GicV2
• int_mask : HDLcd
• Int_Mask : HDLcd
• INT_MASK_M : ArmISA::Interrupts
• INT_MASK_P : ArmISA::Interrupts
• INT_MASK_T : ArmISA::Interrupts
• INT_PENDING : Gicv3
• int_rawstat : HDLcd
• Int_RawStat : HDLcd
• Int_Status : HDLcd
• INT_UNDERRUN : HDLcd
• INT_USED_RING : MmioVirtIO
• INT_VSYNC : HDLcd
• intAluAccesses : InstructionQueue< Impl >
• IntAssignment() : X86ISA::IntelMP::IntAssignment
• intBase : GenericArmPciHost
• intClear() : HDLcd
• IntClear : PL031 , Sp804::Timer
• intClock() : IGbE
• intConfig : GicV2
• intCount : GenericArmPciHost
• intCtl : Iob
• intDelay : AmbaIntDevice , Pl011
• integer : cp::Format , InstResult::MultiResult
• integrationTestEnabled : Sp805
• Intel8254Timer() : Intel8254Timer
• IntelTrace() : Trace::IntelTrace
• IntelTraceRecord() : Trace::IntelTraceRecord
• intEnable : A9GlobalTimer::Timer , CpuLocalTimer::Timer , Sp804::Timer
• intEnabled : GicV2::BankedRegs , GicV2
• Interal : Iob
• interEvent : IGbE
• interface : EtherLink
• Interface() : EtherLink::Interface , EtherSwitch::Interface
• interface : EtherSwitch::SwitchTableEntry , EtherTapBase , NSGigE , sc_core::sc_bind_proxy , sc_core::sc_export< IF > , sc_gem5::Port::Binding , sc_gem5::ScInterfaceWrapper< IF > , Sinic::Base
• Interface() : Sinic::Interface
• interfaceCallback : SerialDevice
• interfaceId : EtherSwitch::Interface
• interfaces : EtherSwitch
• InterfaceTest : X86ISA::I8042
• interleaved() : AddrRange
• intermediateHeader : X86ISA::SMBios::SMBiosTable::SMBiosHeader
• IntermediateHeader() : X86ISA::SMBios::SMBiosTable::SMBiosHeader::IntermediateHeader
• internal() : sc_gem5::Process
• internalMergeFrom() : SubBlock
• internalMergeTo() : SubBlock
• InternalProcReg : AlphaISA::ISA
• InternalScEvent() : sc_gem5::InternalScEvent
• interpImage : Process
• interpreter : ElfObject
• interrupt : ArmISA::PMU , DefaultCommit< Impl >
• Interrupt : Iob , Minor::BranchData
• interrupt : MmioVirtIO
• interruptDeliveryPending : PciVirtIO
• InterruptFault() : RiscvISA::InterruptFault
• InterruptLevel() : SparcISA::Interrupts
• InterruptLevelN() : SparcISA::InterruptLevelN
• interruptLine : PCIConfig , PciDevice
• interruptMap : NoMaliGpu
• InterruptMask : ArmISA::Interrupts
• interruptPending : DefaultFetch< Impl > , TimeBufStruct< Impl >::commitComm
• interruptPin : PCIConfig , PciHost::DeviceInterface
• interruptPriority : Minor::Execute
• interrupts : AlphaISA::Interrupts
• Interrupts() : AlphaISA::Interrupts
• interrupts : ArmISA::Interrupts
• Interrupts() : ArmISA::Interrupts
• interrupts : BaseCPU
• Interrupts() : MipsISA::Interrupts , PowerISA::Interrupts , RiscvISA::Interrupts
• interrupts : SparcISA::Interrupts
• Interrupts() : SparcISA::Interrupts , X86ISA::Interrupts
• interruptsPending() : MipsISA::Interrupts
• interruptStatus : MmioVirtIO
• interruptType : X86ISA::IntelMP::IntAssignment
• intersect() : SparcISA::TlbMap
• intersectionIsEmpty() : NetDest , Set
• intersectionIsNotEmpty() : NetDest
• intersects() : AddrRange , AddrRangeMap< V, max_cache_size > , CacheBlk::Lock
• interval() : CPUProgressEvent , Intel8254Timer::Counter::CounterEvent , MC146818::RTCEvent , MemTest
• intervalCount : SimPoint
• intervalDrift : SimPoint
• intervalSize : SimPoint
• intEvent : Pl011 , Pl111
• intGroup : GicV2::BankedRegs , GicV2
• inTick : IGbE
• intid : Gicv3CPUInterface::hppi_t
• INTID_NONSECURE : Gicv3
• INTID_SECURE : Gicv3
• INTID_SPURIOUS : Gicv3
• inTiming() : sc_gem5::Scheduler
• IntImmOp() : PowerISA::IntImmOp
• intInstQueueReads : InstructionQueue< Impl >
• intInstQueueWakeupAccesses : InstructionQueue< Impl >
• intInstQueueWrites : InstructionQueue< Impl >
• intInstructions : Minor::Fetch2
• intLatency : GicV2
• intList : UnifiedFreeList
• intlvMatch : AddrRange
• intMan : Iob
• intMap : UnifiedRenameMap
• intMask() : HDLcd
• IntMask : PL031
• intMasterId : Request
• intMasterPort : X86ISA::I82094AA , X86ISA::Interrupts
• IntMasterPort() : X86ISA::IntMasterPort< Device >
• intNum : A9GlobalTimer::Timer , AmbaDmaDevice , AmbaIntDevice , ArmInterruptPin , Gicv3Its , Pl011 , Sp804::Timer , UFSHostDevice
• intNumHyp : Gicv3Its
• intNumToBit() : GicV2
• intNumToWord() : GicV2
• intOffset : ThreadContext
• IntOp() : PowerISA::IntOp
• IntOpImm() : SparcISA::IntOpImm
• IntOpImm10() : SparcISA::IntOpImm10
• IntOpImm11() : SparcISA::IntOpImm11
• IntOpImm13() : SparcISA::IntOpImm13
• intPin : X86ISA::Cmos::X86RTC , X86ISA::I8254
• intPolicy : GenericArmPciHost
• intPriority : GicV2::BankedRegs , GicV2
• intr_flag : AlphaISA::ISA
• intr_sum_type : Malta , Tsunami
• intRaise() : HDLcd
• intRaised : Sp805
• InTranslation : Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• intrClear() : IdeDisk , PciDevice
• intrClockFrequency : AlphaAccess , MipsAccess
• IntrControl() : IntrControl
• intrctrl : CopyEngineReg::Regs , Platform
• intrDelay : NSGigE , Sinic::Base
• intReg32Ids : Iris::ThreadContext
• intReg32IdxNameMap : FastModel::CortexA76TC
• intReg64Ids : Iris::ThreadContext
• intReg64IdxNameMap : FastModel::CortexA76TC
• intRegFile : PhysRegFile
• intRegfileReads : FullO3CPU< Impl >
• intRegfileWrites : FullO3CPU< Impl >
• intRegIds : PhysRegFile
• IntRegInfo() : ArmV8KvmCPU::IntRegInfo
• intRegMap : ArmISA::ISA , ArmV8KvmCPU , SparcISA::ISA
• intRegs : SimpleThread
• intRenameLookups : DefaultRename< Impl >
• intResult : ThreadContext
• intrEvent : NSGigE , Sinic::Base
• intrFreq : AlphaSystem
• IntrMask : Sinic::Device
• IntRotateOp() : PowerISA::IntRotateOp
• intrPending : IdeDisk
• intrPost() : IdeController , IdeDisk , PciDevice
• IntrStatus : Sinic::Device
• intrTick : NSGigE , Sinic::Base
• ints : ThreadContext
• IntShiftOp() : PowerISA::IntShiftOp
• intSignalType() : Gicv3CPUInterface
• IntSinkPin() : IntSinkPin< Device >
• IntSinkPinBase() : IntSinkPinBase
• intSlavePort : X86ISA::Interrupts
• IntSlavePort() : X86ISA::IntSlavePort< Device >
• IntSourcePin() : IntSourcePin< Device >
• IntSourcePinBase : IntSinkPinBase , IntSourcePinBase
• intState() : NoMaliGpu
• intstatus : AlphaISA::Interrupts
• intStatus : ArmISA::Interrupts
• IntStatus : Gicv3
• intStatus() : Gicv3Distributor , Gicv3Redistributor , HDLcd , IdeController , SparcISA::Interrupts , Uart8250 , Uart
• IntStatusReg : A9GlobalTimer::Timer
• intTimer : CpuLocalTimer::Timer
• IntTriggerType : Gicv3
• intType : Gicv3Its
• intWatchdog : CpuLocalTimer::Timer
• intWidth : ArmISA::ArmStaticInst
• inUpdate() : sc_gem5::Scheduler
• INV : ItsCommand
• inv() : ItsCommand
• invAddrLoads : LSQUnit< Impl >
• invAddrSwpfs : LSQUnit< Impl >
• invalid() : ArmISA::TableWalker::L2Descriptor
• Invalid : ArmISA::TableWalker::LongDescriptor
• invalid : SparcISA::PageTableEntry
• invalid_01() : sc_dt::sc_logic
• invalid_index() : sc_dt::sc_int_base , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned
• invalid_init() : sc_dt::sc_signed , sc_dt::sc_unsigned
• invalid_length() : sc_dt::sc_int_base , sc_dt::sc_uint_base
• invalid_range() : sc_dt::sc_int_base , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned
• invalid_value() : sc_dt::sc_bit , sc_dt::sc_logic
• invalidate() : AccessMapPatternMatching::AccessMapEntry , AssociativeSet< Entry > , BaseReplacementPolicy , BaseSetAssoc , BaseTags , BRRIPRP , CacheBlk , DeltaCorrelatingPredictionTables::DCPTEntry , FALRU , FIFORP , IndirectMemoryPrefetcher::IndirectPatternDetectorEntry , IndirectMemoryPrefetcher::PrefetchTableEntry , IrregularStreamBufferPrefetcher::AddressMappingEntry , LFURP , LRURP , MemBackdoor , MRURP , RandomRP
• INVALIDATE : Request
• invalidate() : SecondChanceRP , SectorSubBlk , SectorTags , SignaturePathPrefetcher::PatternEntry , SimpleLTInitiator1_dmi , SimpleLTInitiator_ext , STeMSPrefetcher::ActiveGenerationTableEntry , StridePrefetcher::StrideEntry , TaggedEntry , TempCacheBlk , TreePLRURP , WeightedLRUPolicy
• invalidate_direct_mem_ptr() : sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SimpleLTInitiator1 , SimpleLTInitiator1_dmi , SimpleLTInitiator2_dmi , SimpleLTInitiator3_dmi , SimpleLTInitiator_ext , tlm::tlm_bw_direct_mem_if , tlm_utils::callback_binder_bw< TYPES > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::bw_process
• invalidate_dmi_method() : SimpleLTTarget1 , SimpleLTTarget_ext
• invalidate_dmi_pointers() : adapt_ext2gp< BUSWIDTH > , adapt_gp2ext< BUSWIDTH >
• invalidateAll() : ARMArchTLB , ConfigCache , IPACache , SMMUTLB , WalkCache , X86ISA::GpuTLB
• invalidateASID() : ARMArchTLB , SMMUTLB , WalkCache
• invalidateBlock() : BaseCache
• InvalidateDirectMemPtr : tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL >::process , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::process
• invalidateDmi() : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• invalidateDMIPointers() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS > , SimpleBusLT< NR_OF_INITIATORS, NR_OF_TARGETS >
• InvalidateGenerator() : InvalidateGenerator
• invalidateIPA() : IPACache
• invalidateIPAA() : IPACache
• invalidateMiscReg() : ArmISA::TLB
• invalidateNonGlobal() : X86ISA::GpuTLB
• InvalidateReq : MemCmd
• InvalidateResp : MemCmd
• invalidateSC() : Sequencer
• invalidateSID() : ConfigCache , SMMUTLB
• invalidateSSID() : ConfigCache , SMMUTLB
• invalidateSubBlk() : SectorBlk
• invalidateVA() : ARMArchTLB , SMMUTLB , WalkCache
• invalidateVAA() : ARMArchTLB , SMMUTLB , WalkCache
• invalidateVisitor() : BaseCache
• invalidateVMID() : ARMArchTLB , IPACache , SMMUTLB , WalkCache
• invalidationCallbacks : MemBackdoor
• InvalidCmd : MemCmd
• InvalidDestError : MemCmd
• invalidName : CxxConfigParams
• InvalidOpcode() : X86ISA::InvalidOpcode
• invalidPredictorIndex : TournamentBP
• InvalidTSS() : X86ISA::InvalidTSS
• INVALL : ItsCommand
• invall() : ItsCommand
• invariant_regs : ArmKvmCPU
• invCallback() : VIPERCoalescer
• invert() : sc_dt::sc_signed , sc_dt::sc_unsigned
• inVisit : CxxConfigManager
• invL1() : VIPERCoalescer
• invldMasterId : Request
• invldPid : BaseCPU
• invoke() : AlphaISA::AlphaFault , AlphaISA::ArithmeticFault , AlphaISA::DtbFault , AlphaISA::ItbFault , AlphaISA::ItbPageFault , AlphaISA::NDtbMissFault , ArmISA::AbortFault< T > , ArmISA::ArmFault , ArmISA::ArmSev , ArmISA::PCAlignmentFault , ArmISA::Reset , ArmISA::SecureMonitorCall , ArmISA::SupervisorCall , ArmISA::SystemError , ArmISA::UndefinedInstruction , ArmISA::VirtualDataAbort , FaultBase , GenericAlignmentFault , GenericISA::M5DebugFault , GenericISA::M5DebugOnceFault< Flavor > , GenericPageTableFault , MipsISA::AddressFault< T > , MipsISA::CoprocessorUnusableFault , MipsISA::MipsFaultBase , MipsISA::NonMaskableInterrupt , MipsISA::ResetFault , MipsISA::SoftResetFault , MipsISA::TlbFault< T > , ReExec , RiscvISA::Reset , RiscvISA::RiscvFault , SparcISA::FastDataAccessMMUMiss , SparcISA::FastInstructionAccessMMUMiss , SparcISA::FillNNormal , SparcISA::PowerOnReset , SparcISA::SparcFaultBase , SparcISA::SpillNNormal , SparcISA::TrapInstruction , SyscallRetryFault , UnimpFault , X86ISA::InitInterrupt , X86ISA::InvalidOpcode , X86ISA::PageFault , X86ISA::StartupInterrupt , X86ISA::UnimpInstFault , X86ISA::X86Abort , X86ISA::X86FaultBase , X86ISA::X86Trap
• invoke64() : ArmISA::ArmFault
• invokeSE() : RiscvISA::BreakpointFault , RiscvISA::IllegalFrmFault , RiscvISA::IllegalInstFault , RiscvISA::RiscvFault , RiscvISA::SyscallFault , RiscvISA::UnimplementedFault , RiscvISA::UnknownInstFault
• invwbL1() : VIPERCoalescer
• io : Malta , Tsunami
• ioApic : SouthBridge
• IOAPIC() : X86ISA::IntelMP::IOAPIC
• Iob() : Iob
• iobJBusAddr : Iob
• iobJBusSize : Iob
• iobManAddr : Iob
• iobManSize : Iob
• ioctl() : BaseKvmCPU , ClDriver , EmulatedDriver , Kvm , KvmDevice , KvmVM , PerfKvmCounter
• ioctlRun() : BaseKvmCPU
• ioe : Pl111
• ioEnable : NSGigE
• ioEnabled : IdeController
• IOIntAssignment() : X86ISA::IntelMP::IOIntAssignment
• iopt : pdr
• ioptBase : ecoff_fdr
• ioptMax : ecoff_symhdr
• IoSel : RealViewCtrl
• ioShift : IdeController
• iov_base : ArmFreebsd32::tgt_iovec , ArmFreebsd64::tgt_iovec , ArmLinux32::tgt_iovec , ArmLinux64::tgt_iovec , Linux::tgt_iovec , OperatingSystem::tgt_iovec , X86Linux64::tgt_iovec
• iov_len : ArmFreebsd32::tgt_iovec , ArmFreebsd64::tgt_iovec , ArmLinux32::tgt_iovec , ArmLinux64::tgt_iovec , Linux::tgt_iovec , OperatingSystem::tgt_iovec , X86Linux64::tgt_iovec
• ip() : Net::IpAddress , RiscvISA::Interrupts
• Ip6Ptr : Net::EthPtr , Net::Ip6Ptr
• ipa : IPACache::Entry , SMMUEvent
• IPACache() : IPACache
• ipaCache : SMMUv3
• ipaCacheEnable : SMMUv3
• IpAddress() : Net::IpAddress
• ipaLat : SMMUv3
• ipaMask : IPACache::Entry
• ipaSem : SMMUv3
• ipc : ComputeUnit , FullO3CPU< Impl > , Minor::MinorStats , Pl111
• ipd : IndirectMemoryPrefetcher
• ipdEntryTrackingMisses : IndirectMemoryPrefetcher
• ipdFirst : ecoff_fdr
• ipdInstNum() : GPUStaticInst
• ipdMax : ecoff_symhdr
• ipi_pending : Malta , Tsunami
• ipint : TsunamiCChip
• iplLast : AlphaISA::Kernel::Statistics
• iplLastTick : AlphaISA::Kernel::Statistics
• IpNetmask() : Net::IpNetmask
• IpPtr : Net::EthPtr , Net::IpPtr
• ipr : AlphaISA::ISA
• iPred : BPredUnit
• IPredEntry() : SimpleIndirectPredictor::IPredEntry
• IprEvent() : TimingSimpleCPU::IprEvent
• ips : ContextDescriptor
• IpWithPort() : Net::IpWithPort
• IQ : DefaultIEW< Impl > , DefaultRename< Impl > , SimpleCPUPolicy< Impl >
• iqBranchInstsIssued : InstructionQueue< Impl >
• iqCount() : DefaultFetch< Impl > , TimeBufStruct< Impl >::iewComm
• iqEntries : DefaultRename< Impl >::FreeEntries
• IqEntry : BaseDynInst< Impl >
• iqFloatInstsIssued : InstructionQueue< Impl >
• iqInstsAdded : InstructionQueue< Impl >
• iqInstsIssued : InstructionQueue< Impl >
• iqIntInstsIssued : InstructionQueue< Impl >
• iqMemInstsIssued : InstructionQueue< Impl >
• iqMiscInstsIssued : InstructionQueue< Impl >
• iqNonSpecInstsAdded : InstructionQueue< Impl >
• iqPolicy : InstructionQueue< Impl >
• iqPtr : InstructionQueue< Impl >::FUCompletion , MemDepUnit< MemDepPred, Impl >
• iqSquashedInstsExamined : InstructionQueue< Impl >
• iqSquashedInstsIssued : InstructionQueue< Impl >
• iqSquashedNonSpecRemoved : InstructionQueue< Impl >
• iqSquashedOperandsExamined : InstructionQueue< Impl >
• ir0 : ContextDescriptor
• ir1 : ContextDescriptor
• IRM : Gicv3Distributor
• irq_ctrl : SMMURegs
• irq_ctrlack : SMMURegs
• irqActive : Gicv3Distributor , Gicv3Redistributor
• irqAffinityRouting : Gicv3Distributor
• irqAsserted : ArmKvmCPU , BaseArmKvmCPU
• irqConfig : Gicv3Distributor , Gicv3Redistributor
• irqEnabled : Gicv3Distributor , Gicv3Redistributor
• irqGroup : Gicv3Distributor , Gicv3Redistributor
• irqGrpmod : Gicv3Distributor , Gicv3Redistributor
• irqHyp : GenericTimer::CoreTimers
• irqNsacr : Gicv3Distributor , Gicv3Redistributor
• irqPending : Gicv3Distributor , Gicv3Redistributor
• irqPhysNS : GenericTimer::CoreTimers
• irqPhysS : GenericTimer::CoreTimers
• irqPriority : Gicv3Distributor , Gicv3Redistributor
• irqVirt : GenericTimer::CoreTimers
• IRR : X86ISA::I8259
• IrregularStreamBufferPrefetcher() : IrregularStreamBufferPrefetcher
• IRRV : X86ISA::Interrupts
• is_01() : sc_dt::sc_bitref_r< T > , sc_dt::sc_bv_base , sc_dt::sc_concref_r< X, Y > , sc_dt::sc_logic , sc_dt::sc_lv_base , sc_dt::sc_subref_r< X >
• is_device : ArmV8KvmCPU::MiscRegInfo
• is_dmi_allowed() : tlm::tlm_generic_payload
• is_empty() : tlm::circular_buffer< T > , tlm::tlm_fifo< T >
• is_free_signal() : Credit
• is_from() : ExtensionPool< T >
• is_full() : tlm::circular_buffer< T > , tlm::tlm_fifo< T >
• is_imm : RegOrImmOperand< RegOperand, T >
• is_inf() : sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::scfx_ieee_double , sc_dt::scfx_ieee_float , sc_dt::scfx_rep
• is_nan() : sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::scfx_ieee_double , sc_dt::scfx_ieee_float , sc_dt::scfx_rep
• is_neg() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::scfx_rep
• is_none_allowed() : tlm::tlm_dmi
• is_normal() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::scfx_ieee_double , sc_dt::scfx_ieee_float , sc_dt::scfx_rep
• is_read() : tlm::tlm_generic_payload
• is_read_allowed() : tlm::tlm_dmi
• is_read_write_allowed() : tlm::tlm_dmi
• is_reset() : sc_core::sc_unwind_exception
• is_response_error() : tlm::tlm_generic_payload
• is_response_ok() : tlm::tlm_generic_payload
• is_stage() : flit
• is_subnormal() : sc_dt::scfx_ieee_double , sc_dt::scfx_ieee_float
• is_suppressed() : sc_core::sc_report
• is_unwinding() : sc_core::sc_process_handle
• is_vc_idle() : OutputUnit
• is_write() : tlm::tlm_generic_payload
• is_write_allowed() : tlm::tlm_dmi
• is_zero() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::scfx_ieee_double , sc_dt::scfx_ieee_float , sc_dt::scfx_rep
• ISA() : AlphaISA::ISA
• isa : ArmISA::BaseISADevice
• ISA() : ArmISA::ISA
• isa : FullO3CPU< Impl >
• ISA() : MipsISA::ISA , PowerISA::ISA , RiscvISA::ISA
• isa : SimpleThread
• ISA() : SparcISA::ISA , X86ISA::ISA
• isAA64() : Gicv3CPUInterface
• isaac() : QTIsaac< ALPHA >
• isAbort : DistIface::Sync
• isAbsolute() : OutputDirectory
• isAcquire() : GPUDynInst , GPUStaticInst , Request
• isAcquireRelease() : GPUDynInst , GPUStaticInst
• isActive() : DmaReadFifo
• IsaFake() : IsaFake
• isAlignmentFault() : AlphaISA::AlignmentFault
• isAllZeros() : LSQUnit< Impl >::SQEntry
• isALU() : GPUDynInst , GPUStaticInst
• isAnyOutstandingRequest() : LSQ< Impl >::LSQRequest
• isArgLoad() : GPUDynInst , GPUStaticInst
• isArgSeg() : GPUDynInst , GPUStaticInst
• isArgSegment() : Request
• isAtCommit() : BaseDynInst< Impl >
• isAtomic() : BaseDynInst< Impl > , GPUDynInst , GPUStaticInst
• IsAtomic : LSQ< Impl >::LSQRequest
• isAtomic() : LSQ< Impl >::LSQRequest , Request , StaticInst
• isAtomicAdd() : GPUDynInst , GPUStaticInst
• isAtomicAnd() : GPUDynInst , GPUStaticInst
• isAtomicCAS() : GPUDynInst , GPUStaticInst
• isAtomicDec() : GPUDynInst , GPUStaticInst
• isAtomicExch() : GPUDynInst , GPUStaticInst
• isAtomicInc() : GPUDynInst , GPUStaticInst
• isAtomicMax() : GPUDynInst , GPUStaticInst
• isAtomicMin() : GPUDynInst , GPUStaticInst
• isAtomicMode() : System
• isAtomicNoRet() : GPUDynInst , GPUStaticInst
• isAtomicNoReturn() : Request
• isAtomicOp() : Packet
• isAtomicOr() : GPUDynInst , GPUStaticInst
• isAtomicRet() : GPUDynInst , GPUStaticInst
• isAtomicReturn() : Request
• isAtomicSub() : GPUDynInst , GPUStaticInst
• isAtomicXor() : GPUDynInst , GPUStaticInst
• isAtsRequest : SMMUTranslRequest
• isAttached() : BaseRemoteGDB
• isAutoDelete() : Event
• isAvailable() : TraceCPU::ElasticDataGen::HardwareResource
• isBAR() : PciDevice
• isBareMetal() : RiscvSystem
• isBarrier() : GPUDynInst , GPUStaticInst , Minor::LSQ::BarrierDataRequest , Minor::LSQ::LSQRequest
• isBenign() : X86ISA::X86FaultBase
• isBlockCached() : Packet
• isBlocked() : AbstractController , BaseCache::CacheSlavePort , BaseCache
• isBlockInvalid() : CacheMemory
• isBlockNotBusy() : CacheMemory
• isBranch() : GPUDynInst , GPUStaticInst , Minor::BranchData
• isBroadcast() : NetDest , Set
• isBSYSet() : IdeDisk
• isBubble() : Minor::BranchData , Minor::BubbleIF , Minor::BubbleTraitsAdaptor< ElemType > , Minor::BubbleTraitsPtrAdaptor< PtrType, ElemType > , Minor::ForwardInstData , Minor::ForwardLineData , Minor::MinorDynInst , Minor::NoBubbleTraits< ElemType > , Minor::QueuedInst
• isBusy() : DistEtherLink::LocalIface , EtherInt , EtherLink::Interface , SimpleMemory , SMMUCommandExecProcess
• isCacheBlockHit() : LSQ< Impl >::LSQRequest , LSQ< Impl >::SingleDataRequest , LSQ< Impl >::SplitDataRequest
• isCacheClean() : Request
• isCachedAbove() : Cache
• isCacheInvalidate() : Request
• isCacheMaintenance() : Request
• isCacheMiss() : BasePrefetcher::PrefetchInfo
• isCall() : BaseDynInst< Impl > , StaticInst
• isCC() : StaticInst
• isCCPhysReg() : PhysRegId
• isCCReg() : RegId
• isClass() : Net::IpOpt
• isClean() : MemCmd
• IsClean : MemCmd
• isClean() : Packet
• isCleanEviction() : Packet
• isCleaning() : MSHR
• isClockSet() : I2CBus
• isCommitted() : BaseDynInst< Impl >
• isComp() : ElasticTrace::TraceInfo , TraceCPU::ElasticDataGen::GraphNode
• isComplete() : ArmISA::Stage2LookUp , LSQ< Impl >::LSQRequest , LSQ< Impl >::LSQSenderState , MemChecker::WriteCluster , Minor::Fetch1::FetchRequest , Minor::LSQ::LSQRequest
• isCompleted() : BaseDynInst< Impl >
• isCompressed() : CompressionBlk , SuperBlk
• isCondCtrl() : BaseDynInst< Impl > , StaticInst
• isCondDelaySlot() : BaseDynInst< Impl > , StaticInst
• isCondRegister() : BaseOperand , GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T >
• isCondSwap() : Request
• isConfReported() : AbstractMemory
• isConnected() : Port
• isControl() : BaseDynInst< Impl > , StaticInst
• isCopied() : Net::IpOpt
• isCpuDrained() : AtomicSimpleCPU , FullO3CPU< Impl > , TimingSimpleCPU
• isCPUSequencer() : RubyPort
• isDataPrefetch() : BaseDynInst< Impl > , StaticInst
• isDeadlockEventScheduled() : DMASequencer , GPUCoalescer , RubyPort , RubyPortProxy , Sequencer
• isDelayed() : LSQ< Impl >::LSQRequest
• isDelayedCommit() : BaseDynInst< Impl > , StaticInst
• isDenormalized() : PowerISA::FloatOp
• isDestination() : CoherentXBar
• isDeviceScope() : GPUDynInst , GPUStaticInst , Request
• isDEVSelect() : IdeDisk
• isDirectCtrl() : BaseDynInst< Impl > , StaticInst
• isDirty() : BaseCache , CacheBlk
• isDiscardable() : Minor::Fetch1::FetchRequest
• isDiskSelected() : IdeController
• isDone() : ComputeUnit
• isDoneSquashing() : ROB< Impl >
• isDrained() : DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DrainManager , FUPool , InstructionQueue< Impl > , LSQ< Impl > , MemDepUnit< MemDepPred, Impl > , Minor::Decode , Minor::Execute , Minor::Fetch1 , Minor::Fetch2 , Minor::LSQ , Minor::LSQ::StoreBuffer , Minor::Pipeline
• isDraining() : FullO3CPU< Impl >
• isDstOperand() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• isEL3OrMon() : Gicv3CPUInterface
• isElement() : NetDest , Set
• isEmpty() : flitBuffer , LSQ< Impl > , LSQUnit< Impl > , MessageBuffer , NetDest , Queue< Entry > , ROB< Impl > , Set , WriteMask
• isEnabled() : DVFSHandler
• isEnd() : I2CBus
• isEntry() : AlphaISA::StackTrace , ArmISA::StackTrace , BasicBlock , MipsISA::StackTrace , PowerISA::StackTrace , RiscvISA::StackTrace , X86ISA::StackTrace
• isEOISplitMode() : Gicv3CPUInterface
• isEqual() : NetDest , Set
• IsError : MemCmd
• isError() : MemCmd , Packet
• ISET_A64 : Trace::TarmacBaseRecord
• ISET_ARM : Trace::TarmacBaseRecord
• ISET_THUMB : Trace::TarmacBaseRecord
• ISET_UNSUPPORTED : Trace::TarmacBaseRecord
• isetstate : Trace::TarmacBaseRecord::InstEntry
• ISetState : Trace::TarmacBaseRecord
• isetstate : Trace::TarmacBaseRecord::RegEntry
• iSetStateToStr() : Trace::TarmacParserRecord
• isEviction() : MemCmd
• IsEviction : MemCmd
• isEviction() : Packet
• isExecComplete() : TraceCPU::ElasticDataGen
• isExecuted() : BaseDynInst< Impl >
• isExit() : BasicBlock
• isExitEvent() : Event
• IsExitEvent : EventBase
• isExpressSnoop() : Packet
• isFault() : Minor::ForwardLineData , Minor::MinorDynInst
• isFaultModelEnabled() : GarnetNetwork
• isFetch : ArmISA::TableWalker::WalkerState
• isFile() : OutputDirectory
• isFill : BasePrefetcher::PrefetchListener
• isFiltered() : ArmISA::PMU::CounterState , ArmISA::PMU
• isFiq() : GicV2
• isFirstMicroop() : BaseDynInst< Impl > , StaticInst
• isFixedMapping() : PhysRegId
• isFlagSet() : Event
• isFlat() : GPUDynInst , GPUStaticInst
• isFloating() : BaseDynInst< Impl > , StaticInst
• isFloatPhysReg() : PhysRegId
• isFloatReg() : RegId
• isFlush() : MemCmd
• IsFlush : MemCmd
• isFlush() : Packet
• isForward : MSHR
• isFull() : flitBuffer , InstructionQueue< Impl > , LSQ< Impl > , LSQUnit< Impl > , Queue< Entry > , ROB< Impl > , WriteMask
• isGlbMem() : ComputeUnit
• isGloballyCoherent() : GPUDynInst , GPUStaticInst
• isGlobalMem() : GPUDynInst , GPUStaticInst
• isGlobalSeg() : GPUDynInst , GPUStaticInst
• isGlobalSegment() : Request
• isGmInstruction() : Wavefront
• isGMLdRespFIFOWrRdy() : GlobalMemPipeline
• isGMReqFIFOWrRdy() : GlobalMemPipeline
• isGMStRespFIFOWrRdy() : GlobalMemPipeline
• isGroup0() : GicV2
• isGroupSeg() : GPUDynInst , GPUStaticInst
• isGroupSegment() : Request
• isHeadReady() : ROB< Impl >
• isHighConfidence() : MPP_TAGE , TAGEBase
• IsHWPrefetch : MemCmd
• isHWPrefetch() : MemCmd
• isHyp : ArmISA::TableWalker::WalkerState , ArmISA::TLB , ArmISA::TlbEntry
• isHyperPriv() : SparcISA::ISA
• isIENSet() : IdeDisk
• isInAddrMap() : AbstractMemory
• isInbetweenInsts() : Minor::Execute
• isIncoming() : VirtDescriptor
• isIndirectCtrl() : BaseDynInst< Impl > , StaticInst
• isInfinity() : PowerISA::FloatOp
• isInIQ() : BaseDynInst< Impl >
• isInLSQ() : BaseDynInst< Impl >
• isInROB() : BaseDynInst< Impl >
• isInst() : Minor::MinorDynInst
• isInState() : OutVcState
• isInstDataCpuPort() : RubyTester
• isInstFetch() : Request
• isInstOnlyCpuPort() : RubyTester
• isInstPrefetch() : BaseDynInst< Impl > , StaticInst
• isInteger() : BaseDynInst< Impl > , StaticInst
• isInterrupt() : RiscvISA::RiscvFault
• isInterrupted() : Minor::Execute
• isIntPhysReg() : PhysRegId
• isInTranslation() : LSQ< Impl >::LSQRequest
• isIntReg() : RegId
• IsInvalidate : MemCmd
• isInvalidate() : MemCmd , Packet
• isInvariantReg() : ArmKvmCPU
• isInWriteQueue : DRAMCtrl
• isIprAccess() : BaseDynInst< Impl > , StaticInst
• isIssued() : BaseDynInst< Impl >
• isKernArgSeg() : GPUDynInst , GPUStaticInst
• isKernargSegment() : Request
• isKernel() : Request
• isKvmMap() : AbstractMemory
• isLargeBAR() : PciDevice
• isLastMicroop() : BaseDynInst< Impl > , StaticInst
• isLastOpInInst() : Minor::MinorDynInst
• isLeaf() : PageTableOps , V7LPageTableOps , V8PageTableOps16k , V8PageTableOps4k , V8PageTableOps64k
• isLeftNode : StackDistCalc::Node
• isLevelSensitive() : GicV2
• islistening() : ListenSocket , TCPIface
• IsLlsc : MemCmd
• isLLSC() : MemCmd , Packet , Request
• isLmInstruction() : Wavefront
• isLMReqFIFOWrRdy() : LocalMemPipeline
• isLMRespFIFOWrRdy() : LocalMemPipeline
• isLoad() : BaseDynInst< Impl > , ElasticTrace::TraceInfo , GPUDynInst , GPUStaticInst , LSQ< Impl >::LSQRequest
• IsLoad : LSQ< Impl >::LSQRequest
• isLoad : LSQ< Impl >::LSQSenderState , Minor::LSQ::LSQRequest , StaticInst , TraceCPU::ElasticDataGen::GraphNode
• isLocalMem() : GPUDynInst , GPUStaticInst
• isLocked() : AbstractCacheEntry , CacheMemory , PersistentTable
• isLockedRMW() : Request
• isMachineCheckFault() : MipsISA::MachineCheckFault
• isMacroop() : BaseDynInst< Impl > , StaticInst
• IsMainQueue : EventBase
• isManaged() : Event
• isMarked : StackDistCalc::Node
• isMasked() : Request
• isMaskedWrite() : Packet
• isMaster : CxxConfigDirectoryEntry::PortDesc , DistIface
• isMemAccessRequired() : LSQ< Impl >::LSQRequest
• isMemAddr() : PhysicalMemory , System
• isMemBarrier() : BaseDynInst< Impl > , StaticInst
• isMemFence() : GPUDynInst , GPUStaticInst
• isMemRef() : BaseDynInst< Impl > , GPUDynInst , GPUStaticInst , Minor::MinorDynInst , StaticInst
• isMerging : ArmISA::SvePartBrkOp , ArmISA::SveUnaryWideImmPredOp
• isMicroBranch() : BaseDynInst< Impl > , StaticInst
• isMicroop() : BaseDynInst< Impl > , StaticInst
• isMiscPhysReg() : PhysRegId
• isMiscReg() : RegId
• isMmappedIpr() : Request
• isMMUFault() : ArmISA::AbortFault< T >
• isNan() : PowerISA::FloatOp
• isNegative() : PowerISA::FloatOp
• isNoCostInst() : Minor::MinorDynInst
• isNonPriv() : SparcISA::ISA
• isNonSpeculative() : BaseDynInst< Impl > , StaticInst
• isNoOrder() : GPUDynInst , GPUStaticInst
• isNop() : BaseDynInst< Impl > , GPUDynInst , GPUStaticInst , StaticInst
• isNormalized() : PowerISA::FloatOp
• isNoScope() : GPUDynInst , GPUStaticInst
• isNotSPI() : Gicv3Distributor
• isNull() : AbstractMemory
• isNumber() : Net::IpOpt
• isOldestInstALU() : Wavefront
• isOldestInstBarrier() : Wavefront
• isOldestInstFlatMem() : Wavefront
• isOldestInstGMem() : Wavefront
• isOldestInstLMem() : Wavefront
• isOldestInstPrivMem() : Wavefront
• isopt() : Net::TcpOpt
• isOutgoing() : VirtDescriptor
• isOverlap() : WriteMask
• isParallel : BloomFilter::MultiBitSel
• isPartialFault() : LSQ< Impl >::LSQRequest
• isPattern() : DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits > , DictionaryCompressor< T >::LocatedMaskedPattern< mask, location > , DictionaryCompressor< T >::MaskedPattern< mask > , DictionaryCompressor< T >::MaskedValuePattern< value, mask > , DictionaryCompressor< T >::RepeatedValuePattern< RepT > , DictionaryCompressor< T >::UncompressedPattern
• isPendingLPI() : Gicv3Redistributor
• isPendingModified() : MSHR
• isPhysMemAddress() : RubyPort::MemSlavePort
• isPinned() : PhysRegId
• isPinnedRegsRenamed() : BaseDynInst< Impl >
• isPinnedRegsSquashDone() : BaseDynInst< Impl >
• isPinnedRegsWritten() : BaseDynInst< Impl >
• isPipelined() : FuncUnit , FUPool
• isPipeThrough() : Gem5SystemC::Gem5Extension
• isPopable() : Minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits >
• isPred() : InstResult
• isPrefetch() : MemCmd , Request , SMMUTranslRequest , StaticInst , WholeTranslationState
• isPrefetchEx() : Request
• isPresent() : DirectoryMemory , TBETable< ENTRY >
• isPrint() : MemCmd
• IsPrint : MemCmd
• isPrint() : Packet
• isPriv : ArmISA::TLB , Request , SparcISA::ISA
• isPrivateSeg() : GPUDynInst , GPUStaticInst
• isPrivateSegment() : Request
• isPseudoOp() : HsailISA::Call
• isPTWalk() : Request
• isQnan() : PowerISA::FloatOp
• isQueueEmpty() : DRAMCtrl::Rank
• isQuiesce() : BaseDynInst< Impl > , StaticInst
• isr : dp_regs
• ISR : X86ISA::I8259
• isRead() : DRAMCtrl::DRAMPacket , DramGen
• IsRead : MemCmd
• isRead() : MemCmd , Packet
• isReadable() : CacheBlk
• isReadConflict() : VectorRegisterFile
• isReadOnly : BaseCache
• isReadOnlySeg() : GPUDynInst , GPUStaticInst
• isReadonlySegment() : Request
• isReady() : flitBuffer , InputUnit , MessageBuffer , NetworkLink , TimerTable , VirtualChannel , WireBuffer
• isReadySrcRegIdx() : BaseDynInst< Impl >
• isref : ThermalNode
• isReferenced() : IniFile::Entry , IniFile::Section
• isRelaxedOrder() : GPUDynInst , GPUStaticInst
• isRelease() : GPUDynInst , GPUStaticInst , Request
• isReleased() : LSQ< Impl >::LSQRequest
• isRenameable() : RegId
• isRequest() : MemCmd
• IsRequest : MemCmd
• isRequest() : Packet
• isReset() : MSHR::TargetList
• isResponse() : MemCmd
• IsResponse : MemCmd
• isResponse() : Packet
• isResultReady() : BaseDynInst< Impl >
• isRetrying() : X86ISA::Walker::WalkerState
• isRetryResp() : LdsState
• isReturn() : BaseDynInst< Impl > , GPUDynInst , GPUStaticInst , StaticInst
• ISRV : X86ISA::Interrupts
• iss() : ArmISA::AbortFault< T > , ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , ArmISA::DataAbort , ArmISA::SecureMonitorCall , ArmISA::SupervisorCall , ArmISA::SupervisorTrap , ArmISA::UndefinedInstruction , AUXU , ecoff_sym , McrMrcMiscInst
• isSaturated() : SatCounter
• issBase : ecoff_fdr
• isScalar() : GPUDynInst , GPUStaticInst , InstResult
• isScalarRegister() : BaseOperand , GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T >
• isScoped() : Request
• isSecure : ArmISA::TableWalker::WalkerState , ArmISA::TLB , BasePrefetcher::PrefetchInfo , CacheBlk , Packet , QueueEntry , Request , SectorBlk , StridePrefetcher::StrideEntry , TaggedEntry
• isSecureBelowEL3() : Gicv3CPUInterface
• isSel : ArmISA::SvePredLogicalOp
• isSent() : LSQ< Impl >::LSQRequest
• isSerializeAfter() : BaseDynInst< Impl > , StaticInst
• isSerializeBefore() : BaseDynInst< Impl > , StaticInst
• isSerializeHandled() : BaseDynInst< Impl >
• isSerializing() : BaseDynInst< Impl > , StaticInst
• isSet() : BloomFilter::Base , BloomFilter::Multi , Flags< T > , TimerTable
• issExtMax : ecoff_symhdr
• isShrMem() : ComputeUnit
• isSimdDone() : ComputeUnit
• isSimObject : CxxConfigDirectoryEntry::ParamDesc
• issMax : ecoff_symhdr
• isSnan() : PowerISA::FloatOp
• isSnooping() : AddrMapper , AddrMapper::MapperMasterPort , AtomicSimpleCPU::AtomicCPUDPort , BaseCache::CacheMasterPort , CoherentXBar::CoherentXBarMasterPort , CommMonitor , CommMonitor::MonitorMasterPort , LSQ< Impl >::DcachePort , MasterPort , MemCheckerMonitor , MemCheckerMonitor::MonitorMasterPort , MemDelay::MasterPort , Minor::LSQ::DcachePort , SlavePort , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort
• isSoft() : X86ISA::SoftwareInterrupt , X86ISA::X86FaultBase
• isSpecialOp() : GPUDynInst , GPUStaticInst
• isSpeculativeUpdateEnabled() : TAGEBase
• isSpillSeg() : GPUDynInst , GPUStaticInst
• isSpillSegment() : Request
• isSplit() : LSQ< Impl >::LSQRequest
• IsSplit : LSQ< Impl >::LSQRequest
• isSplit : LSQ< Impl >::LSQSenderState , WholeTranslationState
• isSquashAfter() : BaseDynInst< Impl > , StaticInst
• isSquashed() : BaseDynInst< Impl > , TimingSimpleCPU
• isSquashedInIQ() : BaseDynInst< Impl >
• isSquashedInLSQ() : BaseDynInst< Impl >
• isSquashedInROB() : BaseDynInst< Impl >
• issRaw : ArmISA::ArmFault
• isSrcOperand() : GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst
• isStage2() : ArmISA::AbortFault< T > , ArmISA::ArmFault , ArmISA::TableWalker , ArmISA::TLB
• isStalled() : ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , LSQ< Impl > , LSQUnit< Impl >
• isStallMapEmpty() : MessageBuffer
• isStart() : I2CBus
• isStore() : BaseDynInst< Impl > , ElasticTrace::TraceInfo , GPUDynInst , GPUStaticInst , StaticInst , TraceCPU::ElasticDataGen::GraphNode
• isStoreBlocked : LSQUnit< Impl >
• isStoreConditional() : BaseDynInst< Impl > , StaticInst
• isStreamChange() : Minor::BranchData
• IsStrictlyOrdered : BaseDynInst< Impl >
• isStrictlyOrdered() : Request , TraceCPU::ElasticDataGen::GraphNode , WholeTranslationState
• isSubset() : AddrRange , NetDest , Set
• issue() : MemDepUnit< MemDepPred, Impl > , Minor::Execute
• issue_time : GPUCoalescerRequest , SequencerRequest
• Issued : BaseDynInst< Impl >
• issued() : StoreSet
• issuedMemBarrierInst() : Minor::LSQ
• issuedPrefetches : BasePrefetcher
• issuedToMemory : Minor::LSQ::LSQRequest
• issuedTranslationsTable : TLBCoalescer
• issueEvent : GPUCoalescer
• issueLat : MinorFU
• issueLimit : Minor::Execute
• issueNext() : DMASequencer
• issueNextPrefetch() : Prefetcher
• issuePeriod : ComputeUnit
• issuePipelinedIfetch : DefaultFetch< Impl >
• issuePrefetch() : SMMUTranslationProcess
• issuePrefetchRequests : BOPPrefetcher
• issuePriority : Minor::Execute
• issueRate : InstructionQueue< Impl >
• issueRequest() : GlobalMemPipeline , GPUCoalescer , Sequencer
• IssueStruct : DefaultIEW< Impl > , InstructionQueue< Impl > , LSQUnit< Impl > , SimpleCPUPolicy< Impl >
• issueTime : X86ISA::GpuTLB::TranslationState
• issueTLBLookup() : X86ISA::GpuTLB
• issueToExecQueue : DefaultIEW< Impl >
• issueToExecuteDelay : DefaultIEW< Impl >
• issueToExecuteQueue : InstructionQueue< Impl >
• issueTranslation() : X86ISA::GpuTLB
• issueWidth : DefaultIEW< Impl >
• isSuperset() : NetDest , Set
• isSwap() : Request
• isSwitch : DistIface , TCPIface
• isSWPrefetch() : MemCmd
• IsSWPrefetch : MemCmd
• isSyscall() : BaseDynInst< Impl > , StaticInst
• isSystemCoherent() : GPUDynInst , GPUStaticInst
• isSystemScope() : GPUDynInst , GPUStaticInst , Request
• isTagPresent() : CacheMemory , PerfectCacheMemory< ENTRY >
• istatus : ArchTimer
• isTcp : IGbE::TxDescCache
• isTempSerializeAfter() : BaseDynInst< Impl >
• isTempSerializeBefore() : BaseDynInst< Impl >
• isThreadExiting() : FullO3CPU< Impl >
• isThreadSync() : BaseDynInst< Impl > , StaticInst
• isTiming() : X86ISA::Walker::WalkerState
• isTimingMode : DRAMCtrl , System
• isToPOC() : Request
• isToPOU() : Request
• isTraceComplete() : TraceCPU::FixedRetryGen
• isTranslationBlocked() : LSQ< Impl >::LSQRequest
• isTranslationComplete() : LSQ< Impl >::LSQRequest
• isTranslationDelayed() : BaseDynInst< Impl > , Minor::LSQ::LSQRequest
• isTTY() : ArmSemihosting::File , ArmSemihosting::FileBase
• isTtyReq() : AlphaLinux , FreeBSD , Linux , MipsLinux , PowerLinux , SparcLinux
• isUncacheable : ArmISA::TableWalker::WalkerState , QueueEntry , Request
• isUncondCtrl() : BaseDynInst< Impl > , StaticInst
• isUnconditional() : MultiperspectivePerceptron::MPPBranchInfo
• isUnconditionalJump() : GPUDynInst , GPUStaticInst
• isUnmapped() : EmulationPageTable
• isUnverifiable() : BaseDynInst< Impl > , StaticInst
• isUnwinding() : sc_gem5::Process
• IsUpgrade : MemCmd
• isUpgrade() : MemCmd , Packet
• isv : ArmISA::DataAbort
• isValid() : CacheBlk , GPUStaticInst , HsailISA::HsailGPUStaticInst , InstResult , KernelLaunchStaticInst , PageTableOps , SectorBlk , TaggedEntry , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement , V7LPageTableOps , V8PageTableOps16k , V8PageTableOps4k , V8PageTableOps64k
• isValidCounter() : ArmISA::PMU
• isValidDelta() : DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >
• isValidIdx() : CircularQueue< T >
• isVecAlu() : ComputeUnit
• isVecElem() : InstResult , RegId
• isVecPredPhysReg() : PhysRegId
• isVecPredReg() : RegId
• isVecReg() : RegId
• isVector() : BaseDynInst< Impl > , CxxConfigDirectoryEntry::ParamDesc , CxxConfigDirectoryEntry::PortDesc , InstResult , StaticInst
• isVectorPhysElem() : PhysRegId
• isVectorPhysReg() : PhysRegId
• isVectorRegister() : BaseOperand , GPUDynInst , GPUStaticInst , HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::BrInstBase< TargetType > , HsailISA::BrnInstBase< TargetType > , HsailISA::Call , HsailISA::CbrInstBase< TargetType > , HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > , HsailISA::LdaInstBase< DestOperandType, AddrOperandType > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > , HsailISA::SpecialInst1SrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcBase< DestOperandType > , HsailISA::SpecialInstNoSrcNoDest , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > , HsailISA::Stub , HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > , HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > , KernelLaunchStaticInst , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T >
• isVlan() : Net::EthHdr
• isVNetOrdered() : GarnetNetwork , SimpleNetwork
• isWaitcnt() : GPUDynInst , GPUStaticInst
• isWavefrontScope() : GPUDynInst , GPUStaticInst , Request
• isWFxTrapping() : ArmISA::ArmStaticInst
• isWholeLineWrite() : MSHR , MSHR::TargetList , Packet
• isWorkgroupScope() : GPUDynInst , GPUStaticInst , Request
• isWorkitemScope() : GPUDynInst , GPUStaticInst
• isWritable() : CacheBlk , PageTableOps , V7LPageTableOps , V8PageTableOps16k , V8PageTableOps4k , V8PageTableOps64k
• isWrite : ArmISA::TableWalker::WalkerState , BasePrefetcher::PrefetchInfo , DRAMCtrl::DRAMPacket , MemCmd
• IsWrite : MemCmd
• isWrite() : Packet , SMMUTranslRequest
• isWriteback() : MemCmd , Packet
• isWriteBarrier() : BaseDynInst< Impl > , StaticInst
• isWriteConflict() : VectorRegisterFile
• isym : AUXU , pdr
• isymBase : ecoff_fdr
• isymMax : ecoff_symhdr
• isZero() : PowerISA::FloatOp
• iszero() : sc_dt::sc_signed , sc_dt::sc_unsigned
• isZeroReg() : RegId
• it : SnoopFilter::ReqLookupResult
• it_ : sc_core::sc_vector_iter< Element, AccessPolicy >
• itb : CheckerCPU , FullO3CPU< Impl > , SimpleThread
• ItbAcvFault() : AlphaISA::ItbAcvFault
• ItbFault() : AlphaISA::ItbFault
• itBits : ArmISA::Decoder
• ItbPageFault() : AlphaISA::ItbPageFault
• ITBWaitResponse : BaseSimpleCPU
• item : std::deque< T > , std::list< T > , std::vector< T >
• item1 : std::pair< X, Y >
• item2 : std::pair< X, Y >
• items : DecodeCache::AddrMap< Value >::CachePage
• iterator : AddrRangeMap< V, max_cache_size > , AssociativeSet< Entry > , CircularQueue< T >::iterator
• Iterator : MSHR
• iterator : PacketFifo , PCEventQueue , QueuedPrefetcher , sc_core::sc_attr_cltn , sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , SimpleRenameMap , SparcISA::TlbMap
• Iterator : WriteQueueEntry
• iterator_category : CircularQueue< T >::iterator
• ITickEvent() : TimingSimpleCPU::IcachePort::ITickEvent
• itint : TsunamiCChip
• ITLBIALL() : ArmISA::ITLBIALL
• ITLBIASID() : ArmISA::ITLBIASID
• ITLBIMVA() : ArmISA::ITLBIMVA
• ITLBPort() : ComputeUnit::ITLBPort
• ItlbWait : DefaultFetch< Impl >
• itLines : GicV2 , Gicv3Distributor
• itr : iGbReg::Regs
• its : Gicv3 , Gicv3Its::DataPort , ItsProcess
• ItsCommand() : ItsCommand
• itsControl : Gicv3Its
• itsNumber : Gicv3Its
• ItsProcess() : ItsProcess
• ItsTables : Gicv3Its
• itsTranslate : Gicv3Its
• ItsTranslation() : ItsTranslation
• ittAddress : Gicv3Its
• ITTE : ItsProcess
• ittEntrySize : Gicv3Its
• ittRange : Gicv3Its
• ittReadRead : CommMonitor::MonitorStats
• ittReqReq : CommMonitor::MonitorStats
• ittWriteWrite : CommMonitor::MonitorStats
• itype_e : Wavefront
• iwl() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_fxtype_params , sc_dt::scfx_params