smmu_v3.hh

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/*
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#ifndef __DEV_ARM_SMMU_V3_HH__
#define __DEV_ARM_SMMU_V3_HH__

#include <list>
#include <map>
#include <queue>
#include <string>
#include <vector>

#include "base/statistics.hh"
#include "dev/arm/smmu_v3_caches.hh"
#include "dev/arm/smmu_v3_cmdexec.hh"
#include "dev/arm/smmu_v3_defs.hh"
#include "dev/arm/smmu_v3_events.hh"
#include "dev/arm/smmu_v3_ports.hh"
#include "dev/arm/smmu_v3_proc.hh"
#include "dev/arm/smmu_v3_ptops.hh"
#include "dev/arm/smmu_v3_slaveifc.hh"
#include "mem/packet.hh"
#include "params/SMMUv3.hh"
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"

class SMMUTranslationProcess;

class SMMUv3 : public ClockedObject
{
  protected:

    friend class SMMUProcess;
    friend class SMMUTranslationProcess;
    friend class SMMUCommandExecProcess;
    friend class SMMUv3SlaveInterface;

    const System &system;
    const MasterID masterId;

    SMMUMasterPort    masterPort;
    SMMUMasterTableWalkPort masterTableWalkPort;
    SMMUControlPort   controlPort;

    ARMArchTLB  tlb;
    ConfigCache configCache;
    IPACache    ipaCache;
    WalkCache   walkCache;

    const bool tlbEnable;
    const bool configCacheEnable;
    const bool ipaCacheEnable;
    const bool walkCacheEnable;
    bool tableWalkPortEnable;

    const bool walkCacheNonfinalEnable;
    const unsigned walkCacheS1Levels;
    const unsigned walkCacheS2Levels;
    const unsigned masterPortWidth; // in bytes

    SMMUSemaphore tlbSem;
    SMMUSemaphore ifcSmmuSem;
    SMMUSemaphore smmuIfcSem;
    SMMUSemaphore configSem;
    SMMUSemaphore ipaSem;
    SMMUSemaphore walkSem;
    SMMUSemaphore masterPortSem;

    SMMUSemaphore transSem; // max N transactions in SMMU
    SMMUSemaphore ptwSem; // max N concurrent PTWs
    SMMUSemaphore cycleSem; // max 1 table walk per cycle

    // Timing parameters
    const Cycles tlbLat;
    const Cycles ifcSmmuLat;
    const Cycles smmuIfcLat;
    const Cycles configLat;
    const Cycles ipaLat;
    const Cycles walkLat;

    // Stats
    Stats::Scalar steL1Fetches;
    Stats::Scalar steFetches;
    Stats::Scalar cdL1Fetches;
    Stats::Scalar cdFetches;
    Stats::Distribution translationTimeDist;
    Stats::Distribution ptwTimeDist;

    std::vector<SMMUv3SlaveInterface *> slaveInterfaces;

    SMMUCommandExecProcess commandExecutor;

    const AddrRange regsMap;
    SMMURegs regs;

    bool inSecureBlock(uint32_t offs) const;

    std::queue<SMMUAction> packetsToRetry;
    std::queue<SMMUAction> packetsTableWalkToRetry;


    void scheduleSlaveRetries();

    SMMUAction runProcess(SMMUProcess *proc, PacketPtr pkt);
    SMMUAction runProcessAtomic(SMMUProcess *proc, PacketPtr pkt);
    SMMUAction runProcessTiming(SMMUProcess *proc, PacketPtr pkt);

    void processCommands();
    EventWrapper<SMMUv3, &SMMUv3::processCommands> processCommandsEvent;

    void processCommand(const SMMUCommand &cmd);

    const PageTableOps *getPageTableOps(uint8_t trans_granule);

  public:
    SMMUv3(SMMUv3Params *p);
    virtual ~SMMUv3() {}

    virtual void init() override;
    virtual void regStats() override;

    Tick slaveRecvAtomic(PacketPtr pkt, PortID id);
    bool slaveRecvTimingReq(PacketPtr pkt, PortID id);
    bool masterRecvTimingResp(PacketPtr pkt);
    void masterRecvReqRetry();

    bool masterTableWalkRecvTimingResp(PacketPtr pkt);
    void masterTableWalkRecvReqRetry();

    Tick readControl(PacketPtr pkt);
    Tick writeControl(PacketPtr pkt);

    DrainState drain() override;
    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;

    virtual Port &getPort(const std::string &name,
                          PortID id = InvalidPortID) override;
};

#endif /* __DEV_ARM_SMMU_V3_HH__ */