gem5  v20.1.0.0
process.cc
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40 
41 #include "arch/arm/process.hh"
42 
43 #include "arch/arm/isa_traits.hh"
44 #include "arch/arm/types.hh"
47 #include "base/logging.hh"
48 #include "cpu/thread_context.hh"
49 #include "debug/Stack.hh"
50 #include "mem/page_table.hh"
51 #include "params/Process.hh"
52 #include "sim/aux_vector.hh"
53 #include "sim/byteswap.hh"
54 #include "sim/process_impl.hh"
55 #include "sim/syscall_return.hh"
56 #include "sim/system.hh"
57 
58 using namespace std;
59 using namespace ArmISA;
60 
61 ArmProcess::ArmProcess(ProcessParams *params, ::Loader::ObjectFile *objFile,
62  ::Loader::Arch _arch)
63  : Process(params,
64  new EmulationPageTable(params->name, params->pid, PageBytes),
65  objFile),
66  arch(_arch)
67 {
68  fatal_if(params->useArchPT, "Arch page tables not implemented.");
69 }
70 
71 ArmProcess32::ArmProcess32(ProcessParams *params,
72  ::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
73  : ArmProcess(params, objFile, _arch)
74 {
75  Addr brk_point = roundUp(image.maxAddr(), PageBytes);
76  Addr stack_base = 0xbf000000L;
77  Addr max_stack_size = 8 * 1024 * 1024;
78  Addr next_thread_stack_base = stack_base - max_stack_size;
79  Addr mmap_end = 0x40000000L;
80 
81  memState = make_shared<MemState>(this, brk_point, stack_base,
82  max_stack_size, next_thread_stack_base,
83  mmap_end);
84 }
85 
87  ProcessParams *params, ::Loader::ObjectFile *objFile,
88  ::Loader::Arch _arch)
89  : ArmProcess(params, objFile, _arch)
90 {
91  Addr brk_point = roundUp(image.maxAddr(), PageBytes);
92  Addr stack_base = 0x7fffff0000L;
93  Addr max_stack_size = 8 * 1024 * 1024;
94  Addr next_thread_stack_base = stack_base - max_stack_size;
95  Addr mmap_end = 0x4000000000L;
96 
97  memState = make_shared<MemState>(this, brk_point, stack_base,
98  max_stack_size, next_thread_stack_base,
99  mmap_end);
100 }
101 
102 void
104 {
106  argsInit<uint32_t>(PageBytes, INTREG_SP);
107  for (auto id: contextIds) {
108  ThreadContext *tc = system->threads[id];
109  CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
110  // Enable the floating point coprocessors.
111  cpacr.cp10 = 0x3;
112  cpacr.cp11 = 0x3;
113  tc->setMiscReg(MISCREG_CPACR, cpacr);
114  // Generically enable floating point support.
115  FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
116  fpexc.en = 1;
117  tc->setMiscReg(MISCREG_FPEXC, fpexc);
118  }
119 }
120 
121 void
123 {
125  argsInit<uint64_t>(PageBytes, INTREG_SP0);
126  for (auto id: contextIds) {
127  ThreadContext *tc = system->threads[id];
128  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
129  cpsr.mode = MODE_EL0T;
130  tc->setMiscReg(MISCREG_CPSR, cpsr);
131  CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
132  // Enable the floating point coprocessors.
133  cpacr.cp10 = 0x3;
134  cpacr.cp11 = 0x3;
135  // Enable SVE.
136  cpacr.zen = 0x3;
137  tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
138  // Generically enable floating point support.
139  FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
140  fpexc.en = 1;
141  tc->setMiscReg(MISCREG_FPEXC, fpexc);
142  }
143 }
144 
145 uint32_t
147 {
148  enum ArmCpuFeature {
149  Arm_Swp = 1 << 0,
150  Arm_Half = 1 << 1,
151  Arm_Thumb = 1 << 2,
152  Arm_26Bit = 1 << 3,
153  Arm_FastMult = 1 << 4,
154  Arm_Fpa = 1 << 5,
155  Arm_Vfp = 1 << 6,
156  Arm_Edsp = 1 << 7,
157  Arm_Java = 1 << 8,
158  Arm_Iwmmxt = 1 << 9,
159  Arm_Crunch = 1 << 10,
160  Arm_ThumbEE = 1 << 11,
161  Arm_Neon = 1 << 12,
162  Arm_Vfpv3 = 1 << 13,
163  Arm_Vfpv3d16 = 1 << 14
164  };
165 
166  return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult |
167  Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon |
168  Arm_Vfpv3 | Arm_Vfpv3d16;
169 }
170 
171 uint32_t
173 {
174  // In order to know what these flags mean, please refer to Linux
175  // /Documentation/arm64/elf_hwcaps.txt text file.
176  enum ArmCpuFeature {
177  Arm_Fp = 1 << 0,
178  Arm_Asimd = 1 << 1,
179  Arm_Evtstrm = 1 << 2,
180  Arm_Aes = 1 << 3,
181  Arm_Pmull = 1 << 4,
182  Arm_Sha1 = 1 << 5,
183  Arm_Sha2 = 1 << 6,
184  Arm_Crc32 = 1 << 7,
185  Arm_Atomics = 1 << 8,
186  Arm_Fphp = 1 << 9,
187  Arm_Asimdhp = 1 << 10,
188  Arm_Cpuid = 1 << 11,
189  Arm_Asimdrdm = 1 << 12,
190  Arm_Jscvt = 1 << 13,
191  Arm_Fcma = 1 << 14,
192  Arm_Lrcpc = 1 << 15,
193  Arm_Dcpop = 1 << 16,
194  Arm_Sha3 = 1 << 17,
195  Arm_Sm3 = 1 << 18,
196  Arm_Sm4 = 1 << 19,
197  Arm_Asimddp = 1 << 20,
198  Arm_Sha512 = 1 << 21,
199  Arm_Sve = 1 << 22,
200  Arm_Asimdfhm = 1 << 23,
201  Arm_Dit = 1 << 24,
202  Arm_Uscat = 1 << 25,
203  Arm_Ilrcpc = 1 << 26,
204  Arm_Flagm = 1 << 27
205  };
206 
207  uint32_t hwcap = 0;
208 
210 
211  const AA64PFR0 pf_r0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
212 
213  hwcap |= (pf_r0.fp == 0) ? Arm_Fp : 0;
214  hwcap |= (pf_r0.fp == 1) ? Arm_Fphp | Arm_Fp : 0;
215  hwcap |= (pf_r0.advsimd == 0) ? Arm_Asimd : 0;
216  hwcap |= (pf_r0.advsimd == 1) ? Arm_Asimdhp | Arm_Asimd : 0;
217  hwcap |= (pf_r0.sve >= 1) ? Arm_Sve : 0;
218  hwcap |= (pf_r0.dit >= 1) ? Arm_Dit : 0;
219 
220  const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
221 
222  hwcap |= (isa_r0.aes >= 1) ? Arm_Aes : 0;
223  hwcap |= (isa_r0.aes >= 2) ? Arm_Pmull : 0;
224  hwcap |= (isa_r0.sha1 >= 1) ? Arm_Sha1 : 0;
225  hwcap |= (isa_r0.sha2 >= 1) ? Arm_Sha2 : 0;
226  hwcap |= (isa_r0.sha2 >= 2) ? Arm_Sha512 : 0;
227  hwcap |= (isa_r0.crc32 >= 1) ? Arm_Crc32 : 0;
228  hwcap |= (isa_r0.atomic >= 1) ? Arm_Atomics : 0;
229  hwcap |= (isa_r0.rdm >= 1) ? Arm_Asimdrdm : 0;
230  hwcap |= (isa_r0.sha3 >= 1) ? Arm_Sha3 : 0;
231  hwcap |= (isa_r0.sm3 >= 1) ? Arm_Sm3 : 0;
232  hwcap |= (isa_r0.sm4 >= 1) ? Arm_Sm4 : 0;
233  hwcap |= (isa_r0.dp >= 1) ? Arm_Asimddp : 0;
234  hwcap |= (isa_r0.fhm >= 1) ? Arm_Asimdfhm : 0;
235  hwcap |= (isa_r0.ts >= 1) ? Arm_Flagm : 0;
236 
237  const AA64ISAR1 isa_r1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
238 
239  hwcap |= (isa_r1.dpb >= 1) ? Arm_Dcpop : 0;
240  hwcap |= (isa_r1.jscvt >= 1) ? Arm_Jscvt : 0;
241  hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0;
242  hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0;
243  hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0;
244 
245  const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
246 
247  hwcap |= (mm_fr2.at >= 1) ? Arm_Uscat : 0;
248 
249  return hwcap;
250 }
251 
252 template <class IntType>
253 void
254 ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
255 {
256  int intSize = sizeof(IntType);
257 
259 
260  string filename;
261  if (argv.size() < 1)
262  filename = "";
263  else
264  filename = argv[0];
265 
266  //We want 16 byte alignment
267  uint64_t align = 16;
268 
269  //Setup the auxilliary vectors. These will already have endian conversion.
270  //Auxilliary vectors are loaded only for elf formatted executables.
271  auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
272  if (elfObject) {
273 
274  if (objFile->getOpSys() == ::Loader::Linux) {
275  IntType features = armHwcap<IntType>();
276 
277  //Bits which describe the system hardware capabilities
278  //XXX Figure out what these should be
279  auxv.emplace_back(M5_AT_HWCAP, features);
280  //Frequency at which times() increments
281  auxv.emplace_back(M5_AT_CLKTCK, 0x64);
282  //Whether to enable "secure mode" in the executable
283  auxv.emplace_back(M5_AT_SECURE, 0);
284  // Pointer to 16 bytes of random data
285  auxv.emplace_back(M5_AT_RANDOM, 0);
286  //The filename of the program
287  auxv.emplace_back(M5_AT_EXECFN, 0);
288  //The string "v71" -- ARM v7 architecture
289  auxv.emplace_back(M5_AT_PLATFORM, 0);
290  }
291 
292  //The system page size
293  auxv.emplace_back(M5_AT_PAGESZ, ArmISA::PageBytes);
294  // For statically linked executables, this is the virtual address of
295  // the program header tables if they appear in the executable image
296  auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
297  // This is the size of a program header entry from the elf file.
298  auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
299  // This is the number of program headers from the original elf file.
300  auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
301  // This is the base address of the ELF interpreter; it should be
302  // zero for static executables or contain the base address for
303  // dynamic executables.
304  auxv.emplace_back(M5_AT_BASE, getBias());
305  //XXX Figure out what this should be.
306  auxv.emplace_back(M5_AT_FLAGS, 0);
307  //The entry point to the program
308  auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
309  //Different user and group IDs
310  auxv.emplace_back(M5_AT_UID, uid());
311  auxv.emplace_back(M5_AT_EUID, euid());
312  auxv.emplace_back(M5_AT_GID, gid());
313  auxv.emplace_back(M5_AT_EGID, egid());
314  }
315 
316  //Figure out how big the initial stack nedes to be
317 
318  // A sentry NULL void pointer at the top of the stack.
319  int sentry_size = intSize;
320 
321  string platform = "v71";
322  int platform_size = platform.size() + 1;
323 
324  // Bytes for AT_RANDOM above, we'll just keep them 0
325  int aux_random_size = 16; // as per the specification
326 
327  // The aux vectors are put on the stack in two groups. The first group are
328  // the vectors that are generated as the elf is loaded. The second group
329  // are the ones that were computed ahead of time and include the platform
330  // string.
331  int aux_data_size = filename.size() + 1;
332 
333  int env_data_size = 0;
334  for (int i = 0; i < envp.size(); ++i) {
335  env_data_size += envp[i].size() + 1;
336  }
337  int arg_data_size = 0;
338  for (int i = 0; i < argv.size(); ++i) {
339  arg_data_size += argv[i].size() + 1;
340  }
341 
342  int info_block_size =
343  sentry_size + env_data_size + arg_data_size +
344  aux_data_size + platform_size + aux_random_size;
345 
346  //Each auxilliary vector is two 4 byte words
347  int aux_array_size = intSize * 2 * (auxv.size() + 1);
348 
349  int envp_array_size = intSize * (envp.size() + 1);
350  int argv_array_size = intSize * (argv.size() + 1);
351 
352  int argc_size = intSize;
353 
354  //Figure out the size of the contents of the actual initial frame
355  int frame_size =
356  info_block_size +
357  aux_array_size +
358  envp_array_size +
359  argv_array_size +
360  argc_size;
361 
362  //There needs to be padding after the auxiliary vector data so that the
363  //very bottom of the stack is aligned properly.
364  int partial_size = frame_size;
365  int aligned_partial_size = roundUp(partial_size, align);
366  int aux_padding = aligned_partial_size - partial_size;
367 
368  int space_needed = frame_size + aux_padding;
369 
370  memState->setStackMin(memState->getStackBase() - space_needed);
371  memState->setStackMin(roundDown(memState->getStackMin(), align));
372  memState->setStackSize(memState->getStackBase() - memState->getStackMin());
373 
374  // map memory
375  memState->mapRegion(roundDown(memState->getStackMin(), pageSize),
376  roundUp(memState->getStackSize(), pageSize), "stack");
377 
378  // map out initial stack contents
379  IntType sentry_base = memState->getStackBase() - sentry_size;
380  IntType aux_data_base = sentry_base - aux_data_size;
381  IntType env_data_base = aux_data_base - env_data_size;
382  IntType arg_data_base = env_data_base - arg_data_size;
383  IntType platform_base = arg_data_base - platform_size;
384  IntType aux_random_base = platform_base - aux_random_size;
385  IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
386  IntType envp_array_base = auxv_array_base - envp_array_size;
387  IntType argv_array_base = envp_array_base - argv_array_size;
388  IntType argc_base = argv_array_base - argc_size;
389 
390  DPRINTF(Stack, "The addresses of items on the initial stack:\n");
391  DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
392  DPRINTF(Stack, "0x%x - env data\n", env_data_base);
393  DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
394  DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
395  DPRINTF(Stack, "0x%x - platform base\n", platform_base);
396  DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
397  DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
398  DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
399  DPRINTF(Stack, "0x%x - argc \n", argc_base);
400  DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin());
401 
402  // write contents to stack
403 
404  // figure out argc
405  IntType argc = argv.size();
406  IntType guestArgc = htole(argc);
407 
408  //Write out the sentry void *
409  IntType sentry_NULL = 0;
410  initVirtMem->writeBlob(sentry_base, &sentry_NULL, sentry_size);
411 
412  //Fix up the aux vectors which point to other data
413  for (int i = auxv.size() - 1; i >= 0; i--) {
414  if (auxv[i].type == M5_AT_PLATFORM) {
415  auxv[i].val = platform_base;
416  initVirtMem->writeString(platform_base, platform.c_str());
417  } else if (auxv[i].type == M5_AT_EXECFN) {
418  auxv[i].val = aux_data_base;
419  initVirtMem->writeString(aux_data_base, filename.c_str());
420  } else if (auxv[i].type == M5_AT_RANDOM) {
421  auxv[i].val = aux_random_base;
422  // Just leave the value 0, we don't want randomness
423  }
424  }
425 
426  //Copy the aux stuff
427  Addr auxv_array_end = auxv_array_base;
428  for (const auto &aux: auxv) {
429  initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
430  auxv_array_end += sizeof(aux);
431  }
432  //Write out the terminating zeroed auxillary vector
433  const AuxVector<IntType> zero(0, 0);
434  initVirtMem->write(auxv_array_end, zero);
435  auxv_array_end += sizeof(zero);
436 
437  copyStringArray(envp, envp_array_base, env_data_base,
438  ByteOrder::little, *initVirtMem);
439  copyStringArray(argv, argv_array_base, arg_data_base,
440  ByteOrder::little, *initVirtMem);
441 
442  initVirtMem->writeBlob(argc_base, &guestArgc, intSize);
443 
445  //Set the stack pointer register
446  tc->setIntReg(spIndex, memState->getStackMin());
447  //A pointer to a function to run when the program exits. We'll set this
448  //to zero explicitly to make sure this isn't used.
449  tc->setIntReg(ArgumentReg0, 0);
450  //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
451  if (argv.size() > 0) {
452  tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
453  argv[argv.size() - 1].size() - 1);
454  } else {
455  tc->setIntReg(ArgumentReg1, 0);
456  }
457  if (envp.size() > 0) {
458  tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
459  envp[envp.size() - 1].size() - 1);
460  } else {
461  tc->setIntReg(ArgumentReg2, 0);
462  }
463 
464  PCState pc;
465  pc.thumb(arch == ::Loader::Thumb);
466  pc.nextThumb(pc.thumb());
467  pc.aarch64(arch == ::Loader::Arm64);
468  pc.nextAArch64(pc.aarch64());
469  pc.set(getStartPC() & ~mask(1));
470  tc->pcState(pc);
471 
472  //Align the "stackMin" to a page boundary.
473  memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
474 }
475 
477  0, 1, 2, 3, 4, 5, 6
478 };
479 
481  0, 1, 2, 3, 4, 5, 6
482 };
ArmProcess64::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:122
ArmISA::MISCREG_ID_AA64MMFR2_EL1
@ MISCREG_ID_AA64MMFR2_EL1
Definition: miscregs.hh:814
Loader::Linux
@ Linux
Definition: object_file.hh:62
roundDown
T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:150
X86ISA::L
Bitfield< 7, 0 > L
Definition: int.hh:57
ArmISA::MISCREG_ID_AA64ISAR1_EL1
@ MISCREG_ID_AA64ISAR1_EL1
Definition: miscregs.hh:560
system.hh
ArmISA::MODE_EL0T
@ MODE_EL0T
Definition: types.hh:629
Process::envp
std::vector< std::string > envp
Definition: process.hh:217
Loader::Thumb
@ Thumb
Definition: object_file.hh:53
Process::gid
uint64_t gid()
Definition: process.hh:82
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ArmISA::MISCREG_ID_AA64ISAR0_EL1
@ MISCREG_ID_AA64ISAR0_EL1
Definition: miscregs.hh:559
Process
Definition: process.hh:65
M5_AT_UID
@ M5_AT_UID
Definition: aux_vector.hh:69
htole
T htole(T value)
Definition: byteswap.hh:140
Process::argv
std::vector< std::string > argv
Definition: process.hh:216
type
uint8_t type
Definition: inet.hh:421
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
ArmISA::MISCREG_CPACR
@ MISCREG_CPACR
Definition: miscregs.hh:235
ArmISA::ArgumentReg2
const int ArgumentReg2
Definition: registers.hh:111
ArmISA::IntRegIndex
IntRegIndex
Definition: intregs.hh:51
M5_AT_PAGESZ
@ M5_AT_PAGESZ
Definition: aux_vector.hh:64
M5_AT_SECURE
@ M5_AT_SECURE
Definition: aux_vector.hh:76
ArmProcess64::armHwcapImpl
uint32_t armHwcapImpl() const override
AArch64 AT_HWCAP.
Definition: process.cc:172
M5_AT_PHENT
@ M5_AT_PHENT
Definition: aux_vector.hh:62
ArmProcess::arch
::Loader::Arch arch
Definition: process.hh:56
ArmISA::GuestByteOrder
const ByteOrder GuestByteOrder
Definition: isa_traits.hh:49
ArmProcess::argsInit
void argsInit(int pageSize, ArmISA::IntRegIndex spIndex)
Definition: process.cc:254
process_impl.hh
M5_AT_EUID
@ M5_AT_EUID
Definition: aux_vector.hh:70
std::vector
STL vector class.
Definition: stl.hh:37
Process::initVirtMem
std::unique_ptr< SETranslatingPortProxy > initVirtMem
Definition: process.hh:177
ArmISA::ArgumentReg1
const int ArgumentReg1
Definition: registers.hh:110
Process::egid
uint64_t egid()
Definition: process.hh:83
ArmISA
Definition: ccregs.hh:41
types.hh
ArmISA::INTREG_SP
@ INTREG_SP
Definition: intregs.hh:68
Loader::ElfObject
Definition: elf_object.hh:59
ArmProcess::ArmProcess
ArmProcess(ProcessParams *params, ::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
Definition: process.cc:61
Loader::MemoryImage::maxAddr
Addr maxAddr() const
Definition: memory_image.hh:131
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
ArmProcess32::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:103
M5_AT_ENTRY
@ M5_AT_ENTRY
Definition: aux_vector.hh:67
M5_AT_BASE
@ M5_AT_BASE
Definition: aux_vector.hh:65
ArmProcess64::SyscallABI::ArgumentRegs
static const std::vector< int > ArgumentRegs
Definition: process.hh:131
Loader::ObjectFile
Definition: object_file.hh:70
ArmProcess64::ArmProcess64
ArmProcess64(ProcessParams *params, ::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
Definition: process.cc:86
M5_AT_PHNUM
@ M5_AT_PHNUM
Definition: aux_vector.hh:63
elf_object.hh
AuxVector
Definition: aux_vector.hh:38
Loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:108
syscall_return.hh
ArmISA::MISCREG_ID_AA64PFR0_EL1
@ MISCREG_ID_AA64PFR0_EL1
Definition: miscregs.hh:553
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
M5_AT_PLATFORM
@ M5_AT_PLATFORM
Definition: aux_vector.hh:73
EmulationPageTable
Definition: page_table.hh:48
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ArmISA::ArgumentReg0
const int ArgumentReg0
Definition: registers.hh:109
M5_AT_FLAGS
@ M5_AT_FLAGS
Definition: aux_vector.hh:66
ArmProcess32::SyscallABI::ArgumentRegs
static const std::vector< int > ArgumentRegs
Definition: process.hh:88
ArmISA::INTREG_SP0
@ INTREG_SP0
Definition: intregs.hh:118
M5_AT_EXECFN
@ M5_AT_EXECFN
Definition: aux_vector.hh:80
Process::image
::Loader::MemoryImage image
Definition: process.hh:214
M5_AT_RANDOM
@ M5_AT_RANDOM
Definition: aux_vector.hh:78
ArmISA::MISCREG_FPEXC
@ MISCREG_FPEXC
Definition: miscregs.hh:71
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
Process::objFile
::Loader::ObjectFile * objFile
Definition: process.hh:213
Process::getBias
Addr getBias()
Definition: process.cc:468
SimObject::params
const Params * params() const
Definition: sim_object.hh:119
name
const std::string & name()
Definition: trace.cc:50
Process::contextIds
std::vector< ContextID > contextIds
Definition: process.hh:160
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
M5_AT_GID
@ M5_AT_GID
Definition: aux_vector.hh:71
System::threads
Threads threads
Definition: system.hh:309
ArmISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:52
Loader::Arch
Arch
Definition: object_file.hh:44
ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: miscregs.hh:57
aux_vector.hh
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:290
roundUp
T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:131
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
logging.hh
Loader::ObjectFile::getOpSys
OpSys getOpSys() const
Definition: object_file.hh:100
isa_traits.hh
Loader::Arm64
@ Arm64
Definition: object_file.hh:51
Process::euid
uint64_t euid()
Definition: process.hh:81
Process::getStartPC
Addr getStartPC()
Definition: process.cc:476
ArmProcess32::armHwcapImpl
uint32_t armHwcapImpl() const override
AArch32 AT_HWCAP.
Definition: process.cc:146
M5_AT_HWCAP
@ M5_AT_HWCAP
Definition: aux_vector.hh:74
Process::system
System * system
Definition: process.hh:163
Process::uid
uint64_t uid()
Definition: process.hh:80
ArmISA::MISCREG_CPACR_EL1
@ MISCREG_CPACR_EL1
Definition: miscregs.hh:574
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:219
M5_AT_CLKTCK
@ M5_AT_CLKTCK
Definition: aux_vector.hh:75
page_table.hh
ArmProcess32::ArmProcess32
ArmProcess32(ProcessParams *params, ::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
Definition: process.cc:71
process.hh
ArmProcess
Definition: process.hh:53
copyStringArray
void copyStringArray(std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
Definition: process_impl.hh:40
M5_AT_EGID
@ M5_AT_EGID
Definition: aux_vector.hh:72
object_file.hh
thread_context.hh
Process::memState
std::shared_ptr< MemState > memState
Definition: process.hh:279
ArmISA::mask
Bitfield< 28, 24 > mask
Definition: miscregs_types.hh:711
ArmISA::id
Bitfield< 33 > id
Definition: miscregs_types.hh:247
M5_AT_PHDR
@ M5_AT_PHDR
Definition: aux_vector.hh:61
byteswap.hh

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