gem5  v20.1.0.0
cache.hh
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40 
46 #ifndef __MEM_CACHE_CACHE_HH__
47 #define __MEM_CACHE_CACHE_HH__
48 
49 #include <cstdint>
50 #include <unordered_set>
51 
52 #include "base/types.hh"
53 #include "mem/cache/base.hh"
54 #include "mem/packet.hh"
55 
56 class CacheBlk;
57 struct CacheParams;
58 class MSHR;
59 
63 class Cache : public BaseCache
64 {
65  protected:
69  const bool doFastWrites;
70 
76  std::unordered_set<RequestPtr> outstandingSnoop;
77 
78  protected:
83 
84  bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
85  PacketList &writebacks) override;
86 
87  void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
88  Tick request_time) override;
89 
90  void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
91  Tick forward_time,
92  Tick request_time) override;
93 
94  void recvTimingReq(PacketPtr pkt) override;
95 
96  void doWritebacks(PacketList& writebacks, Tick forward_time) override;
97 
98  void doWritebacksAtomic(PacketList& writebacks) override;
99 
100  void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
101  CacheBlk *blk) override;
102 
103  void recvTimingSnoopReq(PacketPtr pkt) override;
104 
105  void recvTimingSnoopResp(PacketPtr pkt) override;
106 
108  PacketList &writebacks) override;
109 
110  Tick recvAtomic(PacketPtr pkt) override;
111 
112  Tick recvAtomicSnoop(PacketPtr pkt) override;
113 
114  void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
115  bool deferred_response = false,
116  bool pending_downgrade = false) override;
117 
118  void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
119  bool already_copied, bool pending_inval);
120 
133  uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
134  bool is_timing, bool is_deferred, bool pending_inval);
135 
136  M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
137 
145 
147  bool needs_writable,
148  bool is_whole_line_write) const override;
149 
154  bool isCachedAbove(PacketPtr pkt, bool is_timing = true);
155 
156  public:
158  Cache(const CacheParams *p);
159 
168  bool sendMSHRQueuePacket(MSHR* mshr) override;
169 };
170 
171 #endif // __MEM_CACHE_CACHE_HH__
Cache::outstandingSnoop
std::unordered_set< RequestPtr > outstandingSnoop
Store the outstanding requests that we are expecting snoop responses from so we can determine which s...
Definition: cache.hh:76
base.hh
Cache::doWritebacksAtomic
void doWritebacksAtomic(PacketList &writebacks) override
Send writebacks down the memory hierarchy in atomic mode.
Definition: cache.cc:227
Cache::evictBlock
M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override
Evict a cache block.
Definition: cache.cc:897
X86ISA::CacheParams
@ CacheParams
Definition: cpuid.cc:40
Cache::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt) override
Snoops bus transactions to maintain coherence.
Definition: cache.cc:1194
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
Cache::recvAtomic
Tick recvAtomic(PacketPtr pkt) override
Performs the access specified by the request.
Definition: cache.cc:650
Cache::handleTimingReqHit
void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) override
Definition: cache.cc:308
M5_NODISCARD
#define M5_NODISCARD
Definition: compiler.hh:86
packet.hh
Cache::isCachedAbove
bool isCachedAbove(PacketPtr pkt, bool is_timing=true)
Send up a snoop request and find cached copies.
Definition: cache.cc:1325
Cache::recvAtomicSnoop
Tick recvAtomicSnoop(PacketPtr pkt) override
Snoop for the provided request in the cache and return the estimated time taken.
Definition: cache.cc:1312
Cache::recvTimingSnoopResp
void recvTimingSnoopResp(PacketPtr pkt) override
Handle a snoop response.
Definition: cache.cc:262
Cache::recvTimingReq
void recvTimingReq(PacketPtr pkt) override
Performs the access specified by the request.
Definition: cache.cc:398
Cache::handleTimingReqMiss
void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time) override
Definition: cache.cc:319
Cache::cleanEvictBlk
PacketPtr cleanEvictBlk(CacheBlk *blk)
Create a CleanEvict request for the given block.
Definition: cache.cc:908
Cache::access
bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks) override
Does all the processing necessary to perform the provided request.
Definition: cache.cc:156
Cache::satisfyRequest
void satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool deferred_response=false, bool pending_downgrade=false) override
Perform any necessary updates to the block and perform any data exchange between the packet and the b...
Definition: cache.cc:73
BaseCache
A basic cache interface.
Definition: base.hh:89
Cache::sendMSHRQueuePacket
bool sendMSHRQueuePacket(MSHR *mshr) override
Take an MSHR, turn it into a suitable downstream packet, and send it out.
Definition: cache.cc:1353
Cache::promoteWholeLineWrites
void promoteWholeLineWrites(PacketPtr pkt)
Turn line-sized writes into WriteInvalidate transactions.
Definition: cache.cc:296
Cache::handleAtomicReqMiss
Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) override
Handle a request in atomic mode that missed in this cache.
Definition: cache.cc:558
Cache::handleSnoop
uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, bool is_deferred, bool pending_inval)
Perform an upward snoop if needed, and update the block state (possibly invalidating the block).
Definition: cache.cc:981
CacheBlk
A Basic Cache block.
Definition: cache_blk.hh:84
types.hh
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
Cache::doFastWrites
const bool doFastWrites
This cache should allocate a block on a line-sized write miss.
Definition: cache.hh:69
Cache::createMissPacket
PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, bool needs_writable, bool is_whole_line_write) const override
Create an appropriate downstream bus request packet.
Definition: cache.cc:472
Cache::doWritebacks
void doWritebacks(PacketList &writebacks, Tick forward_time) override
Insert writebacks into the write buffer.
Definition: cache.cc:185
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
std::list
STL list class.
Definition: stl.hh:51
Cache
A coherent cache that can be arranged in flexible topologies.
Definition: cache.hh:63
Cache::Cache
Cache(const CacheParams *p)
Instantiates a basic cache object.
Definition: cache.cc:66
Cache::doTimingSupplyResponse
void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, bool already_copied, bool pending_inval)
Definition: cache.cc:936
Cache::serviceMSHRTargets
void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) override
Service non-deferred MSHR targets using the received response.
Definition: cache.cc:681
MSHR
Miss Status and handling Register.
Definition: mshr.hh:69

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