cache.hh

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#ifndef __MEM_CACHE_CACHE_HH__
#define __MEM_CACHE_CACHE_HH__
 
#include <cstdint>
#include <unordered_set>
 
#include "base/types.hh"
#include "mem/cache/base.hh"
#include "mem/packet.hh"
 
class CacheBlk;
struct CacheParams;
class MSHR;
 
class Cache : public BaseCache
{
  protected:
    const bool doFastWrites;
 
    std::unordered_set<RequestPtr> outstandingSnoop;
 
  protected:
    void promoteWholeLineWrites(PacketPtr pkt);
 
    bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
                PacketList &writebacks) override;
 
    void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
                            Tick request_time) override;
 
    void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
                             Tick forward_time,
                             Tick request_time) override;
 
    void recvTimingReq(PacketPtr pkt) override;
 
    void doWritebacks(PacketList& writebacks, Tick forward_time) override;
 
    void doWritebacksAtomic(PacketList& writebacks) override;
 
    void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
                            CacheBlk *blk) override;
 
    void recvTimingSnoopReq(PacketPtr pkt) override;
 
    void recvTimingSnoopResp(PacketPtr pkt) override;
 
    Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
                               PacketList &writebacks) override;
 
    Tick recvAtomic(PacketPtr pkt) override;
 
    Tick recvAtomicSnoop(PacketPtr pkt) override;
 
    void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
                        bool deferred_response = false,
                        bool pending_downgrade = false) override;
 
    void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
                                bool already_copied, bool pending_inval);
 
    uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
                         bool is_timing, bool is_deferred, bool pending_inval);
 
    M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
 
    PacketPtr cleanEvictBlk(CacheBlk *blk);
 
    PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
                               bool needs_writable,
                               bool is_whole_line_write) const override;
 
    bool isCachedAbove(PacketPtr pkt, bool is_timing = true);
 
  public:
    Cache(const CacheParams *p);
 
    bool sendMSHRQueuePacket(MSHR* mshr) override;
};
 
#endif // __MEM_CACHE_CACHE_HH__