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46 #ifndef __MEM_CACHE_MSHR_HH__
47 #define __MEM_CACHE_MSHR_HH__
75 template<
typename Entry>
156 Source _source,
bool _markedPending,
bool alloc_on_fill)
264 void print(std::ostream &
os,
int verbosity,
265 const std::string &prefix)
const;
277 [](
bool i) { return i; });
355 void promoteIf(
const std::function<
bool (Target &)>& pred);
396 Tick when_ready,
Counter _order,
bool alloc_on_fill);
501 const std::string &prefix =
"")
const override;
508 std::string
print()
const;
515 #endif // __MEM_CACHE_MSHR_HH__
Iterator allocIter
Pointer to this MSHR on the allocated list.
bool trySatisfyFunctional(PacketPtr pkt)
TargetList deferredTargets
const Source source
Request from cpu, memory, or prefetcher?
void clearDownstreamPending()
bool matchBlockAddr(const Addr addr, const bool is_secure) const override
Check if entry corresponds to the one being looked for.
A queue entry is holding packets that will be serviced as soon as resources are available.
Addr blkSize
Size of the cache block.
bool needsWritable() const
The pending* and post* flags are only valid if inService is true.
int getNumTargets() const
Returns the current number of allocated targets.
void updateFlags(PacketPtr pkt, Target::Source source, bool alloc_on_fill)
Use the provided packet and the source to update the flags of this TargetList.
void markInService(bool pending_modified_resp)
bool hasTargets() const
Returns true if there are targets left.
uint64_t Tick
Tick count type.
void populateFlags()
Goes through the list of targets and uses them to populate the flags of this TargetList.
bool conflictAddr(const QueueEntry *entry) const override
Check if given entry's packets conflict with this' entries packets.
void replaceUpgrades()
Convert upgrades to the equivalent request if the cache line they refer to would have been invalid (U...
Iterator readyIter
Pointer to this MSHR on the ready list.
bool hasFromCache() const
Determine if there are non-deferred requests from other caches.
std::string print() const
A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overhea...
const bool allocOnFill
Should the response servicing this target list allocate in the cache?
void promoteWritable()
Promotes deferred targets that do not require writable.
TargetList targets
List of all requests that match the address.
std::list< MSHR * > List
A list of MSHRs.
TargetList extractServiceableTargets(PacketPtr pkt)
Extracts the subset of the targets that can be serviced given a received response.
bool trySatisfyFunctional(PacketPtr pkt)
void clearDownstreamPending()
void promoteIf(const std::function< bool(Target &)> &pred)
Promotes deferred targets that satisfy a predicate.
bool isPendingModified() const
bool markedPending
We use this flag to track whether we have cleared the downstreamPending flag for the MSHR of the cach...
bool postInvalidate
Did we snoop an invalidate while waiting for data?
int64_t Counter
Statistics counter type.
Target(PacketPtr _pkt, Tick _readyTime, Counter _order, Source _source, bool _markedPending, bool alloc_on_fill)
bool allocOnFill
Set when the response should allocate on fill.
bool promoteDeferredTargets()
List::iterator Iterator
MSHR list iterator.
bool handleSnoop(PacketPtr target, Counter order)
bool isWholeLineWrite() const
Check if this list contains writes that cover an entire cache line.
void popTarget()
Pop first target.
void add(PacketPtr pkt, Tick readyTime, Counter order, Target::Source source, bool markPending, bool alloc_on_fill)
Add the specified packet in the TargetList.
void updateWriteFlags(PacketPtr pkt)
Add the specified packet in the TargetList.
bool postDowngrade
Did we snoop a read while waiting for data?
Abstract base class for objects which support being printed to a stream for debugging.
void init(Addr blk_addr, Addr blk_size)
Reset state.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Tick readyTime
Tick when ready to issue.
Counter order
Order number assigned to disambiguate writes and misses.
bool hasFromCache
Determine whether there was at least one non-snooping target coming from another cache.
QueueEntry::Target * getTarget() override
Returns a reference to the first target.
bool downstreamPending
Flag set by downstream caches.
bool wasWholeLineWrite
Track if we sent this as a whole line write or not.
bool inService
True if the entry has been sent downstream.
void allocateTarget(PacketPtr target, Tick when, Counter order, bool alloc_on_fill)
Add a request to the list of targets.
bool hasPostDowngrade() const
bool sendPacket(BaseCache &cache) override
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
void deallocate()
Mark this MSHR as free.
void print(std::ostream &os, int verbosity, const std::string &prefix) const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
std::vector< char > writesBitmap
Track which bytes are written by requests in this target list.
A high-level queue interface, to be used by both the MSHR queue and the write buffer.
A queue entry base class, to be used by both the MSHRs and write-queue entries.
bool hasPostInvalidate() const
bool isWholeLineWrite() const
Check if this MSHR contains only compatible writes, and if they span the entire cache line.
bool isForward
True if the entry is just a simple forward from an upper level.
void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter _order, bool alloc_on_fill)
Allocate a miss to this MSHR.
void promoteReadable()
Promotes deferred targets that do not require writable.
bool pendingModified
Here we use one flag to track both if:
A Class for maintaining a list of pending and allocated memory requests.
bool canMergeWrites
Indicates whether we can merge incoming write requests.
MSHR()
A simple constructor.
Addr blkAddr
Address of the cache block for this list of targets.
bool isReset() const
Tests if the flags of this TargetList have their default values.
void delay(Tick delay_ticks)
Adds a delay relative to the current tick to the current MSHR.
Miss Status and handling Register.
Tick curTick()
The current simulated tick.
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