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55 #include "debug/Cache.hh"
56 #include "debug/CacheTags.hh"
57 #include "debug/CacheVerbose.hh"
58 #include "enums/Clusivity.hh"
64 #include "params/Cache.hh"
74 bool deferred_response,
bool pending_downgrade)
96 }
else if (blk->
isWritable() && !pending_downgrade &&
111 if (!deferred_response) {
160 if (pkt->
req->isUncacheable()) {
164 "Should never see a write in a read-only cache %s\n",
171 if (old_blk && old_blk->
isValid()) {
187 while (!writebacks.empty()) {
222 writebacks.pop_front();
229 while (!writebacks.empty()) {
252 writebacks.pop_front();
272 if (!forwardAsSnoop) {
279 DPRINTF(
Cache,
"Got prefetch response from above for addr "
303 DPRINTF(
Cache,
"packet promoted from Write to WriteLineReq\n");
313 assert(!pkt->
req->isUncacheable());
322 if (pkt->
req->isUncacheable()) {
327 assert(!blk || !blk->
isValid());
362 assert(pkt->
req->hasPaddr());
363 assert(!pkt->
req->isUncacheable());
373 RequestPtr req = std::make_shared<Request>(pkt->
req->getPaddr(),
375 pkt->
req->getFlags(),
376 pkt->
req->requestorId());
379 assert(
pf->matchAddr(pkt));
408 DPRINTF(
Cache,
"Cache above responding to %s: not responding\n",
474 bool is_whole_line_write)
const
479 bool blkValid = blk && blk->
isValid();
481 if (cpu_pkt->
req->isUncacheable() ||
496 const bool useUpgrades =
true;
498 if (is_whole_line_write) {
504 }
else if (blkValid && useUpgrades) {
507 assert(needsWritable);
537 if (cpu_pkt->
hasSharers() && !needsWritable) {
543 DPRINTF(
Cache,
"%s: passing hasSharers from %s to %s\n",
564 (pkt->
req->isUncacheable() && pkt->
isWrite())) {
570 assert(!(pkt->
req->isUncacheable() && pkt->
isWrite()) ||
581 bool is_forward = (bus_pkt ==
nullptr);
601 DPRINTF(
Cache,
"%s: Receive response: %s in state %i\n", __func__,
602 bus_pkt->
print(), old_state);
621 blk =
handleFill(bus_pkt, blk, writebacks, allocate);
623 is_invalidate =
false;
625 }
else if (bus_pkt->
isRead() ||
642 if (is_invalidate && blk && blk->
isValid()) {
657 assert(!pkt->
req->isCacheInvalidate());
658 DPRINTF(
Cache,
"Cache above responding to %s: not responding\n",
687 const bool is_error = pkt->
isError();
694 for (
auto &target: targets) {
695 Packet *tgt_pkt = target.pkt;
696 switch (target.source) {
698 Tick completion_time;
728 "read-only cache %s\n",
name());
762 int transfer_offset =
764 if (transfer_offset < 0) {
775 assert(!tgt_pkt->
req->isUncacheable());
780 completion_time - target.recvTime;
791 tgt_pkt->
req->setExtraData(0);
793 if (is_invalidate && blk && blk->
isValid()) {
872 pkt->
req->isCacheMaintenance() ||
878 panic(
"Illegal target->source enum %d\n", target.source);
937 bool already_copied,
bool pending_inval)
975 DPRINTF(CacheVerbose,
"%s: created response: %s tick: %lu\n", __func__,
976 pkt->
print(), forward_time);
982 bool is_deferred,
bool pending_inval)
984 DPRINTF(CacheVerbose,
"%s: for %s\n", __func__, pkt->
print());
986 assert(!(is_deferred && !is_timing));
988 assert(!(pending_inval && !is_deferred));
1001 "%s got an invalidating uncacheable snoop request %s",
1004 uint32_t snoop_delay = 0;
1015 Packet snoopPkt(pkt,
true,
true);
1053 bool respond =
false;
1054 bool blk_valid = blk && blk->
isValid();
1056 if (blk_valid && blk->
isDirty()) {
1057 DPRINTF(CacheVerbose,
"%s: packet (snoop) %s found block: %s\n",
1061 writebacks.push_back(wb_pkt);
1074 }
else if (!blk_valid) {
1075 DPRINTF(CacheVerbose,
"%s: snoop miss for %s\n", __func__,
1091 DPRINTF(
Cache,
"%s: snoop hit for %s, old state is %s\n", __func__,
1104 "a dirty block in a read-only cache %s\n",
name());
1112 DPRINTF(
Cache,
"Found addr %#llx in upper level cache for snoop %s "
1118 if (pkt->
isRead() && !invalidate) {
1120 assert(!needs_writable);
1128 if (!pkt->
req->isUncacheable())
1157 "%s is passing a Modified line through %s, "
1158 "but keeping the block",
name(), pkt->
print());
1177 if (!respond && is_deferred) {
1184 if (blk_valid && invalidate) {
1196 DPRINTF(CacheVerbose,
"%s: for %s\n", __func__, pkt->
print());
1220 DPRINTF(
Cache,
"Setting block cached for %s from lower cache on "
1221 "mshr hit\n", pkt->
print());
1229 DPRINTF(
Cache,
"Deferring snoop on in-service MSHR to blk %#llx (%s)."
1230 "mshrs: %s\n", blk_addr, is_secure ?
"s" :
"ns",
1234 warn(
"allocating bonus target for snoop");
1241 DPRINTF(
Cache,
"Snoop hit in writeback to addr %#llx (%s)\n",
1242 pkt->
getAddr(), is_secure ?
"s" :
"ns");
1258 DPRINTF(
Cache,
"%s: Squashing %s from lower cache on writequeue "
1259 "hit\n", __func__, pkt->
print());
1273 if (!pkt->
req->isUncacheable() && pkt->
isRead() && !invalidate) {
1282 if (have_writable) {
1303 uint32_t snoop_delay =
handleSnoop(pkt, blk,
true,
false,
false);
1320 uint32_t snoop_delay =
handleSnoop(pkt, blk,
false,
false,
false);
1335 Packet snoop_pkt(pkt,
true,
false);
1372 Packet snoop_pkt(tgt_pkt,
true,
false);
1399 bool pending_modified_resp = !snoop_pkt.
hasSharers();
1409 DPRINTF(
Cache,
"Block present, prefetch squashed by cache. "
1410 "Deallocating mshr target %#x.\n",
1431 CacheParams::create()
1434 assert(replacement_policy);
1436 return new Cache(
this);
std::unordered_set< RequestPtr > outstandingSnoop
Store the outstanding requests that we are expecting snoop responses from so we can determine which s...
bool isWritable() const
Checks the write permissions of this block.
void makeAtomicResponse()
void clearBlocked(BlockedCause cause)
Marks the cache as unblocked for the given cause.
WriteQueue writeBuffer
Write/writeback buffer.
void maintainClusivity(bool from_cache, CacheBlk *blk)
Maintain the clusivity of this cache by potentially invalidating a block.
bool isSWPrefetch() const
void markInService(MSHR *mshr, bool pending_modified_resp)
Mark a request as in service (sent downstream in the memory system), effectively making this MSHR the...
void makeTimingResponse()
void doWritebacksAtomic(PacketList &writebacks) override
Send writebacks down the memory hierarchy in atomic mode.
bool cacheResponding() const
Addr blkAddr
Block aligned address.
void print(std::ostream &os, int verbosity=0, const std::string &prefix="") const override
Prints the contents of this MSHR for debugging.
M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override
Evict a cache block.
A queue entry is holding packets that will be serviced as soon as resources are available.
void copyResponderFlags(const PacketPtr pkt)
Copy the reponse flags from an input packet to this packet.
CacheBlk * handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, bool allocate)
Handle a fill operation caused by a received packet.
void recvTimingSnoopReq(PacketPtr pkt) override
Snoops bus transactions to maintain coherence.
void setCacheResponding()
Snoop flags.
PacketPtr writebackBlk(CacheBlk *blk)
Create a writeback request for the given block.
bool responderHadWritable() const
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
System * system
System we are currently operating in.
int getNumTargets() const
Returns the current number of allocated targets.
void setResponderHadWritable()
On responding to a snoop request (which only happens for Modified or Owned lines),...
const unsigned blkSize
Block size of this cache.
bool forceDeallocateTarget(MSHR *mshr)
Deallocate top target, possibly freeing the MSHR.
void setHasSharers()
On fills, the hasSharers flag is used by the caches in combination with the cacheResponding flag,...
void setSatisfied()
Set when a request hits in a cache and the cache is not going to respond.
Stats::Vector missLatency
Total number of cycles per thread/command spent waiting for a miss.
uint64_t Tick
Tick count type.
Tick sendAtomicSnoop(PacketPtr pkt)
Send an atomic snoop request packet, where the data is moved and the state is updated in zero time,...
Tick recvAtomic(PacketPtr pkt) override
Performs the access specified by the request.
bool needsWritable() const
bool isInvalidate() const
std::shared_ptr< Request > RequestPtr
@ BlkDirty
dirty (modified)
RequestPtr req
A pointer to the original request.
void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) override
virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
unsigned State
block state: OR of CacheBlkStatusBit
uint32_t task_id
Task Id associated with this block.
void schedTimingResp(PacketPtr pkt, Tick when)
Schedule the sending of a timing response.
const Enums::Clusivity clusivity
Clusivity with respect to the upstream cache, determining if we fill into both this cache and the cac...
const int numTarget
The number of targets for each MSHR.
const Cycles forwardLatency
This is the forward latency of the cache.
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
TargetList extractServiceableTargets(PacketPtr pkt)
Extracts the subset of the targets that can be serviced given a received response.
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
void setData(const uint8_t *p)
Copy data into the packet from the provided pointer.
const PacketPtr pkt
Pending request packet.
void copyError(Packet *pkt)
bool isCachedAbove(PacketPtr pkt, bool is_timing=true)
Send up a snoop request and find cached copies.
void sendTimingSnoopReq(PacketPtr pkt)
Attempt to send a timing snoop request packet to the request port by calling its corresponding receiv...
bool isSecure
True if the entry targets the secure memory space.
void allocateWriteBuffer(PacketPtr pkt, Tick time)
bool isWholeLineWrite(unsigned blk_size)
@ SECURE
The request targets the secure memory space.
MSHRQueue mshrQueue
Miss status registers.
Addr regenerateBlkAddr(CacheBlk *blk)
Regenerate block address using tags.
bool matchAddr(const Addr addr, const bool is_secure) const
Check if packet corresponds to a given address and address space.
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the responder port by calling its corresponding receive function.
bool isDirty() const
Check to see if a block has been written.
Tick recvAtomicSnoop(PacketPtr pkt) override
Snoop for the provided request in the cache and return the estimated time taken.
void recvTimingSnoopResp(PacketPtr pkt) override
Handle a snoop response.
bool allocOnFill(MemCmd cmd) const
Determine whether we should allocate on a fill or not.
BaseCache::CacheStats stats
bool handleSnoop(PacketPtr target, Counter order)
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Addr getBlockAddr(unsigned int blk_size) const
void invalidateBlock(CacheBlk *blk)
Invalidate a cache block.
@ wbRequestorId
This requestor id is used for writeback requests by the caches.
void recvTimingReq(PacketPtr pkt) override
Performs the access specified by the request.
void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time) override
bool needsResponse() const
virtual void recvTimingReq(PacketPtr pkt)
Performs the access specified by the request.
Cycles getDecompressionLatency(const CacheBlk *blk)
Get the decompression latency if the block is compressed.
PacketPtr cleanEvictBlk(CacheBlk *blk)
Create a CleanEvict request for the given block.
void schedTimingSnoopResp(PacketPtr pkt, Tick when)
Schedule the sending of a timing snoop response.
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks) override
Does all the processing necessary to perform the provided request.
State status
The current status of this block.
void setDataFromBlock(const uint8_t *blk_data, int blkSize)
Copy data into the packet from the provided block pointer, which is aligned to the given block size.
bool forwardSnoops
Do we forward snoops from mem side port through to cpu side port?
#define chatty_assert(cond,...)
The chatty assert macro will function like a normal assert, but will allow the specification of addit...
bool mustCheckAbove() const
Does the request need to check for cached copies of the same block in the memory hierarchy above.
PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
Create a writeclean request for the given block.
virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks)
Does all the processing necessary to perform the provided request.
const bool isReadOnly
Is this cache read only, for example the instruction cache, or table-walker cache.
Addr getOffset(unsigned int blk_size) const
virtual bool sendMSHRQueuePacket(MSHR *mshr)
Take an MSHR, turn it into a suitable downstream packet, and send it out.
uint32_t snoopDelay
Keep track of the extra delay incurred by snooping upwards before sending a request down the memory s...
std::string print() const override
Pretty-print tag, set and way, and interpret state bits to readable form including mapping to a MOESI...
Entry * findMatch(Addr blk_addr, bool is_secure, bool ignore_uncacheable=true) const
Find the first entry that matches the provided address.
int getNumTargets() const
Returns the current number of allocated targets.
void satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool deferred_response=false, bool pending_downgrade=false) override
Perform any necessary updates to the block and perform any data exchange between the packet and the b...
const Cycles lookupLatency
The latency of tag lookup of a cache.
MSHR * allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send=true)
@ BlkHWPrefetched
block was a hardware prefetch yet unaccessed
Target * getTarget() override
Returns a reference to the first target.
ProbePointArg< PacketInfo > Packet
Packet probe point.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool sendMSHRQueuePacket(MSHR *mshr) override
Take an MSHR, turn it into a suitable downstream packet, and send it out.
virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool deferred_response=false, bool pending_downgrade=false)
Perform any necessary updates to the block and perform any data exchange between the packet and the b...
void promoteWholeLineWrites(PacketPtr pkt)
Turn line-sized writes into WriteInvalidate transactions.
Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks) override
Handle a request in atomic mode that missed in this cache.
QueueEntry::Target * getTarget() override
Returns a reference to the first target.
Compressor::Base * compressor
Compression method being used.
const bool writebackClean
Determine if clean lines should be written back or not.
virtual const std::string name() const
MemCmd cmd
The command field of the packet.
BaseTags * tags
Tag and data Storage.
bool wasWholeLineWrite
Track if we sent this as a whole line write or not.
bool isValid() const
Checks that a block is valid.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
virtual M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk)=0
Evict a cache block.
@ BlkWritable
write permission
bool hasPostDowngrade() const
uint8_t * data
Contains a copy of the data in this block for easy access.
uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, bool is_deferred, bool pending_inval)
Perform an upward snoop if needed, and update the block state (possibly invalidating the block).
RequestorID maxRequestors()
Get the number of requestors registered in the system.
Cycles ticksToCycles(Tick t) const
void setExpressSnoop()
The express snoop flag is used for two purposes.
virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time)=0
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
WriteAllocator *const writeAllocator
The writeAllocator drive optimizations for streaming writes.
bool isMaskedWrite() const
bool allocate() const
Should writes allocate?
bool isUncacheable() const
Cycles is a wrapper class for representing cycle counts, i.e.
bool hasPostInvalidate() const
Stats::Vector mshr_uncacheable
Number of misses that miss in the MSHRs, per command and thread.
const bool doFastWrites
This cache should allocate a block on a line-sized write miss.
PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, bool needs_writable, bool is_whole_line_write) const override
Create an appropriate downstream bus request packet.
const Cycles responseLatency
The latency of sending reponse to its upper level cache/core on a linefill.
void doWritebacks(PacketList &writebacks, Tick forward_time) override
Insert writebacks into the write buffer.
SenderState * senderState
This packet's sender state.
virtual void recvTimingResp(PacketPtr pkt)
Handles a response (cache line fill/write ack) from the bus.
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
bool isBlockCached() const
bool isForward
True if the entry is just a simple forward from an upper level.
void allocate()
Allocate memory for the packet.
A coherent cache that can be arranged in flexible topologies.
Cache(const CacheParams *p)
Instantiates a basic cache object.
virtual Tick recvAtomic(PacketPtr pkt)
Performs the access specified by the request.
void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, bool already_copied, bool pending_inval)
void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk) override
Service non-deferred MSHR targets using the received response.
const T * getConstPtr() const
CacheCmdStats & cmdStats(const PacketPtr p)
bool inRange(Addr addr) const
Determine if an address is in the ranges covered by this cache.
bool isSecure() const
Check if this block holds data from the secure memory space.
#define panic(...)
This implements a cprintf based panic() function.
Miss Status and handling Register.
uint64_t order
Increasing order number assigned to each incoming request.
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