gem5  v20.1.0.0
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DefaultFetch< Impl > Class Template Reference

DefaultFetch class handles both single threaded and SMT fetch. More...

#include <fetch.hh>

Classes

struct  FetchStatGroup
 
class  FetchTranslation
 
class  FinishTranslationEvent
 
class  IcachePort
 IcachePort class for instruction fetch. More...
 
struct  Stalls
 Source of possible stalls. More...
 

Public Types

enum  FetchStatus { Active, Inactive }
 Overall fetch status. More...
 
enum  ThreadStatus {
  Running, Idle, Squashing, Blocked,
  Fetching, TrapPending, QuiescePending, ItlbWait,
  IcacheWaitResponse, IcacheWaitRetry, IcacheAccessComplete, NoGoodAddr
}
 Individual thread status. More...
 
typedef Impl::CPUPol CPUPol
 Typedefs from Impl. More...
 
typedef Impl::DynInst DynInst
 
typedef Impl::DynInstPtr DynInstPtr
 
typedef Impl::O3CPU O3CPU
 
typedef CPUPol::FetchStruct FetchStruct
 Typedefs from the CPU policy. More...
 
typedef CPUPol::TimeStruct TimeStruct
 
typedef TheISA::MachInst MachInst
 Typedefs from ISA. More...
 

Public Member Functions

 DefaultFetch (O3CPU *_cpu, DerivO3CPUParams *params)
 DefaultFetch constructor. More...
 
std::string name () const
 Returns the name of fetch. More...
 
void regProbePoints ()
 Registers probes. More...
 
void setTimeBuffer (TimeBuffer< TimeStruct > *time_buffer)
 Sets the main backwards communication time buffer pointer. More...
 
void setActiveThreads (std::list< ThreadID > *at_ptr)
 Sets pointer to list of active threads. More...
 
void setFetchQueue (TimeBuffer< FetchStruct > *fq_ptr)
 Sets pointer to time buffer used to communicate to the next stage. More...
 
void startupStage ()
 Initialize stage. More...
 
void clearStates (ThreadID tid)
 Clear all thread-specific states. More...
 
void recvReqRetry ()
 Handles retrying the fetch access. More...
 
void processCacheCompletion (PacketPtr pkt)
 Processes cache completion event. More...
 
void drainResume ()
 Resume after a drain. More...
 
void drainSanityCheck () const
 Perform sanity checks after a drain. More...
 
bool isDrained () const
 Has the stage drained? More...
 
void takeOverFrom ()
 Takes over from another CPU's thread. More...
 
void drainStall (ThreadID tid)
 Stall the fetch stage after reaching a safe drain point. More...
 
void wakeFromQuiesce ()
 Tells fetch to wake up from a quiesce instruction. More...
 
void deactivateThread (ThreadID tid)
 For priority-based fetch policies, need to keep update priorityList. More...
 
void squash (const TheISA::PCState &newPC, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid)
 Squashes a specific thread and resets the PC. More...
 
void tick ()
 Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible. More...
 
bool checkSignalsAndUpdate (ThreadID tid)
 Checks all input signals and updates the status as necessary. More...
 
void fetch (bool &status_change)
 Does the actual fetching of instructions and passing them on to the next stage. More...
 
Addr fetchBufferAlignPC (Addr addr)
 Align a PC to the start of a fetch buffer block. More...
 
RequestPortgetInstPort ()
 

Public Attributes

TheISA::Decoder * decoder [Impl::MaxThreads]
 The decoder. More...
 

Protected Attributes

DefaultFetch::FetchStatGroup fetchStats
 

Private Member Functions

void resetStage ()
 Reset this pipeline stage. More...
 
void switchToActive ()
 Changes the status of this stage to active, and indicates this to the CPU. More...
 
void switchToInactive ()
 Changes the status of this stage to inactive, and indicates this to the CPU. More...
 
bool lookupAndUpdateNextPC (const DynInstPtr &inst, TheISA::PCState &pc)
 Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch target. More...
 
bool fetchCacheLine (Addr vaddr, ThreadID tid, Addr pc)
 Fetches the cache line that contains the fetch PC. More...
 
void finishTranslation (const Fault &fault, const RequestPtr &mem_req)
 
bool checkInterrupt (Addr pc)
 Check if an interrupt is pending and that we need to handle. More...
 
void doSquash (const TheISA::PCState &newPC, const DynInstPtr squashInst, ThreadID tid)
 Squashes a specific thread and resets the PC. More...
 
void squashFromDecode (const TheISA::PCState &newPC, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid)
 Squashes a specific thread and resets the PC. More...
 
bool checkStall (ThreadID tid) const
 Checks if a thread is stalled. More...
 
FetchStatus updateFetchStatus ()
 Updates overall fetch stage status; to be called at the end of each cycle. More...
 
DynInstPtr buildInst (ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, TheISA::PCState thisPC, TheISA::PCState nextPC, bool trace)
 
ThreadID getFetchingThread ()
 Returns the appropriate thread to fetch, given the fetch policy. More...
 
ThreadID roundRobin ()
 Returns the appropriate thread to fetch using a round robin policy. More...
 
ThreadID iqCount ()
 Returns the appropriate thread to fetch using the IQ count policy. More...
 
ThreadID lsqCount ()
 Returns the appropriate thread to fetch using the LSQ count policy. More...
 
ThreadID branchCount ()
 Returns the appropriate thread to fetch using the branch count policy. More...
 
void pipelineIcacheAccesses (ThreadID tid)
 Pipeline the next I-cache access to the current one. More...
 
void profileStall (ThreadID tid)
 Profile the reasons of fetch stall. More...
 

Private Attributes

FetchStatus _status
 Fetch status. More...
 
ThreadStatus fetchStatus [Impl::MaxThreads]
 Per-thread status. More...
 
FetchPolicy fetchPolicy
 Fetch policy. More...
 
std::list< ThreadIDpriorityList
 List that has the threads organized by priority. More...
 
ProbePointArg< DynInstPtr > * ppFetch
 Probe points. More...
 
ProbePointArg< RequestPtr > * ppFetchRequestSent
 To probe when a fetch request is successfully sent. More...
 
O3CPUcpu
 Pointer to the O3CPU. More...
 
TimeBuffer< TimeStruct > * timeBuffer
 Time buffer interface. More...
 
TimeBuffer< TimeStruct >::wire fromDecode
 Wire to get decode's information from backwards time buffer. More...
 
TimeBuffer< TimeStruct >::wire fromRename
 Wire to get rename's information from backwards time buffer. More...
 
TimeBuffer< TimeStruct >::wire fromIEW
 Wire to get iew's information from backwards time buffer. More...
 
TimeBuffer< TimeStruct >::wire fromCommit
 Wire to get commit's information from backwards time buffer. More...
 
TimeBuffer< FetchStruct >::wire toDecode
 Wire used to write any information heading to decode. More...
 
BPredUnitbranchPred
 BPredUnit. More...
 
TheISA::PCState pc [Impl::MaxThreads]
 
Addr fetchOffset [Impl::MaxThreads]
 
StaticInstPtr macroop [Impl::MaxThreads]
 
bool delayedCommit [Impl::MaxThreads]
 Can the fetch stage redirect from an interrupt on this instruction? More...
 
RequestPtr memReq [Impl::MaxThreads]
 Memory request used to access cache. More...
 
bool wroteToTimeBuffer
 Variable that tracks if fetch has written to the time buffer this cycle. More...
 
int numInst
 Tracks how many instructions has been fetched this cycle. More...
 
Stalls stalls [Impl::MaxThreads]
 Tracks which stages are telling fetch to stall. More...
 
Cycles decodeToFetchDelay
 Decode to fetch delay. More...
 
Cycles renameToFetchDelay
 Rename to fetch delay. More...
 
Cycles iewToFetchDelay
 IEW to fetch delay. More...
 
Cycles commitToFetchDelay
 Commit to fetch delay. More...
 
unsigned fetchWidth
 The width of fetch in instructions. More...
 
unsigned decodeWidth
 The width of decode in instructions. More...
 
bool cacheBlocked
 Is the cache blocked? If so no threads can access it. More...
 
PacketPtr retryPkt
 The packet that is waiting to be retried. More...
 
ThreadID retryTid
 The thread that is waiting on the cache to tell fetch to retry. More...
 
unsigned int cacheBlkSize
 Cache block size. More...
 
unsigned fetchBufferSize
 The size of the fetch buffer in bytes. More...
 
Addr fetchBufferMask
 Mask to align a fetch address to a fetch buffer boundary. More...
 
uint8_t * fetchBuffer [Impl::MaxThreads]
 The fetch data that is being fetched and buffered. More...
 
Addr fetchBufferPC [Impl::MaxThreads]
 The PC of the first instruction loaded into the fetch buffer. More...
 
unsigned fetchQueueSize
 The size of the fetch queue in micro-ops. More...
 
std::deque< DynInstPtrfetchQueue [Impl::MaxThreads]
 Queue of fetched instructions. More...
 
bool fetchBufferValid [Impl::MaxThreads]
 Whether or not the fetch buffer data is valid. More...
 
int instSize
 Size of instructions. More...
 
Counter lastIcacheStall [Impl::MaxThreads]
 Icache stall statistics. More...
 
std::list< ThreadID > * activeThreads
 List of Active Threads. More...
 
ThreadID numThreads
 Number of threads. More...
 
ThreadID numFetchingThreads
 Number of threads that are actively fetching. More...
 
ThreadID threadFetched
 Thread ID being fetched. More...
 
bool interruptPending
 Checks if there is an interrupt pending. More...
 
IcachePort icachePort
 Instruction port. More...
 
bool issuePipelinedIfetch [Impl::MaxThreads]
 Set to true if a pipelined I-cache request should be issued. More...
 
FinishTranslationEvent finishTranslationEvent
 Event used to delay fault generation of translation faults. More...
 

Detailed Description

template<class Impl>
class DefaultFetch< Impl >

DefaultFetch class handles both single threaded and SMT fetch.

Its width is specified by the parameters; each cycle it tries to fetch that many instructions. It supports using a branch predictor to predict direction and targets. It supports the idling functionality of the CPU by indicating to the CPU when it is active and inactive.

Definition at line 71 of file fetch.hh.

Member Typedef Documentation

◆ CPUPol

template<class Impl >
typedef Impl::CPUPol DefaultFetch< Impl >::CPUPol

Typedefs from Impl.

Definition at line 75 of file fetch.hh.

◆ DynInst

template<class Impl >
typedef Impl::DynInst DefaultFetch< Impl >::DynInst

Definition at line 76 of file fetch.hh.

◆ DynInstPtr

template<class Impl >
typedef Impl::DynInstPtr DefaultFetch< Impl >::DynInstPtr

Definition at line 77 of file fetch.hh.

◆ FetchStruct

template<class Impl >
typedef CPUPol::FetchStruct DefaultFetch< Impl >::FetchStruct

Typedefs from the CPU policy.

Definition at line 81 of file fetch.hh.

◆ MachInst

template<class Impl >
typedef TheISA::MachInst DefaultFetch< Impl >::MachInst

Typedefs from ISA.

Definition at line 85 of file fetch.hh.

◆ O3CPU

template<class Impl >
typedef Impl::O3CPU DefaultFetch< Impl >::O3CPU

Definition at line 78 of file fetch.hh.

◆ TimeStruct

template<class Impl >
typedef CPUPol::TimeStruct DefaultFetch< Impl >::TimeStruct

Definition at line 82 of file fetch.hh.

Member Enumeration Documentation

◆ FetchStatus

template<class Impl >
enum DefaultFetch::FetchStatus

Overall fetch status.

Used to determine if the CPU can deschedule itsef due to a lack of activity.

Enumerator
Active 
Inactive 

Definition at line 179 of file fetch.hh.

◆ ThreadStatus

template<class Impl >
enum DefaultFetch::ThreadStatus

Individual thread status.

Enumerator
Running 
Idle 
Squashing 
Blocked 
Fetching 
TrapPending 
QuiescePending 
ItlbWait 
IcacheWaitResponse 
IcacheWaitRetry 
IcacheAccessComplete 
NoGoodAddr 

Definition at line 185 of file fetch.hh.

Constructor & Destructor Documentation

◆ DefaultFetch()

template<class Impl >
DefaultFetch< Impl >::DefaultFetch ( O3CPU _cpu,
DerivO3CPUParams *  params 
)

Member Function Documentation

◆ branchCount()

template<class Impl >
ThreadID DefaultFetch< Impl >::branchCount
private

Returns the appropriate thread to fetch using the branch count policy.

Definition at line 1553 of file fetch_impl.hh.

References InvalidThreadID, and panic.

Referenced by DefaultFetch< Impl >::getFetchingThread().

◆ buildInst()

template<class Impl >
Impl::DynInstPtr DefaultFetch< Impl >::buildInst ( ThreadID  tid,
StaticInstPtr  staticInst,
StaticInstPtr  curMacroop,
TheISA::PCState  thisPC,
TheISA::PCState  nextPC,
bool  trace 
)
private

◆ checkInterrupt()

template<class Impl >
bool DefaultFetch< Impl >::checkInterrupt ( Addr  pc)
inlineprivate

Check if an interrupt is pending and that we need to handle.

Definition at line 321 of file fetch.hh.

References DefaultFetch< Impl >::interruptPending.

Referenced by DefaultFetch< Impl >::fetch(), and DefaultFetch< Impl >::fetchCacheLine().

◆ checkSignalsAndUpdate()

template<class Impl >
bool DefaultFetch< Impl >::checkSignalsAndUpdate ( ThreadID  tid)

◆ checkStall()

template<class Impl >
bool DefaultFetch< Impl >::checkStall ( ThreadID  tid) const
private

◆ clearStates()

template<class Impl >
void DefaultFetch< Impl >::clearStates ( ThreadID  tid)

◆ deactivateThread()

template<class Impl >
void DefaultFetch< Impl >::deactivateThread ( ThreadID  tid)

For priority-based fetch policies, need to keep update priorityList.

Definition at line 512 of file fetch_impl.hh.

References DefaultFetch< Impl >::priorityList.

◆ doSquash()

template<class Impl >
void DefaultFetch< Impl >::doSquash ( const TheISA::PCState &  newPC,
const DynInstPtr  squashInst,
ThreadID  tid 
)
inlineprivate

◆ drainResume()

template<class Impl >
void DefaultFetch< Impl >::drainResume

◆ drainSanityCheck()

template<class Impl >
void DefaultFetch< Impl >::drainSanityCheck

◆ drainStall()

template<class Impl >
void DefaultFetch< Impl >::drainStall ( ThreadID  tid)

Stall the fetch stage after reaching a safe drain point.

The CPU uses this method to stop fetching instructions from a thread that has been drained. The drain stall is different from all other stalls in that it is signaled instantly from the commit stage (without the normal communication delay) when it has reached a safe point to drain from.

Definition at line 466 of file fetch_impl.hh.

References DefaultFetch< Impl >::cpu, DPRINTF, DefaultFetch< Impl >::Stalls::drain, and DefaultFetch< Impl >::stalls.

◆ fetch()

template<class Impl >
void DefaultFetch< Impl >::fetch ( bool &  status_change)

Does the actual fetching of instructions and passing them on to the next stage.

Parameters
status_changefetch() sets this variable if there was a status change (ie switching to IcacheMissStall).

Definition at line 1121 of file fetch_impl.hh.

References DefaultFetch< Impl >::buildInst(), DefaultFetch< Impl >::checkInterrupt(), DefaultFetch< Impl >::cpu, curTick(), DefaultFetch< Impl >::FetchStatGroup::cycles, DefaultFetch< Impl >::decoder, DefaultFetch< Impl >::delayedCommit, DPRINTF, DTRACE, DefaultFetch< Impl >::fetchBuffer, DefaultFetch< Impl >::fetchBufferAlignPC(), DefaultFetch< Impl >::fetchBufferPC, DefaultFetch< Impl >::fetchBufferSize, DefaultFetch< Impl >::fetchBufferValid, DefaultFetch< Impl >::fetchCacheLine(), StaticInst::fetchMicroop(), DefaultFetch< Impl >::fetchOffset, DefaultFetch< Impl >::fetchQueue, DefaultFetch< Impl >::fetchQueueSize, DefaultFetch< Impl >::fetchStats, DefaultFetch< Impl >::fetchStatus, DefaultFetch< Impl >::fetchWidth, DefaultFetch< Impl >::getFetchingThread(), DefaultFetch< Impl >::IcacheAccessComplete, DefaultFetch< Impl >::FetchStatGroup::icacheStallCycles, DefaultFetch< Impl >::IcacheWaitResponse, DefaultFetch< Impl >::IcacheWaitRetry, DefaultFetch< Impl >::Idle, DefaultFetch< Impl >::FetchStatGroup::idleCycles, DefaultFetch< Impl >::FetchStatGroup::insts, DefaultFetch< Impl >::instSize, InvalidThreadID, StaticInst::isLastMicroop(), StaticInst::isMacroop(), isRomMicroPC(), DefaultFetch< Impl >::issuePipelinedIfetch, DefaultFetch< Impl >::ItlbWait, DefaultFetch< Impl >::lookupAndUpdateNextPC(), DefaultFetch< Impl >::macroop, DefaultFetch< Impl >::FetchStatGroup::miscStallCycles, ProbePointArg< Arg >::notify(), DefaultFetch< Impl >::numFetchingThreads, DefaultFetch< Impl >::numInst, DefaultFetch< Impl >::numThreads, DefaultFetch< Impl >::pc, BaseCPU::PCMask, DefaultFetch< Impl >::ppFetch, DefaultFetch< Impl >::profileStall(), PseudoInst::quiesce(), DefaultFetch< Impl >::QuiescePending, DefaultFetch< Impl >::Running, DefaultFetch< Impl >::threadFetched, DefaultFetch< Impl >::FetchStatGroup::tlbCycles, and DefaultFetch< Impl >::wroteToTimeBuffer.

Referenced by DefaultFetch< Impl >::FetchStatGroup::FetchStatGroup(), DefaultFetch< Impl >::IcachePort::recvReqRetry(), DefaultFetch< Impl >::IcachePort::recvTimingResp(), and DefaultFetch< Impl >::tick().

◆ fetchBufferAlignPC()

template<class Impl >
Addr DefaultFetch< Impl >::fetchBufferAlignPC ( Addr  addr)
inline

Align a PC to the start of a fetch buffer block.

Definition at line 371 of file fetch.hh.

References addr, and DefaultFetch< Impl >::fetchBufferMask.

Referenced by DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::fetchCacheLine(), and DefaultFetch< Impl >::pipelineIcacheAccesses().

◆ fetchCacheLine()

template<class Impl >
bool DefaultFetch< Impl >::fetchCacheLine ( Addr  vaddr,
ThreadID  tid,
Addr  pc 
)
private

Fetches the cache line that contains the fetch PC.

Returns any fault that happened. Puts the data into the class variable fetchBuffer, which may not hold the entire fetched cache line.

Parameters
vaddrThe memory address that is being fetched from.
ret_faultThe fault reference that will be set to the result of the icache access.
tidThread id.
pcThe actual PC of the current instruction.
Returns
Any fault that occured.

Definition at line 569 of file fetch_impl.hh.

References DefaultFetch< Impl >::cacheBlocked, DefaultFetch< Impl >::checkInterrupt(), DefaultFetch< Impl >::cpu, DefaultFetch< Impl >::delayedCommit, DPRINTF, BaseTLB::Execute, DefaultFetch< Impl >::fetchBufferAlignPC(), DefaultFetch< Impl >::fetchBufferSize, DefaultFetch< Impl >::fetchStatus, Request::INST_FETCH, DefaultFetch< Impl >::ItlbWait, DefaultFetch< Impl >::memReq, NoFault, DefaultFetch< Impl >::pc, and MipsISA::vaddr.

Referenced by DefaultFetch< Impl >::fetch(), and DefaultFetch< Impl >::pipelineIcacheAccesses().

◆ finishTranslation()

template<class Impl >
void DefaultFetch< Impl >::finishTranslation ( const Fault fault,
const RequestPtr mem_req 
)
private

◆ getFetchingThread()

template<class Impl >
ThreadID DefaultFetch< Impl >::getFetchingThread
private

◆ getInstPort()

template<class Impl >
RequestPort& DefaultFetch< Impl >::getInstPort ( )
inline

Definition at line 379 of file fetch.hh.

References DefaultFetch< Impl >::icachePort.

◆ iqCount()

template<class Impl >
ThreadID DefaultFetch< Impl >::iqCount
private

◆ isDrained()

template<class Impl >
bool DefaultFetch< Impl >::isDrained

◆ lookupAndUpdateNextPC()

template<class Impl >
bool DefaultFetch< Impl >::lookupAndUpdateNextPC ( const DynInstPtr inst,
TheISA::PCState &  pc 
)
private

Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch target.

Parameters
next_PCNext PC variable passed in by reference. It is expected to be set to the current PC; it will be updated with what the next PC will be.
next_NPCUsed for ISAs which use delay slots.
Returns
Whether or not a branch was predicted as taken.

Definition at line 523 of file fetch_impl.hh.

References ArmISA::advancePC(), DefaultFetch< Impl >::FetchStatGroup::branches, DefaultFetch< Impl >::branchPred, DPRINTF, DefaultFetch< Impl >::fetchStats, BPredUnit::predict(), and DefaultFetch< Impl >::FetchStatGroup::predictedBranches.

Referenced by DefaultFetch< Impl >::fetch().

◆ lsqCount()

template<class Impl >
ThreadID DefaultFetch< Impl >::lsqCount
private

◆ name()

template<class Impl >
std::string DefaultFetch< Impl >::name

Returns the name of fetch.

Definition at line 150 of file fetch_impl.hh.

◆ pipelineIcacheAccesses()

template<class Impl >
void DefaultFetch< Impl >::pipelineIcacheAccesses ( ThreadID  tid)
private

◆ processCacheCompletion()

template<class Impl >
void DefaultFetch< Impl >::processCacheCompletion ( PacketPtr  pkt)

◆ profileStall()

template<class Impl >
void DefaultFetch< Impl >::profileStall ( ThreadID  tid)
private

◆ recvReqRetry()

template<class Impl >
void DefaultFetch< Impl >::recvReqRetry

◆ regProbePoints()

template<class Impl >
void DefaultFetch< Impl >::regProbePoints

Registers probes.

Definition at line 157 of file fetch_impl.hh.

◆ resetStage()

template<class Impl >
void DefaultFetch< Impl >::resetStage
private

◆ roundRobin()

template<class Impl >
ThreadID DefaultFetch< Impl >::roundRobin
private

◆ setActiveThreads()

template<class Impl >
void DefaultFetch< Impl >::setActiveThreads ( std::list< ThreadID > *  at_ptr)

Sets pointer to list of active threads.

Definition at line 272 of file fetch_impl.hh.

References DefaultFetch< Impl >::activeThreads.

◆ setFetchQueue()

template<class Impl >
void DefaultFetch< Impl >::setFetchQueue ( TimeBuffer< FetchStruct > *  fq_ptr)

Sets pointer to time buffer used to communicate to the next stage.

Definition at line 279 of file fetch_impl.hh.

References TimeBuffer< T >::getWire(), and DefaultFetch< Impl >::toDecode.

◆ setTimeBuffer()

template<class Impl >
void DefaultFetch< Impl >::setTimeBuffer ( TimeBuffer< TimeStruct > *  time_buffer)

◆ squash()

template<class Impl >
void DefaultFetch< Impl >::squash ( const TheISA::PCState &  newPC,
const InstSeqNum  seq_num,
DynInstPtr  squashInst,
ThreadID  tid 
)

Squashes a specific thread and resets the PC.

Also tells the CPU to remove any instructions that are not in the ROB. The source of this squash should be the commit stage.

Definition at line 848 of file fetch_impl.hh.

References DefaultFetch< Impl >::cpu, DefaultFetch< Impl >::doSquash(), and DPRINTF.

Referenced by DefaultFetch< Impl >::checkSignalsAndUpdate().

◆ squashFromDecode()

template<class Impl >
void DefaultFetch< Impl >::squashFromDecode ( const TheISA::PCState &  newPC,
const DynInstPtr  squashInst,
const InstSeqNum  seq_num,
ThreadID  tid 
)
private

Squashes a specific thread and resets the PC.

Also tells the CPU to remove any instructions between fetch and decode that should be sqaushed.

Definition at line 778 of file fetch_impl.hh.

References DefaultFetch< Impl >::cpu, DefaultFetch< Impl >::doSquash(), and DPRINTF.

Referenced by DefaultFetch< Impl >::checkSignalsAndUpdate().

◆ startupStage()

template<class Impl >
void DefaultFetch< Impl >::startupStage

◆ switchToActive()

template<class Impl >
void DefaultFetch< Impl >::switchToActive
inlineprivate

Changes the status of this stage to active, and indicates this to the CPU.

Definition at line 486 of file fetch_impl.hh.

References DefaultFetch< Impl >::_status, DefaultFetch< Impl >::Active, DefaultFetch< Impl >::cpu, DPRINTF, and DefaultFetch< Impl >::Inactive.

Referenced by DefaultFetch< Impl >::processCacheCompletion(), and DefaultFetch< Impl >::startupStage().

◆ switchToInactive()

template<class Impl >
void DefaultFetch< Impl >::switchToInactive
inlineprivate

Changes the status of this stage to inactive, and indicates this to the CPU.

Definition at line 499 of file fetch_impl.hh.

References DefaultFetch< Impl >::_status, DefaultFetch< Impl >::Active, DefaultFetch< Impl >::cpu, DPRINTF, and DefaultFetch< Impl >::Inactive.

◆ takeOverFrom()

template<class Impl >
void DefaultFetch< Impl >::takeOverFrom

Takes over from another CPU's thread.

Definition at line 457 of file fetch_impl.hh.

References DefaultFetch< Impl >::cpu, and DefaultFetch< Impl >::resetStage().

◆ tick()

template<class Impl >
void DefaultFetch< Impl >::tick

◆ updateFetchStatus()

template<class Impl >
DefaultFetch< Impl >::FetchStatus DefaultFetch< Impl >::updateFetchStatus
private

◆ wakeFromQuiesce()

template<class Impl >
void DefaultFetch< Impl >::wakeFromQuiesce

Tells fetch to wake up from a quiesce instruction.

Definition at line 476 of file fetch_impl.hh.

References DPRINTF, DefaultFetch< Impl >::fetchStatus, and DefaultFetch< Impl >::Running.

Member Data Documentation

◆ _status

template<class Impl >
FetchStatus DefaultFetch< Impl >::_status
private

◆ activeThreads

template<class Impl >
std::list<ThreadID>* DefaultFetch< Impl >::activeThreads
private

◆ branchPred

template<class Impl >
BPredUnit* DefaultFetch< Impl >::branchPred
private

◆ cacheBlkSize

template<class Impl >
unsigned int DefaultFetch< Impl >::cacheBlkSize
private

Cache block size.

Definition at line 491 of file fetch.hh.

Referenced by DefaultFetch< Impl >::DefaultFetch().

◆ cacheBlocked

template<class Impl >
bool DefaultFetch< Impl >::cacheBlocked
private

◆ commitToFetchDelay

template<class Impl >
Cycles DefaultFetch< Impl >::commitToFetchDelay
private

Commit to fetch delay.

Definition at line 473 of file fetch.hh.

Referenced by DefaultFetch< Impl >::setTimeBuffer().

◆ cpu

template<class Impl >
O3CPU* DefaultFetch< Impl >::cpu
private

◆ decoder

template<class Impl >
TheISA::Decoder* DefaultFetch< Impl >::decoder[Impl::MaxThreads]

◆ decodeToFetchDelay

template<class Impl >
Cycles DefaultFetch< Impl >::decodeToFetchDelay
private

Decode to fetch delay.

Definition at line 464 of file fetch.hh.

Referenced by DefaultFetch< Impl >::setTimeBuffer().

◆ decodeWidth

template<class Impl >
unsigned DefaultFetch< Impl >::decodeWidth
private

The width of decode in instructions.

Definition at line 479 of file fetch.hh.

Referenced by DefaultFetch< Impl >::tick().

◆ delayedCommit

template<class Impl >
bool DefaultFetch< Impl >::delayedCommit[Impl::MaxThreads]
private

◆ fetchBuffer

template<class Impl >
uint8_t* DefaultFetch< Impl >::fetchBuffer[Impl::MaxThreads]
private

The fetch data that is being fetched and buffered.

Definition at line 502 of file fetch.hh.

Referenced by DefaultFetch< Impl >::DefaultFetch(), DefaultFetch< Impl >::fetch(), and DefaultFetch< Impl >::processCacheCompletion().

◆ fetchBufferMask

template<class Impl >
Addr DefaultFetch< Impl >::fetchBufferMask
private

Mask to align a fetch address to a fetch buffer boundary.

Definition at line 499 of file fetch.hh.

Referenced by DefaultFetch< Impl >::fetchBufferAlignPC().

◆ fetchBufferPC

template<class Impl >
Addr DefaultFetch< Impl >::fetchBufferPC[Impl::MaxThreads]
private

◆ fetchBufferSize

template<class Impl >
unsigned DefaultFetch< Impl >::fetchBufferSize
private

The size of the fetch buffer in bytes.

The fetch buffer itself may be smaller than a cache line.

Definition at line 496 of file fetch.hh.

Referenced by DefaultFetch< Impl >::DefaultFetch(), DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::fetchCacheLine(), DefaultFetch< Impl >::finishTranslation(), and DefaultFetch< Impl >::processCacheCompletion().

◆ fetchBufferValid

template<class Impl >
bool DefaultFetch< Impl >::fetchBufferValid[Impl::MaxThreads]
private

◆ fetchOffset

template<class Impl >
Addr DefaultFetch< Impl >::fetchOffset[Impl::MaxThreads]
private

◆ fetchPolicy

template<class Impl >
FetchPolicy DefaultFetch< Impl >::fetchPolicy
private

Fetch policy.

Definition at line 208 of file fetch.hh.

Referenced by DefaultFetch< Impl >::DefaultFetch(), and DefaultFetch< Impl >::getFetchingThread().

◆ fetchQueue

template<class Impl >
std::deque<DynInstPtr> DefaultFetch< Impl >::fetchQueue[Impl::MaxThreads]
private

◆ fetchQueueSize

template<class Impl >
unsigned DefaultFetch< Impl >::fetchQueueSize
private

The size of the fetch queue in micro-ops.

Definition at line 508 of file fetch.hh.

Referenced by DefaultFetch< Impl >::buildInst(), DefaultFetch< Impl >::fetch(), and DefaultFetch< Impl >::finishTranslation().

◆ fetchStats

template<class Impl >
DefaultFetch::FetchStatGroup DefaultFetch< Impl >::fetchStats
protected

◆ fetchStatus

template<class Impl >
ThreadStatus DefaultFetch< Impl >::fetchStatus[Impl::MaxThreads]
private

◆ fetchWidth

template<class Impl >
unsigned DefaultFetch< Impl >::fetchWidth
private

◆ finishTranslationEvent

template<class Impl >
FinishTranslationEvent DefaultFetch< Impl >::finishTranslationEvent
private

Event used to delay fault generation of translation faults.

Definition at line 546 of file fetch.hh.

Referenced by DefaultFetch< Impl >::finishTranslation(), and DefaultFetch< Impl >::isDrained().

◆ fromCommit

template<class Impl >
TimeBuffer<TimeStruct>::wire DefaultFetch< Impl >::fromCommit
private

Wire to get commit's information from backwards time buffer.

Definition at line 425 of file fetch.hh.

Referenced by DefaultFetch< Impl >::checkSignalsAndUpdate(), DefaultFetch< Impl >::setTimeBuffer(), and DefaultFetch< Impl >::tick().

◆ fromDecode

template<class Impl >
TimeBuffer<TimeStruct>::wire DefaultFetch< Impl >::fromDecode
private

Wire to get decode's information from backwards time buffer.

Definition at line 416 of file fetch.hh.

Referenced by DefaultFetch< Impl >::checkSignalsAndUpdate(), and DefaultFetch< Impl >::setTimeBuffer().

◆ fromIEW

template<class Impl >
TimeBuffer<TimeStruct>::wire DefaultFetch< Impl >::fromIEW
private

Wire to get iew's information from backwards time buffer.

Definition at line 422 of file fetch.hh.

Referenced by DefaultFetch< Impl >::iqCount(), DefaultFetch< Impl >::lsqCount(), and DefaultFetch< Impl >::setTimeBuffer().

◆ fromRename

template<class Impl >
TimeBuffer<TimeStruct>::wire DefaultFetch< Impl >::fromRename
private

Wire to get rename's information from backwards time buffer.

Definition at line 419 of file fetch.hh.

Referenced by DefaultFetch< Impl >::setTimeBuffer().

◆ icachePort

template<class Impl >
IcachePort DefaultFetch< Impl >::icachePort
private

Instruction port.

Note that it has to appear after the fetch stage.

Definition at line 540 of file fetch.hh.

Referenced by DefaultFetch< Impl >::finishTranslation(), DefaultFetch< Impl >::getInstPort(), and DefaultFetch< Impl >::recvReqRetry().

◆ iewToFetchDelay

template<class Impl >
Cycles DefaultFetch< Impl >::iewToFetchDelay
private

IEW to fetch delay.

Definition at line 470 of file fetch.hh.

Referenced by DefaultFetch< Impl >::setTimeBuffer().

◆ instSize

template<class Impl >
int DefaultFetch< Impl >::instSize
private

Size of instructions.

Definition at line 517 of file fetch.hh.

Referenced by DefaultFetch< Impl >::DefaultFetch(), and DefaultFetch< Impl >::fetch().

◆ interruptPending

template<class Impl >
bool DefaultFetch< Impl >::interruptPending
private

Checks if there is an interrupt pending.

If there is, fetch must stop once it is not fetching PAL instructions.

Definition at line 537 of file fetch.hh.

Referenced by DefaultFetch< Impl >::checkInterrupt(), DefaultFetch< Impl >::drainSanityCheck(), DefaultFetch< Impl >::resetStage(), and DefaultFetch< Impl >::tick().

◆ issuePipelinedIfetch

template<class Impl >
bool DefaultFetch< Impl >::issuePipelinedIfetch[Impl::MaxThreads]
private

Set to true if a pipelined I-cache request should be issued.

Definition at line 543 of file fetch.hh.

Referenced by DefaultFetch< Impl >::DefaultFetch(), DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::pipelineIcacheAccesses(), and DefaultFetch< Impl >::tick().

◆ lastIcacheStall

template<class Impl >
Counter DefaultFetch< Impl >::lastIcacheStall[Impl::MaxThreads]
private

Icache stall statistics.

Definition at line 520 of file fetch.hh.

Referenced by DefaultFetch< Impl >::DefaultFetch(), and DefaultFetch< Impl >::finishTranslation().

◆ macroop

template<class Impl >
StaticInstPtr DefaultFetch< Impl >::macroop[Impl::MaxThreads]
private

◆ memReq

template<class Impl >
RequestPtr DefaultFetch< Impl >::memReq[Impl::MaxThreads]
private

◆ numFetchingThreads

template<class Impl >
ThreadID DefaultFetch< Impl >::numFetchingThreads
private

Number of threads that are actively fetching.

Definition at line 529 of file fetch.hh.

Referenced by DefaultFetch< Impl >::fetch(), and DefaultFetch< Impl >::tick().

◆ numInst

template<class Impl >
int DefaultFetch< Impl >::numInst
private

◆ numThreads

template<class Impl >
ThreadID DefaultFetch< Impl >::numThreads
private

◆ pc

template<class Impl >
TheISA::PCState DefaultFetch< Impl >::pc[Impl::MaxThreads]
private

◆ ppFetch

template<class Impl >
ProbePointArg<DynInstPtr>* DefaultFetch< Impl >::ppFetch
private

Probe points.

Definition at line 214 of file fetch.hh.

Referenced by DefaultFetch< Impl >::fetch().

◆ ppFetchRequestSent

template<class Impl >
ProbePointArg<RequestPtr>* DefaultFetch< Impl >::ppFetchRequestSent
private

To probe when a fetch request is successfully sent.

Definition at line 216 of file fetch.hh.

Referenced by DefaultFetch< Impl >::finishTranslation(), and DefaultFetch< Impl >::recvReqRetry().

◆ priorityList

template<class Impl >
std::list<ThreadID> DefaultFetch< Impl >::priorityList
private

List that has the threads organized by priority.

Definition at line 211 of file fetch.hh.

Referenced by DefaultFetch< Impl >::deactivateThread(), DefaultFetch< Impl >::resetStage(), DefaultFetch< Impl >::roundRobin(), and DefaultFetch< Impl >::startupStage().

◆ renameToFetchDelay

template<class Impl >
Cycles DefaultFetch< Impl >::renameToFetchDelay
private

Rename to fetch delay.

Definition at line 467 of file fetch.hh.

Referenced by DefaultFetch< Impl >::setTimeBuffer().

◆ retryPkt

template<class Impl >
PacketPtr DefaultFetch< Impl >::retryPkt
private

◆ retryTid

template<class Impl >
ThreadID DefaultFetch< Impl >::retryTid
private

The thread that is waiting on the cache to tell fetch to retry.

Definition at line 488 of file fetch.hh.

Referenced by DefaultFetch< Impl >::doSquash(), DefaultFetch< Impl >::drainSanityCheck(), DefaultFetch< Impl >::finishTranslation(), and DefaultFetch< Impl >::recvReqRetry().

◆ stalls

template<class Impl >
Stalls DefaultFetch< Impl >::stalls[Impl::MaxThreads]
private

◆ threadFetched

template<class Impl >
ThreadID DefaultFetch< Impl >::threadFetched
private

Thread ID being fetched.

Definition at line 532 of file fetch.hh.

Referenced by DefaultFetch< Impl >::fetch(), and DefaultFetch< Impl >::tick().

◆ timeBuffer

template<class Impl >
TimeBuffer<TimeStruct>* DefaultFetch< Impl >::timeBuffer
private

Time buffer interface.

Definition at line 413 of file fetch.hh.

Referenced by DefaultFetch< Impl >::setTimeBuffer().

◆ toDecode

template<class Impl >
TimeBuffer<FetchStruct>::wire DefaultFetch< Impl >::toDecode
private

Wire used to write any information heading to decode.

Definition at line 429 of file fetch.hh.

Referenced by DefaultFetch< Impl >::setFetchQueue(), and DefaultFetch< Impl >::tick().

◆ wroteToTimeBuffer

template<class Impl >
bool DefaultFetch< Impl >::wroteToTimeBuffer
private

Variable that tracks if fetch has written to the time buffer this cycle.

Used to tell CPU if there is activity this cycle.

Definition at line 449 of file fetch.hh.

Referenced by DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::finishTranslation(), DefaultFetch< Impl >::resetStage(), and DefaultFetch< Impl >::tick().


The documentation for this class was generated from the following files:

Generated on Wed Sep 30 2020 14:02:23 for gem5 by doxygen 1.8.17