gem5  v20.1.0.0
fetch.hh
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40 
41 #ifndef __CPU_O3_FETCH_HH__
42 #define __CPU_O3_FETCH_HH__
43 
44 #include "arch/decoder.hh"
45 #include "arch/utility.hh"
46 #include "base/statistics.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/pc_event.hh"
49 #include "cpu/pred/bpred_unit.hh"
50 #include "cpu/timebuf.hh"
51 #include "cpu/translation.hh"
52 #include "enums/FetchPolicy.hh"
53 #include "mem/packet.hh"
54 #include "mem/port.hh"
55 #include "sim/eventq.hh"
56 #include "sim/probe/probe.hh"
57 
58 struct DerivO3CPUParams;
59 template <class Impl>
60 class FullO3CPU;
61 
70 template <class Impl>
72 {
73  public:
75  typedef typename Impl::CPUPol CPUPol;
76  typedef typename Impl::DynInst DynInst;
77  typedef typename Impl::DynInstPtr DynInstPtr;
78  typedef typename Impl::O3CPU O3CPU;
79 
81  typedef typename CPUPol::FetchStruct FetchStruct;
82  typedef typename CPUPol::TimeStruct TimeStruct;
83 
86 
90  class IcachePort : public RequestPort
91  {
92  protected:
95 
96  public:
99  : RequestPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
100  { }
101 
102  protected:
103 
106  virtual bool recvTimingResp(PacketPtr pkt);
107 
109  virtual void recvReqRetry();
110  };
111 
113  {
114  protected:
116 
117  public:
119  : fetch(_fetch)
120  {}
121 
122  void
124  {}
125 
126  void
127  finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
129  {
130  assert(mode == BaseTLB::Execute);
131  fetch->finishTranslation(fault, req);
132  delete this;
133  }
134  };
135 
136  private:
137  /* Event to delay delivery of a fetch translation result in case of
138  * a fault and the nop to carry the fault cannot be generated
139  * immediately */
141  {
142  private:
146 
147  public:
149  : fetch(_fetch), req(nullptr)
150  {}
151 
152  void setFault(Fault _fault)
153  {
154  fault = _fault;
155  }
156 
157  void setReq(const RequestPtr &_req)
158  {
159  req = _req;
160  }
161 
163  void process()
164  {
165  assert(fetch->numInst < fetch->fetchWidth);
166  fetch->finishTranslation(fault, req);
167  }
168 
169  const char *description() const
170  {
171  return "FullO3CPU FetchFinishTranslation";
172  }
173  };
174 
175  public:
179  enum FetchStatus {
182  };
183 
198  };
199 
200  private:
203 
205  ThreadStatus fetchStatus[Impl::MaxThreads];
206 
208  FetchPolicy fetchPolicy;
209 
212 
217 
218  public:
220  DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
221 
223  std::string name() const;
224 
225 
227  void regProbePoints();
228 
230  void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
231 
234 
237 
239  void startupStage();
240 
242  void clearStates(ThreadID tid);
243 
245  void recvReqRetry();
246 
249 
251  void drainResume();
252 
254  void drainSanityCheck() const;
255 
257  bool isDrained() const;
258 
260  void takeOverFrom();
261 
271  void drainStall(ThreadID tid);
272 
274  void wakeFromQuiesce();
275 
277  void deactivateThread(ThreadID tid);
278  private:
280  void resetStage();
281 
285  inline void switchToActive();
286 
290  inline void switchToInactive();
291 
302 
314  bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
315  void finishTranslation(const Fault &fault, const RequestPtr &mem_req);
316 
317 
320  bool
322  {
323  return interruptPending;
324  }
325 
327  inline void doSquash(const TheISA::PCState &newPC,
328  const DynInstPtr squashInst, ThreadID tid);
329 
334  void squashFromDecode(const TheISA::PCState &newPC,
335  const DynInstPtr squashInst,
336  const InstSeqNum seq_num, ThreadID tid);
337 
339  bool checkStall(ThreadID tid) const;
340 
344 
345  public:
350  void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
351  DynInstPtr squashInst, ThreadID tid);
352 
356  void tick();
357 
362 
368  void fetch(bool &status_change);
369 
372  {
373  return (addr & ~(fetchBufferMask));
374  }
375 
377  TheISA::Decoder *decoder[Impl::MaxThreads];
378 
380 
381  private:
382  DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
383  StaticInstPtr curMacroop, TheISA::PCState thisPC,
384  TheISA::PCState nextPC, bool trace);
385 
388 
391 
393  ThreadID iqCount();
394 
396  ThreadID lsqCount();
397 
401 
404 
406  void profileStall(ThreadID tid);
407 
408  private:
411 
414 
417 
420 
423 
426 
427  //Might be annoying how this name is different than the queue.
430 
433 
434  TheISA::PCState pc[Impl::MaxThreads];
435 
436  Addr fetchOffset[Impl::MaxThreads];
437 
438  StaticInstPtr macroop[Impl::MaxThreads];
439 
441  bool delayedCommit[Impl::MaxThreads];
442 
444  RequestPtr memReq[Impl::MaxThreads];
445 
450 
452  int numInst;
453 
455  struct Stalls {
456  bool decode;
457  bool drain;
458  };
459 
461  Stalls stalls[Impl::MaxThreads];
462 
465 
468 
471 
474 
476  unsigned fetchWidth;
477 
479  unsigned decodeWidth;
480 
483 
486 
489 
491  unsigned int cacheBlkSize;
492 
496  unsigned fetchBufferSize;
497 
500 
502  uint8_t *fetchBuffer[Impl::MaxThreads];
503 
505  Addr fetchBufferPC[Impl::MaxThreads];
506 
508  unsigned fetchQueueSize;
509 
512 
514  bool fetchBufferValid[Impl::MaxThreads];
515 
517  int instSize;
518 
520  Counter lastIcacheStall[Impl::MaxThreads];
521 
524 
527 
530 
533 
538 
541 
543  bool issuePipelinedIfetch[Impl::MaxThreads];
544 
547 
548  protected:
549  struct FetchStatGroup : public Stats::Group
550  {
552  // @todo: Consider making these
553  // vectors and tracking on a per thread basis.
606  } fetchStats;
607 };
608 
609 #endif //__CPU_O3_FETCH_HH__
DefaultFetch::FetchStatGroup::cycles
Stats::Scalar cycles
Stat for total number of cycles spent fetching.
Definition: fetch.hh:563
DefaultFetch::FetchStruct
CPUPol::FetchStruct FetchStruct
Typedefs from the CPU policy.
Definition: fetch.hh:81
DefaultFetch::switchToActive
void switchToActive()
Changes the status of this stage to active, and indicates this to the CPU.
Definition: fetch_impl.hh:486
DefaultFetch::FetchStatGroup::pendingQuiesceStallCycles
Stats::Scalar pendingQuiesceStallCycles
Total number of stall cycles caused by pending quiesce instructions.
Definition: fetch.hh:585
DefaultFetch::macroop
StaticInstPtr macroop[Impl::MaxThreads]
Definition: fetch.hh:438
FullO3CPU
FullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time ...
Definition: cpu.hh:93
DefaultFetch::FetchTranslation::FetchTranslation
FetchTranslation(DefaultFetch< Impl > *_fetch)
Definition: fetch.hh:118
DefaultFetch::FinishTranslationEvent::setReq
void setReq(const RequestPtr &_req)
Definition: fetch.hh:157
DefaultFetch::getFetchingThread
ThreadID getFetchingThread()
Returns the appropriate thread to fetch, given the fetch policy.
Definition: fetch_impl.hh:1414
DefaultFetch::commitToFetchDelay
Cycles commitToFetchDelay
Commit to fetch delay.
Definition: fetch.hh:473
DefaultFetch::Stalls::decode
bool decode
Definition: fetch.hh:456
DefaultFetch::FinishTranslationEvent::fault
Fault fault
Definition: fetch.hh:144
DefaultFetch::fetchBufferAlignPC
Addr fetchBufferAlignPC(Addr addr)
Align a PC to the start of a fetch buffer block.
Definition: fetch.hh:371
DefaultFetch::FetchStatGroup::tlbSquashes
Stats::Scalar tlbSquashes
Total number of outstanding tlb accesses that were dropped due to a squash.
Definition: fetch.hh:597
DefaultFetch::switchToInactive
void switchToInactive()
Changes the status of this stage to inactive, and indicates this to the CPU.
Definition: fetch_impl.hh:499
DefaultFetch::IcacheAccessComplete
@ IcacheAccessComplete
Definition: fetch.hh:196
DefaultFetch::finishTranslationEvent
FinishTranslationEvent finishTranslationEvent
Event used to delay fault generation of translation faults.
Definition: fetch.hh:546
DefaultFetch::FetchStatGroup::predictedBranches
Stats::Scalar predictedBranches
Stat for total number of predicted branches.
Definition: fetch.hh:561
DefaultFetch::QuiescePending
@ QuiescePending
Definition: fetch.hh:192
ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:227
DefaultFetch::fetchOffset
Addr fetchOffset[Impl::MaxThreads]
Definition: fetch.hh:436
DefaultFetch::FetchStatus
FetchStatus
Overall fetch status.
Definition: fetch.hh:179
ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:52
DefaultFetch::O3CPU
Impl::O3CPU O3CPU
Definition: fetch.hh:78
DefaultFetch::IcacheWaitResponse
@ IcacheWaitResponse
Definition: fetch.hh:194
DefaultFetch::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: fetch_impl.hh:457
DefaultFetch::FetchStatGroup::pendingTrapStallCycles
Stats::Scalar pendingTrapStallCycles
Total number of stall cycles caused by pending traps.
Definition: fetch.hh:582
DefaultFetch::regProbePoints
void regProbePoints()
Registers probes.
Definition: fetch_impl.hh:157
BaseTLB::Mode
Mode
Definition: tlb.hh:57
ProbePointArg< DynInstPtr >
DefaultFetch::Active
@ Active
Definition: fetch.hh:180
DefaultFetch::fetchStats
DefaultFetch::FetchStatGroup fetchStats
DefaultFetch::NoGoodAddr
@ NoGoodAddr
Definition: fetch.hh:197
DefaultFetch::Blocked
@ Blocked
Definition: fetch.hh:189
DefaultFetch::fetchPolicy
FetchPolicy fetchPolicy
Fetch policy.
Definition: fetch.hh:208
DefaultFetch::squashFromDecode
void squashFromDecode(const TheISA::PCState &newPC, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid)
Squashes a specific thread and resets the PC.
Definition: fetch_impl.hh:778
DefaultFetch::decodeWidth
unsigned decodeWidth
The width of decode in instructions.
Definition: fetch.hh:479
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:82
DefaultFetch::fetchBufferValid
bool fetchBufferValid[Impl::MaxThreads]
Whether or not the fetch buffer data is valid.
Definition: fetch.hh:514
DefaultFetch::cacheBlkSize
unsigned int cacheBlkSize
Cache block size.
Definition: fetch.hh:491
DefaultFetch::fetchBufferPC
Addr fetchBufferPC[Impl::MaxThreads]
The PC of the first instruction loaded into the fetch buffer.
Definition: fetch.hh:505
DefaultFetch::FetchStatGroup::cacheLines
Stats::Scalar cacheLines
Stat for total number of fetched cache lines.
Definition: fetch.hh:589
DefaultFetch::FetchStatGroup::branchRate
Stats::Formula branchRate
Number of branch fetches per cycle.
Definition: fetch.hh:603
DefaultFetch::fromIEW
TimeBuffer< TimeStruct >::wire fromIEW
Wire to get iew's information from backwards time buffer.
Definition: fetch.hh:422
DefaultFetch::deactivateThread
void deactivateThread(ThreadID tid)
For priority-based fetch policies, need to keep update priorityList.
Definition: fetch_impl.hh:512
DefaultFetch::FetchTranslation::markDelayed
void markDelayed()
Signal that the translation has been delayed due to a hw page table walk.
Definition: fetch.hh:123
DefaultFetch::numFetchingThreads
ThreadID numFetchingThreads
Number of threads that are actively fetching.
Definition: fetch.hh:529
DefaultFetch::Fetching
@ Fetching
Definition: fetch.hh:190
DefaultFetch::FetchStatGroup::noActiveThreadStallCycles
Stats::Scalar noActiveThreadStallCycles
Total number of stall cycles caused by no active threads to run.
Definition: fetch.hh:580
DefaultFetch::FetchStatGroup
Definition: fetch.hh:549
DefaultFetch::tick
void tick()
Ticks the fetch stage, processing all inputs signals and fetching as many instructions as possible.
Definition: fetch_impl.hh:862
DefaultFetch::Running
@ Running
Definition: fetch.hh:186
TimeBuffer< TimeStruct >
DefaultFetch::decoder
TheISA::Decoder * decoder[Impl::MaxThreads]
The decoder.
Definition: fetch.hh:377
DefaultFetch::roundRobin
ThreadID roundRobin()
Returns the appropriate thread to fetch using a round robin policy.
Definition: fetch_impl.hh:1450
DefaultFetch::wroteToTimeBuffer
bool wroteToTimeBuffer
Variable that tracks if fetch has written to the time buffer this cycle.
Definition: fetch.hh:449
DefaultFetch::instSize
int instSize
Size of instructions.
Definition: fetch.hh:517
DefaultFetch::wakeFromQuiesce
void wakeFromQuiesce()
Tells fetch to wake up from a quiesce instruction.
Definition: fetch_impl.hh:476
DefaultFetch::pipelineIcacheAccesses
void pipelineIcacheAccesses(ThreadID tid)
Pipeline the next I-cache access to the current one.
Definition: fetch_impl.hh:1561
packet.hh
DefaultFetch::resetStage
void resetStage()
Reset this pipeline stage.
Definition: fetch_impl.hh:319
DefaultFetch::memReq
RequestPtr memReq[Impl::MaxThreads]
Memory request used to access cache.
Definition: fetch.hh:444
DefaultFetch::FetchStatGroup::squashCycles
Stats::Scalar squashCycles
Stat for total number of cycles spent squashing.
Definition: fetch.hh:565
DefaultFetch::retryTid
ThreadID retryTid
The thread that is waiting on the cache to tell fetch to retry.
Definition: fetch.hh:488
timebuf.hh
Stats::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:2533
DefaultFetch::doSquash
void doSquash(const TheISA::PCState &newPC, const DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
Definition: fetch_impl.hh:726
DefaultFetch::lsqCount
ThreadID lsqCount()
Returns the appropriate thread to fetch using the LSQ count policy.
Definition: fetch_impl.hh:1517
Counter
int64_t Counter
Statistics counter type.
Definition: types.hh:58
DefaultFetch::isDrained
bool isDrained() const
Has the stage drained?
Definition: fetch_impl.hh:426
DefaultFetch::icachePort
IcachePort icachePort
Instruction port.
Definition: fetch.hh:540
DefaultFetch::FetchTranslation
Definition: fetch.hh:112
DefaultFetch::fromDecode
TimeBuffer< TimeStruct >::wire fromDecode
Wire to get decode's information from backwards time buffer.
Definition: fetch.hh:416
DefaultFetch::FetchStatGroup::insts
Stats::Scalar insts
Stat for total number of fetched instructions.
Definition: fetch.hh:557
DefaultFetch::fetchCacheLine
bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
Fetches the cache line that contains the fetch PC.
Definition: fetch_impl.hh:569
DefaultFetch::FetchStatGroup::miscStallCycles
Stats::Scalar miscStallCycles
Total number of cycles spent in any other state.
Definition: fetch.hh:576
DefaultFetch::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: fetch_impl.hh:272
DefaultFetch::branchCount
ThreadID branchCount()
Returns the appropriate thread to fetch using the branch count policy.
Definition: fetch_impl.hh:1553
DefaultFetch::name
std::string name() const
Returns the name of fetch.
Definition: fetch_impl.hh:150
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
translation.hh
DefaultFetch::IcachePort::IcachePort
IcachePort(DefaultFetch< Impl > *_fetch, FullO3CPU< Impl > *_cpu)
Default constructor.
Definition: fetch.hh:98
Event
Definition: eventq.hh:246
DefaultFetch::issuePipelinedIfetch
bool issuePipelinedIfetch[Impl::MaxThreads]
Set to true if a pipelined I-cache request should be issued.
Definition: fetch.hh:543
DefaultFetch::recvReqRetry
void recvReqRetry()
Handles retrying the fetch access.
Definition: fetch_impl.hh:1383
DefaultFetch::decodeToFetchDelay
Cycles decodeToFetchDelay
Decode to fetch delay.
Definition: fetch.hh:464
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
MipsISA::vaddr
vaddr
Definition: pra_constants.hh:275
DefaultFetch::setFetchQueue
void setFetchQueue(TimeBuffer< FetchStruct > *fq_ptr)
Sets pointer to time buffer used to communicate to the next stage.
Definition: fetch_impl.hh:279
statistics.hh
DefaultFetch::TimeStruct
CPUPol::TimeStruct TimeStruct
Definition: fetch.hh:82
DefaultFetch::iewToFetchDelay
Cycles iewToFetchDelay
IEW to fetch delay.
Definition: fetch.hh:470
DefaultFetch::startupStage
void startupStage()
Initialize stage.
Definition: fetch_impl.hh:287
DefaultFetch::FinishTranslationEvent
Definition: fetch.hh:140
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
BPredUnit
Basically a wrapper class to hold both the branch predictor and the BTB.
Definition: bpred_unit.hh:62
port.hh
DefaultFetch::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
Time buffer interface.
Definition: fetch.hh:413
DefaultFetch::renameToFetchDelay
Cycles renameToFetchDelay
Rename to fetch delay.
Definition: fetch.hh:467
BaseTLB::Translation
Definition: tlb.hh:59
DefaultFetch::FinishTranslationEvent::description
const char * description() const
Return a C string describing the event.
Definition: fetch.hh:169
DefaultFetch::Stalls::drain
bool drain
Definition: fetch.hh:457
DefaultFetch::FinishTranslationEvent::FinishTranslationEvent
FinishTranslationEvent(DefaultFetch< Impl > *_fetch)
Definition: fetch.hh:148
DefaultFetch::cacheBlocked
bool cacheBlocked
Is the cache blocked? If so no threads can access it.
Definition: fetch.hh:482
DefaultFetch::checkSignalsAndUpdate
bool checkSignalsAndUpdate(ThreadID tid)
Checks all input signals and updates the status as necessary.
Definition: fetch_impl.hh:964
DefaultFetch::FetchStatGroup::branches
Stats::Scalar branches
Total number of fetched branches.
Definition: fetch.hh:559
DefaultFetch::Stalls
Source of possible stalls.
Definition: fetch.hh:455
DefaultFetch::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: fetch_impl.hh:408
RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:74
DefaultFetch::FetchStatGroup::blockedCycles
Stats::Scalar blockedCycles
Total number of cycles spent blocked.
Definition: fetch.hh:574
DefaultFetch::FetchStatGroup::rate
Stats::Formula rate
Number of instruction fetched per cycle.
Definition: fetch.hh:605
InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:37
DefaultFetch::buildInst
DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, TheISA::PCState thisPC, TheISA::PCState nextPC, bool trace)
Definition: fetch_impl.hh:1069
DefaultFetch::FetchStatGroup::nisnDist
Stats::Distribution nisnDist
Distribution of number of instructions fetched each cycle.
Definition: fetch.hh:599
DefaultFetch::IcachePort
IcachePort class for instruction fetch.
Definition: fetch.hh:90
DefaultFetch::drainStall
void drainStall(ThreadID tid)
Stall the fetch stage after reaching a safe drain point.
Definition: fetch_impl.hh:466
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:106
Stats::Distribution
A simple distribution stat.
Definition: statistics.hh:2617
DefaultFetch::updateFetchStatus
FetchStatus updateFetchStatus()
Updates overall fetch stage status; to be called at the end of each cycle.
Definition: fetch_impl.hh:808
DefaultFetch::ppFetchRequestSent
ProbePointArg< RequestPtr > * ppFetchRequestSent
To probe when a fetch request is successfully sent.
Definition: fetch.hh:216
DefaultFetch
DefaultFetch class handles both single threaded and SMT fetch.
Definition: fetch.hh:71
DefaultFetch::delayedCommit
bool delayedCommit[Impl::MaxThreads]
Can the fetch stage redirect from an interrupt on this instruction?
Definition: fetch.hh:441
DefaultFetch::FetchStatGroup::pendingDrainCycles
Stats::Scalar pendingDrainCycles
Total number of cycles spent in waiting for drains.
Definition: fetch.hh:578
DefaultFetch::ppFetch
ProbePointArg< DynInstPtr > * ppFetch
Probe points.
Definition: fetch.hh:214
DefaultFetch::lookupAndUpdateNextPC
bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc)
Looks up in the branch predictor to see if the next PC should be either next PC+=MachInst or a branch...
Definition: fetch_impl.hh:523
DefaultFetch::toDecode
TimeBuffer< FetchStruct >::wire toDecode
Wire used to write any information heading to decode.
Definition: fetch.hh:429
DefaultFetch::fetchWidth
unsigned fetchWidth
The width of fetch in instructions.
Definition: fetch.hh:476
DefaultFetch::Squashing
@ Squashing
Definition: fetch.hh:188
DefaultFetch::FinishTranslationEvent::setFault
void setFault(Fault _fault)
Definition: fetch.hh:152
DefaultFetch::FetchStatGroup::idleCycles
Stats::Scalar idleCycles
Stat for total number of cycles spent blocked due to other stages in the pipeline.
Definition: fetch.hh:572
DefaultFetch::MachInst
TheISA::MachInst MachInst
Typedefs from ISA.
Definition: fetch.hh:85
DefaultFetch::FetchStatGroup::FetchStatGroup
FetchStatGroup(O3CPU *cpu, DefaultFetch *fetch)
Definition: fetch_impl.hh:167
DefaultFetch::CPUPol
Impl::CPUPol CPUPol
Typedefs from Impl.
Definition: fetch.hh:75
DefaultFetch::priorityList
std::list< ThreadID > priorityList
List that has the threads organized by priority.
Definition: fetch.hh:211
DefaultFetch::FinishTranslationEvent::process
void process()
Process the delayed finish translation.
Definition: fetch.hh:163
DefaultFetch::fetch
void fetch(bool &status_change)
Does the actual fetching of instructions and passing them on to the next stage.
Definition: fetch_impl.hh:1121
DefaultFetch::interruptPending
bool interruptPending
Checks if there is an interrupt pending.
Definition: fetch.hh:537
DefaultFetch::IcachePort::recvReqRetry
virtual void recvReqRetry()
Handles doing a retry of a failed fetch.
Definition: fetch_impl.hh:1653
DefaultFetch::profileStall
void profileStall(ThreadID tid)
Profile the reasons of fetch stall.
Definition: fetch_impl.hh:1591
DefaultFetch::numThreads
ThreadID numThreads
Number of threads.
Definition: fetch.hh:526
DefaultFetch::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: fetch_impl.hh:299
pc_event.hh
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
DefaultFetch::drainResume
void drainResume()
Resume after a drain.
Definition: fetch_impl.hh:398
bpred_unit.hh
DefaultFetch::finishTranslation
void finishTranslation(const Fault &fault, const RequestPtr &mem_req)
Definition: fetch_impl.hh:619
DefaultFetch::FinishTranslationEvent::fetch
DefaultFetch< Impl > * fetch
Definition: fetch.hh:143
DefaultFetch::fetchQueueSize
unsigned fetchQueueSize
The size of the fetch queue in micro-ops.
Definition: fetch.hh:508
Stats::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:3037
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
DefaultFetch::FetchStatGroup::tlbCycles
Stats::Scalar tlbCycles
Stat for total number of cycles spent waiting for translation.
Definition: fetch.hh:567
std::deque< DynInstPtr >
DefaultFetch::FetchStatGroup::icacheSquashes
Stats::Scalar icacheSquashes
Total number of outstanding icache accesses that were dropped due to a squash.
Definition: fetch.hh:593
DefaultFetch::TrapPending
@ TrapPending
Definition: fetch.hh:191
Stats::Group
Statistics container.
Definition: group.hh:83
DefaultFetch::FetchStatGroup::idleRate
Stats::Formula idleRate
Rate of how often fetch was idle.
Definition: fetch.hh:601
DefaultFetch::fromRename
TimeBuffer< TimeStruct >::wire fromRename
Wire to get rename's information from backwards time buffer.
Definition: fetch.hh:419
DefaultFetch::Inactive
@ Inactive
Definition: fetch.hh:181
addr
ip6_addr_t addr
Definition: inet.hh:423
DefaultFetch::fetchBufferMask
Addr fetchBufferMask
Mask to align a fetch address to a fetch buffer boundary.
Definition: fetch.hh:499
DefaultFetch::ThreadStatus
ThreadStatus
Individual thread status.
Definition: fetch.hh:185
Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
DefaultFetch::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *time_buffer)
Sets the main backwards communication time buffer pointer.
Definition: fetch_impl.hh:259
DefaultFetch::IcacheWaitRetry
@ IcacheWaitRetry
Definition: fetch.hh:195
DefaultFetch::ItlbWait
@ ItlbWait
Definition: fetch.hh:193
DefaultFetch::threadFetched
ThreadID threadFetched
Thread ID being fetched.
Definition: fetch.hh:532
DefaultFetch::FetchStatGroup::icacheWaitRetryStallCycles
Stats::Scalar icacheWaitRetryStallCycles
Total number of stall cycles caused by I-cache wait retrys.
Definition: fetch.hh:587
DefaultFetch::processCacheCompletion
void processCacheCompletion(PacketPtr pkt)
Processes cache completion event.
Definition: fetch_impl.hh:354
DefaultFetch::pc
TheISA::PCState pc[Impl::MaxThreads]
Definition: fetch.hh:434
RefCountingPtr< StaticInst >
DefaultFetch::Idle
@ Idle
Definition: fetch.hh:187
DefaultFetch::fetchQueue
std::deque< DynInstPtr > fetchQueue[Impl::MaxThreads]
Queue of fetched instructions.
Definition: fetch.hh:511
DefaultFetch::iqCount
ThreadID iqCount()
Returns the appropriate thread to fetch using the IQ count policy.
Definition: fetch_impl.hh:1480
DefaultFetch::DynInst
Impl::DynInst DynInst
Definition: fetch.hh:76
DefaultFetch::cpu
O3CPU * cpu
Pointer to the O3CPU.
Definition: fetch.hh:410
DefaultFetch::DefaultFetch
DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
DefaultFetch constructor.
Definition: fetch_impl.hh:78
DefaultFetch::FetchTranslation::fetch
DefaultFetch< Impl > * fetch
Definition: fetch.hh:115
DefaultFetch::FetchTranslation::finish
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Definition: fetch.hh:127
DefaultFetch::branchPred
BPredUnit * branchPred
BPredUnit.
Definition: fetch.hh:432
DefaultFetch::numInst
int numInst
Tracks how many instructions has been fetched this cycle.
Definition: fetch.hh:452
std::list< ThreadID >
DefaultFetch::fetchBuffer
uint8_t * fetchBuffer[Impl::MaxThreads]
The fetch data that is being fetched and buffered.
Definition: fetch.hh:502
DefaultFetch::_status
FetchStatus _status
Fetch status.
Definition: fetch.hh:202
DefaultFetch::IcachePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Timing version of receive.
Definition: fetch_impl.hh:1640
probe.hh
DefaultFetch::stalls
Stalls stalls[Impl::MaxThreads]
Tracks which stages are telling fetch to stall.
Definition: fetch.hh:461
DefaultFetch::retryPkt
PacketPtr retryPkt
The packet that is waiting to be retried.
Definition: fetch.hh:485
DefaultFetch::checkStall
bool checkStall(ThreadID tid) const
Checks if a thread is stalled.
Definition: fetch_impl.hh:793
BaseTLB::Execute
@ Execute
Definition: tlb.hh:57
DefaultFetch::FetchStatGroup::icacheStallCycles
Stats::Scalar icacheStallCycles
Stat for total number of cycles stalled due to an icache miss.
Definition: fetch.hh:555
DefaultFetch::lastIcacheStall
Counter lastIcacheStall[Impl::MaxThreads]
Icache stall statistics.
Definition: fetch.hh:520
DefaultFetch::FinishTranslationEvent::req
RequestPtr req
Definition: fetch.hh:145
DefaultFetch::checkInterrupt
bool checkInterrupt(Addr pc)
Check if an interrupt is pending and that we need to handle.
Definition: fetch.hh:321
DefaultFetch::fetchStatus
ThreadStatus fetchStatus[Impl::MaxThreads]
Per-thread status.
Definition: fetch.hh:205
DefaultFetch::activeThreads
std::list< ThreadID > * activeThreads
List of Active Threads.
Definition: fetch.hh:523
DefaultFetch::IcachePort::fetch
DefaultFetch< Impl > * fetch
Pointer to fetch.
Definition: fetch.hh:94
DefaultFetch::getInstPort
RequestPort & getInstPort()
Definition: fetch.hh:379
DefaultFetch::squash
void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid)
Squashes a specific thread and resets the PC.
Definition: fetch_impl.hh:848
DefaultFetch::fetchBufferSize
unsigned fetchBufferSize
The size of the fetch buffer in bytes.
Definition: fetch.hh:496
DefaultFetch::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's information from backwards time buffer.
Definition: fetch.hh:425
DefaultFetch::DynInstPtr
Impl::DynInstPtr DynInstPtr
Definition: fetch.hh:77
eventq.hh

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