gem5  v20.1.0.0
cortex_a76.cc
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27 
28 #include "arch/arm/fastmodel/CortexA76/cortex_a76.hh"
29 
30 #include "arch/arm/fastmodel/iris/cpu.hh"
31 #include "base/logging.hh"
32 #include "dev/arm/base_gic.hh"
33 #include "sim/core.hh"
34 #include "systemc/tlm_bridge/gem5_to_tlm.hh"
35 
36 namespace FastModel
37 {
38 
39 void
40 CortexA76::initState()
41 {
42  for (auto *tc : threadContexts)
43  tc->setMiscRegNoEffect(ArmISA::MISCREG_CNTFRQ_EL0, params().cntfrq);
44 }
45 
46 void
47 CortexA76::setCluster(CortexA76Cluster *_cluster, int _num)
48 {
49  cluster = _cluster;
50  num = _num;
51 
52  set_evs_param("CFGEND", params().CFGEND);
53  set_evs_param("CFGTE", params().CFGTE);
54  set_evs_param("CRYPTODISABLE", params().CRYPTODISABLE);
55  set_evs_param("RVBARADDR", params().RVBARADDR);
56  set_evs_param("VINITHI", params().VINITHI);
57  set_evs_param("enable_trace_special_hlt_imm16",
58  params().enable_trace_special_hlt_imm16);
59  set_evs_param("l2cache-hit_latency", params().l2cache_hit_latency);
60  set_evs_param("l2cache-maintenance_latency",
61  params().l2cache_maintenance_latency);
62  set_evs_param("l2cache-miss_latency", params().l2cache_miss_latency);
63  set_evs_param("l2cache-read_access_latency",
64  params().l2cache_read_access_latency);
65  set_evs_param("l2cache-read_latency", params().l2cache_read_latency);
66  set_evs_param("l2cache-size", params().l2cache_size);
67  set_evs_param("l2cache-snoop_data_transfer_latency",
68  params().l2cache_snoop_data_transfer_latency);
69  set_evs_param("l2cache-snoop_issue_latency",
70  params().l2cache_snoop_issue_latency);
71  set_evs_param("l2cache-write_access_latency",
72  params().l2cache_write_access_latency);
73  set_evs_param("l2cache-write_latency", params().l2cache_write_latency);
74  set_evs_param("max_code_cache_mb", params().max_code_cache_mb);
75  set_evs_param("min_sync_level", params().min_sync_level);
76  set_evs_param("semihosting-A32_HLT", params().semihosting_A32_HLT);
77  set_evs_param("semihosting-A64_HLT", params().semihosting_A64_HLT);
78  set_evs_param("semihosting-ARM_SVC", params().semihosting_ARM_SVC);
79  set_evs_param("semihosting-T32_HLT", params().semihosting_T32_HLT);
80  set_evs_param("semihosting-Thumb_SVC", params().semihosting_Thumb_SVC);
81  set_evs_param("semihosting-cmd_line", params().semihosting_cmd_line);
82  set_evs_param("semihosting-cwd", params().semihosting_cwd);
83  set_evs_param("semihosting-enable", params().semihosting_enable);
84  set_evs_param("semihosting-heap_base", params().semihosting_heap_base);
85  set_evs_param("semihosting-heap_limit", params().semihosting_heap_limit);
86  set_evs_param("semihosting-stack_base", params().semihosting_stack_base);
87  set_evs_param("semihosting-stack_limit", params().semihosting_stack_limit);
88  set_evs_param("trace_special_hlt_imm16", params().trace_special_hlt_imm16);
89  set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
90 }
91 
92 Port &
93 CortexA76::getPort(const std::string &if_name, PortID idx)
94 {
95  if (if_name == "redistributor")
96  return cluster->getEvs()->gem5_getPort(if_name, num);
97  else
98  return Base::getPort(if_name, idx);
99 }
100 
101 CortexA76Cluster::CortexA76Cluster(Params &p) :
102  SimObject(&p), _params(p), cores(p.cores), evs(p.evs)
103 {
104  for (int i = 0; i < p.cores.size(); i++)
105  p.cores[i]->setCluster(this, i);
106 
107  sc_core::sc_attr_base *base;
108 
109  base = evs->get_attribute(Iris::Gem5CpuClusterAttributeName);
110  auto *gem5_cluster_attr =
111  dynamic_cast<sc_core::sc_attribute<CortexA76Cluster *> *>(base);
112  panic_if(base && !gem5_cluster_attr,
113  "The EVS gem5 CPU cluster attribute was not of type "
114  "sc_attribute<FastModel::CortexA76Cluster *>.");
115  if (gem5_cluster_attr)
116  gem5_cluster_attr->value = this;
117 
118  set_evs_param("core.BROADCASTATOMIC", p.BROADCASTATOMIC);
119  set_evs_param("core.BROADCASTCACHEMAINT", p.BROADCASTCACHEMAINT);
120  set_evs_param("core.BROADCASTOUTER", p.BROADCASTOUTER);
121  set_evs_param("core.BROADCASTPERSIST", p.BROADCASTPERSIST);
122  set_evs_param("core.CLUSTER_ID", p.CLUSTER_ID);
123  set_evs_param("core.GICDISABLE", p.GICDISABLE);
124  set_evs_param("core.cpi_div", p.cpi_div);
125  set_evs_param("core.cpi_mul", p.cpi_mul);
126  set_evs_param("core.dcache-hit_latency", p.dcache_hit_latency);
127  set_evs_param("core.dcache-maintenance_latency",
128  p.dcache_maintenance_latency);
129  set_evs_param("core.dcache-miss_latency", p.dcache_miss_latency);
130  set_evs_param("core.dcache-prefetch_enabled",
131  p.dcache_prefetch_enabled);
132  set_evs_param("core.dcache-read_access_latency",
133  p.dcache_read_access_latency);
134  set_evs_param("core.dcache-read_latency", p.dcache_read_latency);
135  set_evs_param("core.dcache-snoop_data_transfer_latency",
136  p.dcache_snoop_data_transfer_latency);
137  set_evs_param("core.dcache-state_modelled", p.dcache_state_modelled);
138  set_evs_param("core.dcache-write_access_latency",
139  p.dcache_write_access_latency);
140  set_evs_param("core.dcache-write_latency", p.dcache_write_latency);
141  set_evs_param("core.default_opmode", p.default_opmode);
142  set_evs_param("core.diagnostics", p.diagnostics);
143  set_evs_param("core.enable_simulation_performance_optimizations",
144  p.enable_simulation_performance_optimizations);
145  set_evs_param("core.ext_abort_device_read_is_sync",
146  p.ext_abort_device_read_is_sync);
147  set_evs_param("core.ext_abort_device_write_is_sync",
148  p.ext_abort_device_write_is_sync);
149  set_evs_param("core.ext_abort_so_read_is_sync",
150  p.ext_abort_so_read_is_sync);
151  set_evs_param("core.ext_abort_so_write_is_sync",
152  p.ext_abort_so_write_is_sync);
153  set_evs_param("core.gicv3.cpuintf-mmap-access-level",
154  p.gicv3_cpuintf_mmap_access_level);
155  set_evs_param("core.has_peripheral_port", p.has_peripheral_port);
156  set_evs_param("core.has_statistical_profiling",
157  p.has_statistical_profiling);
158  set_evs_param("core.icache-hit_latency", p.icache_hit_latency);
159  set_evs_param("core.icache-maintenance_latency",
160  p.icache_maintenance_latency);
161  set_evs_param("core.icache-miss_latency", p.icache_miss_latency);
162  set_evs_param("core.icache-prefetch_enabled",
163  p.icache_prefetch_enabled);
164  set_evs_param("core.icache-read_access_latency",
165  p.icache_read_access_latency);
166  set_evs_param("core.icache-read_latency", p.icache_read_latency);
167  set_evs_param("core.icache-state_modelled", p.icache_state_modelled);
168  set_evs_param("core.l3cache-hit_latency", p.l3cache_hit_latency);
169  set_evs_param("core.l3cache-maintenance_latency",
170  p.l3cache_maintenance_latency);
171  set_evs_param("core.l3cache-miss_latency", p.l3cache_miss_latency);
172  set_evs_param("core.l3cache-read_access_latency",
173  p.l3cache_read_access_latency);
174  set_evs_param("core.l3cache-read_latency", p.l3cache_read_latency);
175  set_evs_param("core.l3cache-size", p.l3cache_size);
176  set_evs_param("core.l3cache-snoop_data_transfer_latency",
177  p.l3cache_snoop_data_transfer_latency);
178  set_evs_param("core.l3cache-snoop_issue_latency",
179  p.l3cache_snoop_issue_latency);
180  set_evs_param("core.l3cache-write_access_latency",
181  p.l3cache_write_access_latency);
182  set_evs_param("core.l3cache-write_latency", p.l3cache_write_latency);
183  set_evs_param("core.pchannel_treat_simreset_as_poreset",
184  p.pchannel_treat_simreset_as_poreset);
185  set_evs_param("core.periph_address_end", p.periph_address_end);
186  set_evs_param("core.periph_address_start", p.periph_address_start);
187  set_evs_param("core.ptw_latency", p.ptw_latency);
188  set_evs_param("core.tlb_latency", p.tlb_latency);
189  set_evs_param("core.treat-dcache-cmos-to-pou-as-nop",
190  p.treat_dcache_cmos_to_pou_as_nop);
191  set_evs_param("core.walk_cache_latency", p.walk_cache_latency);
192 }
193 
194 Port &
195 CortexA76Cluster::getPort(const std::string &if_name, PortID idx)
196 {
197  if (if_name == "amba") {
198  return evs->gem5_getPort(if_name, idx);
199  } else {
200  return SimObject::getPort(if_name, idx);
201  }
202 }
203 
204 } // namespace FastModel
205 
206 FastModel::CortexA76 *
207 FastModelCortexA76Params::create()
208 {
209  return new FastModel::CortexA76(*this);
210 }
211 
212 FastModel::CortexA76Cluster *
213 FastModelCortexA76ClusterParams::create()
214 {
215  return new FastModel::CortexA76Cluster(*this);
216 }
BaseCPU::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
Definition: base.cc:402
FastModel::CortexA76Cluster::Params
FastModelCortexA76ClusterParams Params
Definition: cortex_a76.hh:96
cortex_a76.hh
FastModel::CortexA76
Definition: cortex_a76.hh:52
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
ArmISA::MISCREG_CNTFRQ_EL0
@ MISCREG_CNTFRQ_EL0
Definition: miscregs.hh:745
gem5_to_tlm.hh
base_gic.hh
sc_core::sc_attribute
Definition: sc_attr.hh:55
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:237
Iris::Gem5CpuClusterAttributeName
static const std::string Gem5CpuClusterAttributeName
Definition: cpu.hh:49
X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
FastModel::CortexA76::setCluster
void setCluster(CortexA76Cluster *_cluster, int _num)
Definition: cortex_a76.cc:47
FastModel::CortexA76::params
const Params & params()
Definition: cortex_a76.hh:62
cpu.hh
sc_core::sc_attr_base
Definition: sc_attr.hh:37
FastModel::CortexA76::cluster
CortexA76Cluster * cluster
Definition: cortex_a76.hh:59
FastModel::CortexA76::initState
void initState() override
Definition: cortex_a76.cc:40
sc_core::sc_module::gem5_getPort
virtual ::Port & gem5_getPort(const std::string &if_name, int idx=-1)
Definition: sc_module.cc:117
FastModel::CortexA76Cluster::getEvs
sc_core::sc_module * getEvs()
Definition: cortex_a76.hh:111
SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:123
FastModel::CortexA76Cluster::CortexA76Cluster
CortexA76Cluster(Params &p)
Definition: cortex_a76.cc:101
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
BaseCPU::threadContexts
std::vector< ThreadContext * > threadContexts
Definition: base.hh:252
FastModel::CortexA76::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Definition: cortex_a76.cc:93
core.hh
FastModel::CortexA76::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:122
sc_core::sc_object::get_attribute
sc_attr_base * get_attribute(const std::string &)
Definition: sc_object.cc:92
FastModel::CortexA76::num
int num
Definition: cortex_a76.hh:60
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
FastModel
Definition: amba_from_tlm_bridge.cc:32
FastModel::CortexA76Cluster::set_evs_param
void set_evs_param(const std::string &n, T val)
Definition: cortex_a76.hh:105
FastModel::CortexA76Cluster
Definition: cortex_a76.hh:93
logging.hh
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
FastModel::CortexA76Cluster::evs
sc_core::sc_module * evs
Definition: cortex_a76.hh:100
FastModel::CortexA76Cluster::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: cortex_a76.cc:195
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:92
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