gem5  v20.1.0.0
Public Member Functions | Protected Types | Protected Member Functions | Protected Attributes | List of all members
FastModel::CortexA76 Class Reference

#include <cortex_a76.hh>

Inheritance diagram for FastModel::CortexA76:
Iris::CPU< CortexA76TC > Iris::BaseCPU BaseCPU

Public Member Functions

 CortexA76 (Params &p)
void clockPeriodUpdated () override
void initState () override
template<class T >
void set_evs_param (const std::string &n, T val)
void setCluster (CortexA76Cluster *_cluster, int _num)
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
- Public Member Functions inherited from Iris::CPU< CortexA76TC >
 CPU (IrisBaseCPUParams *params, iris::IrisConnectionInterface *iris_if)
- Public Member Functions inherited from Iris::BaseCPU
 BaseCPU (BaseCPUParams *params, sc_core::sc_module *_evs)
virtual ~BaseCPU ()
PortgetDataPort () override
 Purely virtual method that returns a reference to the data port. More...
PortgetInstPort () override
 Purely virtual method that returns a reference to the instruction port. More...
void wakeup (ThreadID tid) override
Counter totalInsts () const override
Counter totalOps () const override
PortProxy::SendFunctionalFunc getSendFunctional () override
 Returns a sendFunctional delegate for use with port proxies. More...
- Public Member Functions inherited from BaseCPU
int cpuId () const
 Reads this CPU's ID. More...
uint32_t socketId () const
 Reads this CPU's Socket ID. More...
RequestorID dataRequestorId () const
 Reads this CPU's unique data requestor ID. More...
RequestorID instRequestorId () const
 Reads this CPU's unique instruction requestor ID. More...
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port on this CPU. More...
uint32_t taskId () const
 Get cpu task id. More...
void taskId (uint32_t id)
 Set cpu task id. More...
uint32_t getPid () const
void setPid (uint32_t pid)
void workItemBegin ()
void workItemEnd ()
Tick instCount ()
BaseInterruptsgetInterruptController (ThreadID tid)
void postInterrupt (ThreadID tid, int int_num, int index)
void clearInterrupt (ThreadID tid, int int_num, int index)
void clearInterrupts (ThreadID tid)
bool checkInterrupts (ThreadID tid) const
Trace::InstTracergetTracer ()
 Provide access to the tracer pointer. More...
virtual void activateContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now active. More...
virtual void suspendContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now suspended. More...
virtual void haltContext (ThreadID thread_num)
 Notify the CPU that the indicated context is now halted. More...
int findContext (ThreadContext *tc)
 Given a Thread Context pointer return the thread num. More...
virtual ThreadContextgetContext (int tn)
 Given a thread num get tho thread context for it. More...
unsigned numContexts ()
 Get the number of thread contexts available. More...
ThreadID contextToThread (ContextID cid)
 Convert ContextID to threadID. More...
const Paramsparams () const
 BaseCPU (Params *params, bool is_checker=false)
void init () override
void startup () override
void regStats () override
void regProbePoints () override
void registerThreadContexts ()
void deschedulePowerGatingEvent ()
void schedulePowerGatingEvent ()
virtual void switchOut ()
 Prepare for another CPU to take over execution. More...
virtual void takeOverFrom (BaseCPU *cpu)
 Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...
void flushTLBs ()
 Flush all TLBs in the CPU. More...
bool switchedOut () const
 Determine if the CPU is switched out. More...
virtual void verifyMemoryMode () const
 Verify that the system is in a memory mode supported by the CPU. More...
unsigned int cacheLineSize () const
 Get the cache line size of the system. More...
void serialize (CheckpointOut &cp) const override
 Serialize this object to the given output stream. More...
void unserialize (CheckpointIn &cp) override
 Reconstruct the state of this object from a checkpoint. More...
virtual void unserializeThread (CheckpointIn &cp, ThreadID tid)
 Unserialize one thread. More...
void scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
 Schedule an event that exits the simulation loops after a predefined number of instructions. More...
uint64_t getCurrentInstCount (ThreadID tid)
 Get the number of instructions executed by the specified thread on this CPU. More...
void traceFunctions (Addr pc)
void armMonitor (ThreadID tid, Addr address)
bool mwait (ThreadID tid, PacketPtr pkt)
void mwaitAtomic (ThreadID tid, ThreadContext *tc, BaseTLB *dtb)
AddressMonitorgetCpuAddrMonitor (ThreadID tid)
bool waitForRemoteGDB () const
virtual void probeInstCommit (const StaticInstPtr &inst, Addr pc)
 Helper method to trigger PMU probes for a committed instruction. More...

Protected Types

typedef FastModelCortexA76Params Params
typedef Iris::CPU< CortexA76TCBase
- Protected Types inherited from BaseCPU

Protected Member Functions

const Paramsparams ()
- Protected Member Functions inherited from Iris::BaseCPU
void clockPeriodUpdated () override
void init () override
void serializeThread (CheckpointOut &cp, ThreadID tid) const override
 Serialize a single thread. More...
- Protected Member Functions inherited from BaseCPU
void updateCycleCounters (CPUState state)
 base method keeping track of cycle progression More...
void enterPwrGating ()
ProbePoints::PMUUPtr pmuProbePoint (const char *name)
 Helper method to instantiate probe points belonging to this object. More...

Protected Attributes

const Params_params
CortexA76Clustercluster = nullptr
int num = 0
- Protected Attributes inherited from Iris::BaseCPU
- Protected Attributes inherited from BaseCPU
Tick instCnt
 Instruction count used for SPARC misc register. More...
int _cpuId
const uint32_t _socketId
 Each cpu will have a socket ID that corresponds to its physical location in the system. More...
RequestorID _instRequestorId
 instruction side request id that must be placed in all requests More...
RequestorID _dataRequestorId
 data side request id that must be placed in all requests More...
uint32_t _taskId
 An intrenal representation of a task identifier within gem5. More...
uint32_t _pid
 The current OS process ID that is executing on this processor. More...
bool _switchedOut
 Is the CPU switched out or active? More...
const unsigned int _cacheLineSize
 Cache the cache line size that we get from the system. More...
std::vector< BaseInterrupts * > interrupts
std::vector< ThreadContext * > threadContexts
Cycles previousCycle
CPUState previousState
const Cycles pwrGatingLatency
const bool powerGatingOnIdle
EventFunctionWrapper enterPwrGatingEvent
ProbePoints::PMUUPtr ppRetiredInsts
 Instruction commit probe point. More...
ProbePoints::PMUUPtr ppRetiredInstsPC
ProbePoints::PMUUPtr ppRetiredLoads
 Retired load instructions. More...
ProbePoints::PMUUPtr ppRetiredStores
 Retired store instructions. More...
ProbePoints::PMUUPtr ppRetiredBranches
 Retired branches (any type) More...
ProbePoints::PMUUPtr ppAllCycles
 CPU cycle counter even if any thread Context is suspended. More...
ProbePoints::PMUUPtr ppActiveCycles
 CPU cycle counter, only counts if any thread contexts is active. More...
ProbePointArg< bool > * ppSleeping
 ProbePoint that signals transitions of threadContexts sets. More...

Additional Inherited Members

- Public Types inherited from BaseCPU
typedef BaseCPUParams Params
- Static Public Member Functions inherited from BaseCPU
static int numSimulatedInsts ()
static int numSimulatedOps ()
static void wakeup (ThreadID tid)
static int numSimulatedCPUs ()
static Counter numSimulatedInsts ()
static Counter numSimulatedOps ()
- Public Attributes inherited from BaseCPU
ThreadID numThreads
 Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...
Stats::Scalar numCycles
Stats::Scalar numWorkItemsStarted
Stats::Scalar numWorkItemsCompleted
Cycles syscallRetryLatency
- Static Public Attributes inherited from BaseCPU
static const uint32_t invldPid = std::numeric_limits<uint32_t>::max()
 Invalid or unknown Pid. More...
static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

Detailed Description

Definition at line 52 of file cortex_a76.hh.

Member Typedef Documentation

◆ Base

Definition at line 56 of file cortex_a76.hh.

◆ Params

typedef FastModelCortexA76Params FastModel::CortexA76::Params

Definition at line 55 of file cortex_a76.hh.

Constructor & Destructor Documentation

◆ CortexA76()

FastModel::CortexA76::CortexA76 ( Params p)

Definition at line 65 of file cortex_a76.hh.

Member Function Documentation

◆ clockPeriodUpdated()

void FastModel::CortexA76::clockPeriodUpdated ( )

◆ getPort()

Port & FastModel::CortexA76::getPort ( const std::string &  if_name,
PortID  idx = InvalidPortID 

◆ initState()

void FastModel::CortexA76::initState ( )

Definition at line 40 of file

References ArmISA::MISCREG_CNTFRQ_EL0, params(), and BaseCPU::threadContexts.

◆ params()

const Params& FastModel::CortexA76::params ( )

Definition at line 62 of file cortex_a76.hh.

References _params.

Referenced by initState(), set_evs_param(), and setCluster().

◆ set_evs_param()

template<class T >
void FastModel::CortexA76::set_evs_param ( const std::string &  n,

Definition at line 122 of file cortex_a76.hh.

References cluster, ArmISA::n, params(), FastModel::CortexA76Cluster::set_evs_param(), and X86ISA::val.

Referenced by setCluster().

◆ setCluster()

void FastModel::CortexA76::setCluster ( CortexA76Cluster _cluster,
int  _num 

Definition at line 47 of file

References cluster, num, params(), and set_evs_param().

Member Data Documentation

◆ _params

const Params& FastModel::CortexA76::_params

Definition at line 57 of file cortex_a76.hh.

Referenced by params().

◆ cluster

CortexA76Cluster* FastModel::CortexA76::cluster = nullptr

Definition at line 59 of file cortex_a76.hh.

Referenced by getPort(), set_evs_param(), and setCluster().

◆ num

int FastModel::CortexA76::num = 0

Definition at line 60 of file cortex_a76.hh.

Referenced by getPort(), and setCluster().

The documentation for this class was generated from the following files:

Generated on Wed Sep 30 2020 14:02:39 for gem5 by doxygen 1.8.17