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43 #include "arch/isa.hh"
44 #include "arch/registers.hh"
48 #include "debug/MinorExecute.hh"
49 #include "enums/OpClass.hh"
63 os <<
id.threadId <<
'/' <<
id.streamSeqNum <<
'.'
64 <<
id.predictionSeqNum <<
'/' <<
id.lineSeqNum;
67 if (
id.fetchSeqNum != 0) {
68 os <<
'/' <<
id.fetchSeqNum;
69 if (
id.execSeqNum != 0)
70 os <<
'.' <<
id.execSeqNum;
118 os << inst.
id <<
" pc: 0x"
119 << std::hex << inst.
pc.instAddr() << std::dec <<
" (";
122 os <<
"fault: \"" << inst.
fault->name() <<
'"';
140 switch (
reg.classValue())
147 #if THE_ISA == ARM_ISA
151 os <<
'n' << misc_reg;
156 os << 'f' << static_cast<unsigned int>(
reg.index());
159 os << 'v' << static_cast<unsigned int>(
reg.index());
162 os << 'v' << static_cast<unsigned int>(
reg.index()) <<
'[' <<
163 static_cast<unsigned int>(
reg.elemIndex()) <<
']';
166 if (
reg.isZeroReg()) {
169 os << 'r' << static_cast<unsigned int>(
reg.index());
173 os << 'c' << static_cast<unsigned int>(
reg.index());
176 panic(
"Unknown register class: %d", (
int)
reg.classValue());
184 MINORINST(&named_object,
"id=F;%s addr=0x%x fault=\"%s\"\n",
185 id,
pc.instAddr(),
fault->name());
190 std::ostringstream regs_str;
195 regs_str <<
" srcRegs=";
197 unsigned int src_reg = 0;
198 while (src_reg < num_src_regs) {
202 if (src_reg != num_src_regs)
206 regs_str <<
" destRegs=";
208 unsigned int dest_reg = 0;
209 while (dest_reg < num_dest_regs) {
213 if (dest_reg != num_dest_regs)
217 #if THE_ISA == ARM_ISA
218 regs_str <<
" extMachInst=" << std::hex << std::setw(16)
223 std::ostringstream flags;
226 MINORINST(&named_object,
"id=%s addr=0x%x inst=\"%s\" class=%s"
227 " flags=\"%s\"%s%s\n",
bool predictedTaken
This instruction was predicted to change control flow and the following instructions will have a newe...
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
@ VecElemClass
Vector Register Native Elem lane.
static const InstSeqNum firstLineSeqNum
static MinorDynInstPtr bubbleInst
A prototypical bubble instruction.
bool isNoCostInst() const
Is this an instruction that can be executed ‘for free’ and needn't spend time in an FU.
static const InstSeqNum firstStreamSeqNum
First sequence numbers to use in initialisation of the pipeline and to be expected on the first line/...
static const InstSeqNum firstExecSeqNum
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
const char *const miscRegName[]
static const InstSeqNum firstFetchSeqNum
#define MINORINST(sim_object,...)
DPRINTFN for MinorTrace MinorInst line reporting.
Register ID: describe an architectural register with its class and index.
@ FloatRegClass
Floating-point register.
Dynamic instruction for Minor.
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
int8_t numDestRegs() const
Number of destination registers.
static void init()
Initialise the class.
Trace::InstRecord * traceData
Trace information for this instruction's execution.
std::string getName()
Return name of machine instruction.
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
constexpr decltype(nullptr) NoFault
bool isInst() const
Is this a real instruction.
@ IntRegClass
Integer register.
bool isFault() const
Is this a fault rather than instruction.
RefCountingPtr< MinorDynInst > MinorDynInstPtr
MinorDynInsts are currently reference counted.
@ CCRegClass
Condition-code register.
static const InstSeqNum firstPredictionSeqNum
void minorTraceInst(const Named &named_object) const
Print (possibly verbose) instruction information for MinorTrace using the given Named object's name.
int8_t numSrcRegs() const
Number of source registers.
bool isLastMicroop() const
@ MiscRegClass
Control (misc) register.
std::ostream & operator<<(std::ostream &os, const InstId &id)
Print this id in the usual slash-separated format expected by MinorTrace.
@ VecRegClass
Vector Register.
void reportData(std::ostream &os) const
ReportIF interface.
const ExtMachInst machInst
The binary machine instruction.
virtual const std::string & disassemble(Addr pc, const Loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
MinorDynInst(InstId id_=InstId(), Fault fault_=NoFault)
Fault translationFault
Translation fault in case of a mem ref.
bool isLastOpInInst() const
Assuming this is not a fault, is this instruction either a whole instruction or the last microop from...
TheISA::PCState pc
The fetch address of this instruction.
bool isBubble() const
The BubbleIF interface.
static void printRegName(std::ostream &os, const RegId ®)
Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer, float, misc and zero registers ...
Fault fault
This is actually a fault masquerading as an instruction.
Id for lines and instructions.
#define panic(...)
This implements a cprintf based panic() function.
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