gem5  v20.1.0.0
dyn_inst.cc
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37 
38 #include "cpu/minor/dyn_inst.hh"
39 
40 #include <iomanip>
41 #include <sstream>
42 
43 #include "arch/isa.hh"
44 #include "arch/registers.hh"
45 #include "cpu/base.hh"
46 #include "cpu/minor/trace.hh"
47 #include "cpu/reg_class.hh"
48 #include "debug/MinorExecute.hh"
49 #include "enums/OpClass.hh"
50 
51 namespace Minor
52 {
53 
59 
60 std::ostream &
61 operator <<(std::ostream &os, const InstId &id)
62 {
63  os << id.threadId << '/' << id.streamSeqNum << '.'
64  << id.predictionSeqNum << '/' << id.lineSeqNum;
65 
66  /* Not all structures have fetch and exec sequence numbers */
67  if (id.fetchSeqNum != 0) {
68  os << '/' << id.fetchSeqNum;
69  if (id.execSeqNum != 0)
70  os << '.' << id.execSeqNum;
71  }
72 
73  return os;
74 }
75 
77 
78 void
80 {
81  if (!bubbleInst) {
82  bubbleInst = new MinorDynInst();
83  assert(bubbleInst->isBubble());
84  /* Make bubbleInst immortal */
85  bubbleInst->incref();
86  }
87 }
88 
89 bool
91 {
92  assert(staticInst);
93  return !(staticInst->isMicroop() && !staticInst->isLastMicroop());
94 }
95 
96 bool
98 {
99  return isInst() && staticInst->opClass() == No_OpClass;
100 }
101 
102 void
103 MinorDynInst::reportData(std::ostream &os) const
104 {
105  if (isBubble())
106  os << "-";
107  else if (isFault())
108  os << "F;" << id;
109  else if (translationFault != NoFault)
110  os << "TF;" << id;
111  else
112  os << id;
113 }
114 
115 std::ostream &
116 operator <<(std::ostream &os, const MinorDynInst &inst)
117 {
118  os << inst.id << " pc: 0x"
119  << std::hex << inst.pc.instAddr() << std::dec << " (";
120 
121  if (inst.isFault())
122  os << "fault: \"" << inst.fault->name() << '"';
123  else if (inst.translationFault != NoFault)
124  os << "translation fault: \"" << inst.translationFault->name() << '"';
125  else if (inst.staticInst)
126  os << inst.staticInst->getName();
127  else
128  os << "bubble";
129 
130  os << ')';
131 
132  return os;
133 }
134 
137 static void
138 printRegName(std::ostream &os, const RegId& reg)
139 {
140  switch (reg.classValue())
141  {
142  case MiscRegClass:
143  {
144  RegIndex misc_reg = reg.index();
145 
146  /* This is an ugly test because not all archs. have miscRegName */
147 #if THE_ISA == ARM_ISA
148  os << 'm' << misc_reg << '(' << TheISA::miscRegName[misc_reg] <<
149  ')';
150 #else
151  os << 'n' << misc_reg;
152 #endif
153  }
154  break;
155  case FloatRegClass:
156  os << 'f' << static_cast<unsigned int>(reg.index());
157  break;
158  case VecRegClass:
159  os << 'v' << static_cast<unsigned int>(reg.index());
160  break;
161  case VecElemClass:
162  os << 'v' << static_cast<unsigned int>(reg.index()) << '[' <<
163  static_cast<unsigned int>(reg.elemIndex()) << ']';
164  break;
165  case IntRegClass:
166  if (reg.isZeroReg()) {
167  os << 'z';
168  } else {
169  os << 'r' << static_cast<unsigned int>(reg.index());
170  }
171  break;
172  case CCRegClass:
173  os << 'c' << static_cast<unsigned int>(reg.index());
174  break;
175  default:
176  panic("Unknown register class: %d", (int)reg.classValue());
177  }
178 }
179 
180 void
181 MinorDynInst::minorTraceInst(const Named &named_object) const
182 {
183  if (isFault()) {
184  MINORINST(&named_object, "id=F;%s addr=0x%x fault=\"%s\"\n",
185  id, pc.instAddr(), fault->name());
186  } else {
187  unsigned int num_src_regs = staticInst->numSrcRegs();
188  unsigned int num_dest_regs = staticInst->numDestRegs();
189 
190  std::ostringstream regs_str;
191 
192  /* Format lists of src and dest registers for microops and
193  * 'full' instructions */
194  if (!staticInst->isMacroop()) {
195  regs_str << " srcRegs=";
196 
197  unsigned int src_reg = 0;
198  while (src_reg < num_src_regs) {
199  printRegName(regs_str, staticInst->srcRegIdx(src_reg));
200 
201  src_reg++;
202  if (src_reg != num_src_regs)
203  regs_str << ',';
204  }
205 
206  regs_str << " destRegs=";
207 
208  unsigned int dest_reg = 0;
209  while (dest_reg < num_dest_regs) {
210  printRegName(regs_str, staticInst->destRegIdx(dest_reg));
211 
212  dest_reg++;
213  if (dest_reg != num_dest_regs)
214  regs_str << ',';
215  }
216 
217 #if THE_ISA == ARM_ISA
218  regs_str << " extMachInst=" << std::hex << std::setw(16)
219  << std::setfill('0') << staticInst->machInst << std::dec;
220 #endif
221  }
222 
223  std::ostringstream flags;
224  staticInst->printFlags(flags, " ");
225 
226  MINORINST(&named_object, "id=%s addr=0x%x inst=\"%s\" class=%s"
227  " flags=\"%s\"%s%s\n",
228  id, pc.instAddr(),
229  (staticInst->opClass() == No_OpClass ?
230  "(invalid)" : staticInst->disassemble(0,NULL)),
231  Enums::OpClassStrings[staticInst->opClass()],
232  flags.str(),
233  regs_str.str(),
234  (predictedTaken ? " predictedTaken" : ""));
235  }
236 }
237 
239 {
240  if (traceData)
241  delete traceData;
242 }
243 
244 }
dyn_inst.hh
Minor::MinorDynInst::predictedTaken
bool predictedTaken
This instruction was predicted to change control flow and the following instructions will have a newe...
Definition: dyn_inst.hh:182
X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:230
VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:58
Minor::InstId::firstLineSeqNum
static const InstSeqNum firstLineSeqNum
Definition: dyn_inst.hh:75
Minor::MinorDynInst::bubbleInst
static MinorDynInstPtr bubbleInst
A prototypical bubble instruction.
Definition: dyn_inst.hh:160
Minor::MinorDynInst::isNoCostInst
bool isNoCostInst() const
Is this an instruction that can be executed ‘for free’ and needn't spend time in an FU.
Definition: dyn_inst.cc:97
Minor::InstId::firstStreamSeqNum
static const InstSeqNum firstStreamSeqNum
First sequence numbers to use in initialisation of the pipeline and to be expected on the first line/...
Definition: dyn_inst.hh:73
Minor::InstId::firstExecSeqNum
static const InstSeqNum firstExecSeqNum
Definition: dyn_inst.hh:77
StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:225
ArmISA::miscRegName
const char *const miscRegName[]
Definition: miscregs.hh:1159
Minor::InstId::firstFetchSeqNum
static const InstSeqNum firstFetchSeqNum
Definition: dyn_inst.hh:76
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
Minor
Definition: activity.cc:44
MINORINST
#define MINORINST(sim_object,...)
DPRINTFN for MinorTrace MinorInst line reporting.
Definition: trace.hh:64
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:54
Minor::MinorDynInst
Dynamic instruction for Minor.
Definition: dyn_inst.hh:155
StaticInst::printFlags
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
Definition: static_inst.cc:130
StaticInst::numDestRegs
int8_t numDestRegs() const
Number of destination registers.
Definition: static_inst.hh:137
Minor::MinorDynInst::init
static void init()
Initialise the class.
Definition: dyn_inst.cc:79
Minor::MinorDynInst::traceData
Trace::InstRecord * traceData
Trace information for this instruction's execution.
Definition: dyn_inst.hh:168
StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:198
StaticInst::getName
std::string getName()
Return name of machine instruction.
Definition: static_inst.hh:350
Minor::MinorDynInst::id
InstId id
Definition: dyn_inst.hh:165
StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:234
InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:37
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:245
Minor::MinorDynInst::isInst
bool isInst() const
Is this a real instruction.
Definition: dyn_inst.hh:254
IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:53
Minor::MinorDynInst::isFault
bool isFault() const
Is this a fault rather than instruction.
Definition: dyn_inst.hh:251
Minor::MinorDynInstPtr
RefCountingPtr< MinorDynInst > MinorDynInstPtr
MinorDynInsts are currently reference counted.
Definition: dyn_inst.hh:61
CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:60
Named
Definition: trace.hh:147
Minor::InstId::firstPredictionSeqNum
static const InstSeqNum firstPredictionSeqNum
Definition: dyn_inst.hh:74
Minor::MinorDynInst::minorTraceInst
void minorTraceInst(const Named &named_object) const
Print (possibly verbose) instruction information for MinorTrace using the given Named object's name.
Definition: dyn_inst.cc:181
StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:199
StaticInst::numSrcRegs
int8_t numSrcRegs() const
Number of source registers.
Definition: static_inst.hh:135
StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:201
MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:61
Minor::operator<<
std::ostream & operator<<(std::ostream &os, const InstId &id)
Print this id in the usual slash-separated format expected by MinorTrace.
Definition: dyn_inst.cc:61
VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:56
Minor::MinorDynInst::reportData
void reportData(std::ostream &os) const
ReportIF interface.
Definition: dyn_inst.cc:103
base.hh
StaticInst::machInst
const ExtMachInst machInst
The binary machine instruction.
Definition: static_inst.hh:243
RegIndex
uint16_t RegIndex
Definition: types.hh:52
StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const Loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:121
reg_class.hh
Minor::MinorDynInst::MinorDynInst
MinorDynInst(InstId id_=InstId(), Fault fault_=NoFault)
Definition: dyn_inst.hh:233
Minor::MinorDynInst::translationFault
Fault translationFault
Translation fault in case of a mem ref.
Definition: dyn_inst.hh:196
Minor::MinorDynInst::isLastOpInInst
bool isLastOpInInst() const
Assuming this is not a fault, is this instruction either a whole instruction or the last microop from...
Definition: dyn_inst.cc:90
Minor::MinorDynInst::pc
TheISA::PCState pc
The fetch address of this instruction.
Definition: dyn_inst.hh:171
Minor::MinorDynInst::isBubble
bool isBubble() const
The BubbleIF interface.
Definition: dyn_inst.hh:245
trace.hh
Minor::printRegName
static void printRegName(std::ostream &os, const RegId &reg)
Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer, float, misc and zero registers ...
Definition: dyn_inst.cc:138
Minor::MinorDynInst::staticInst
StaticInstPtr staticInst
Definition: dyn_inst.hh:163
Minor::MinorDynInst::fault
Fault fault
This is actually a fault masquerading as an instruction.
Definition: dyn_inst.hh:174
Minor::MinorDynInst::~MinorDynInst
~MinorDynInst()
Definition: dyn_inst.cc:238
Minor::InstId
Id for lines and instructions.
Definition: dyn_inst.hh:68
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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