Go to the documentation of this file.
30 #ifndef __ARCH_SPARC_INSTS_PRIV_HH__
31 #define __ARCH_SPARC_INSTS_PRIV_HH__
44 using SparcStaticInst::SparcStaticInst;
53 OpClass __opClass,
char const * _regName) :
88 Priv(mnem, _machInst, __opClass),
imm(
bits(_machInst, 12, 0))
101 OpClass __opClass,
char const *_regName) :
113 #endif //__ARCH_SPARC_INSTS_PRIV_HH__
WrPrivImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, char const *_regName)
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
PrivReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, char const *_regName)
Base class for privelege mode operations with immediates.
TheISA::ExtMachInst ExtMachInst
Binary extended machine instruction type.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Base class for all SPARC static instructions.
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
PrivImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Base class for privelege mode operations.
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Generated on Wed Sep 30 2020 14:02:07 for gem5 by doxygen 1.8.17