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process.cc
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28 
29 #include "arch/sparc/process.hh"
30 
31 #include "arch/sparc/asi.hh"
32 #include "arch/sparc/handlers.hh"
33 #include "arch/sparc/isa_traits.hh"
34 #include "arch/sparc/registers.hh"
35 #include "arch/sparc/types.hh"
38 #include "base/logging.hh"
39 #include "cpu/thread_context.hh"
40 #include "debug/Stack.hh"
41 #include "mem/page_table.hh"
42 #include "params/Process.hh"
43 #include "sim/aux_vector.hh"
44 #include "sim/process_impl.hh"
45 #include "sim/syscall_return.hh"
46 #include "sim/system.hh"
47 
48 using namespace SparcISA;
49 
50 SparcProcess::SparcProcess(const ProcessParams &params,
51  ::Loader::ObjectFile *objFile, Addr _StackBias)
52  : Process(params,
53  new EmulationPageTable(params.name, params.pid, PageBytes),
54  objFile),
55  StackBias(_StackBias)
56 {
57  fatal_if(params.useArchPT, "Arch page tables not implemented.");
58  // Initialize these to 0s
59  fillStart = 0;
60  spillStart = 0;
61 }
62 
63 void
65 {
67 
69  // From the SPARC ABI
70 
71  // Setup default FP state
73 
75 
76  /*
77  * Register window management registers
78  */
79 
80  // No windows contain info from other programs
81  tc->setIntReg(INTREG_OTHERWIN, 0);
82  // There are no windows to pop
84  // All windows are available to save into
86  // All windows are "clean"
88  // Start with register window 0
89  tc->setMiscReg(MISCREG_CWP, 0);
90  // Always use spill and fill traps 0
91  tc->setIntReg(INTREG_WSTATE, 0);
92  // Set the trap level to 0
94  // Set the ASI register to something fixed
96 
97  // Set the MMU Primary Context Register to hold the process' pid
99 
100  /*
101  * T1 specific registers
102  */
103  // Turn on the icache, dcache, dtb translation, and itb translation.
105 }
106 
107 void
109 {
111 
113  // The process runs in user mode with 32 bit addresses
114  PSTATE pstate = 0;
115  pstate.ie = 1;
116  pstate.am = 1;
117  tc->setMiscReg(MISCREG_PSTATE, pstate);
118 
119  argsInit(32 / 8, PageBytes);
120 }
121 
122 void
124 {
126 
128  // The process runs in user mode
129  PSTATE pstate = 0;
130  pstate.ie = 1;
131  tc->setMiscReg(MISCREG_PSTATE, pstate);
132 
133  argsInit(sizeof(RegVal), PageBytes);
134 }
135 
136 template<class IntType>
137 void
139 {
140  int intSize = sizeof(IntType);
141 
143 
144  std::string filename;
145  if (argv.size() < 1)
146  filename = "";
147  else
148  filename = argv[0];
149 
150  // Even for a 32 bit process, the ABI says we still need to
151  // maintain double word alignment of the stack pointer.
152  uint64_t align = 16;
153 
154  enum hardwareCaps
155  {
156  M5_HWCAP_SPARC_FLUSH = 1,
157  M5_HWCAP_SPARC_STBAR = 2,
158  M5_HWCAP_SPARC_SWAP = 4,
159  M5_HWCAP_SPARC_MULDIV = 8,
160  M5_HWCAP_SPARC_V9 = 16,
161  // This one should technically only be set
162  // if there is a cheetah or cheetah_plus tlb,
163  // but we'll use it all the time
164  M5_HWCAP_SPARC_ULTRA3 = 32
165  };
166 
167  const int64_t hwcap =
168  M5_HWCAP_SPARC_FLUSH |
169  M5_HWCAP_SPARC_STBAR |
170  M5_HWCAP_SPARC_SWAP |
171  M5_HWCAP_SPARC_MULDIV |
172  M5_HWCAP_SPARC_V9 |
173  M5_HWCAP_SPARC_ULTRA3;
174 
175  // Setup the auxilliary vectors. These will already have endian conversion.
176  // Auxilliary vectors are loaded only for elf formatted executables.
177  auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
178  if (elfObject) {
179  // Bits which describe the system hardware capabilities
180  auxv.emplace_back(M5_AT_HWCAP, hwcap);
181  // The system page size
182  auxv.emplace_back(M5_AT_PAGESZ, SparcISA::PageBytes);
183  // Defined to be 100 in the kernel source.
184  // Frequency at which times() increments
185  auxv.emplace_back(M5_AT_CLKTCK, 100);
186  // For statically linked executables, this is the virtual address of
187  // the program header tables if they appear in the executable image
188  auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
189  // This is the size of a program header entry from the elf file.
190  auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
191  // This is the number of program headers from the original elf file.
192  auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
193  // This is the base address of the ELF interpreter; it should be
194  // zero for static executables or contain the base address for
195  // dynamic executables.
196  auxv.emplace_back(M5_AT_BASE, getBias());
197  // This is hardwired to 0 in the elf loading code in the kernel
198  auxv.emplace_back(M5_AT_FLAGS, 0);
199  // The entry point to the program
200  auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
201  // Different user and group IDs
202  auxv.emplace_back(M5_AT_UID, uid());
203  auxv.emplace_back(M5_AT_EUID, euid());
204  auxv.emplace_back(M5_AT_GID, gid());
205  auxv.emplace_back(M5_AT_EGID, egid());
206  // Whether to enable "secure mode" in the executable
207  auxv.emplace_back(M5_AT_SECURE, 0);
208  // The address of 16 "random" bytes.
209  auxv.emplace_back(M5_AT_RANDOM, 0);
210  }
211 
212  // Figure out how big the initial stack needs to be
213 
214  // The unaccounted for 8 byte 0 at the top of the stack
215  int sentry_size = 8;
216 
217  // This is the name of the file which is present on the initial stack
218  // It's purpose is to let the user space linker examine the original file.
219  int file_name_size = filename.size() + 1;
220 
221  const int numRandomBytes = 16;
222  int aux_data_size = numRandomBytes;
223 
224  int env_data_size = 0;
225  for (int i = 0; i < envp.size(); ++i) {
226  env_data_size += envp[i].size() + 1;
227  }
228  int arg_data_size = 0;
229  for (int i = 0; i < argv.size(); ++i) {
230  arg_data_size += argv[i].size() + 1;
231  }
232 
233  // The info_block.
234  int base_info_block_size =
235  sentry_size + file_name_size + env_data_size + arg_data_size;
236 
237  int info_block_size = roundUp(base_info_block_size, align);
238 
239  int info_block_padding = info_block_size - base_info_block_size;
240 
241  // Each auxilliary vector is two words
242  int aux_array_size = intSize * 2 * (auxv.size() + 1);
243 
244  int envp_array_size = intSize * (envp.size() + 1);
245  int argv_array_size = intSize * (argv.size() + 1);
246 
247  int argc_size = intSize;
248  int window_save_size = intSize * 16;
249 
250  // Figure out the size of the contents of the actual initial frame
251  int frame_size =
252  aux_array_size +
253  envp_array_size +
254  argv_array_size +
255  argc_size +
256  window_save_size;
257 
258  // There needs to be padding after the auxiliary vector data so that the
259  // very bottom of the stack is aligned properly.
260  int aligned_partial_size = roundUp(frame_size, align);
261  int aux_padding = aligned_partial_size - frame_size;
262 
263  int space_needed =
264  info_block_size +
265  aux_data_size +
266  aux_padding +
267  frame_size;
268 
269  memState->setStackMin(memState->getStackBase() - space_needed);
270  memState->setStackMin(roundDown(memState->getStackMin(), align));
271  memState->setStackSize(memState->getStackBase() - memState->getStackMin());
272 
273  // Allocate space for the stack
274  memState->mapRegion(roundDown(memState->getStackMin(), pageSize),
275  roundUp(memState->getStackSize(), pageSize), "stack");
276 
277  // map out initial stack contents
278  IntType sentry_base = memState->getStackBase() - sentry_size;
279  IntType file_name_base = sentry_base - file_name_size;
280  IntType env_data_base = file_name_base - env_data_size;
281  IntType arg_data_base = env_data_base - arg_data_size;
282  IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
283  IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
284  IntType envp_array_base = auxv_array_base - envp_array_size;
285  IntType argv_array_base = envp_array_base - argv_array_size;
286  IntType argc_base = argv_array_base - argc_size;
287 #if TRACING_ON
288  IntType window_save_base = argc_base - window_save_size;
289 #endif
290 
291  DPRINTF(Stack, "The addresses of items on the initial stack:\n");
292  DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base);
293  DPRINTF(Stack, "filename = %s\n", filename);
294  DPRINTF(Stack, "%#x - file name\n", file_name_base);
295  DPRINTF(Stack, "%#x - env data\n", env_data_base);
296  DPRINTF(Stack, "%#x - arg data\n", arg_data_base);
297  DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base);
298  DPRINTF(Stack, "%#x - envp array\n", envp_array_base);
299  DPRINTF(Stack, "%#x - argv array\n", argv_array_base);
300  DPRINTF(Stack, "%#x - argc \n", argc_base);
301  DPRINTF(Stack, "%#x - window save\n", window_save_base);
302  DPRINTF(Stack, "%#x - stack min\n", memState->getStackMin());
303 
304  assert(window_save_base == memState->getStackMin());
305 
306  // write contents to stack
307 
308  // figure out argc
309  IntType argc = argv.size();
310  IntType guestArgc = htobe(argc);
311 
312  // Write out the sentry void *
313  uint64_t sentry_NULL = 0;
314  initVirtMem->writeBlob(sentry_base, &sentry_NULL, sentry_size);
315 
316  // Write the file name
317  initVirtMem->writeString(file_name_base, filename.c_str());
318 
319  // Fix up the aux vectors which point to data.
320  for (auto &aux: auxv) {
321  if (aux.type == M5_AT_RANDOM)
322  aux.val = aux_data_base;
323  }
324 
325  // Copy the aux stuff
326  Addr auxv_array_end = auxv_array_base;
327  for (const auto &aux: auxv) {
328  initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
329  auxv_array_end += sizeof(aux);
330  }
331 
332  // Write out the terminating zeroed auxilliary vector
333  const AuxVector<IntType> zero(0, 0);
334  initVirtMem->write(auxv_array_end, zero);
335  auxv_array_end += sizeof(zero);
336 
337  copyStringArray(envp, envp_array_base, env_data_base,
338  ByteOrder::big, *initVirtMem);
339  copyStringArray(argv, argv_array_base, arg_data_base,
340  ByteOrder::big, *initVirtMem);
341 
342  initVirtMem->writeBlob(argc_base, &guestArgc, intSize);
343 
344  // Set up space for the trap handlers into the processes address space.
345  // Since the stack grows down and there is reserved address space abov
346  // it, we can put stuff above it and stay out of the way.
347  fillStart = memState->getStackBase();
349 
351  // Set up the thread context to start running the process
352  // assert(NumArgumentRegs >= 2);
353  // tc->setIntReg(ArgumentReg[0], argc);
354  // tc->setIntReg(ArgumentReg[1], argv_array_base);
355  tc->setIntReg(StackPointerReg, memState->getStackMin() - StackBias);
356 
357  // %g1 is a pointer to a function that should be run at exit. Since we
358  // don't have anything like that, it should be set to 0.
359  tc->setIntReg(1, 0);
360 
361  tc->pcState(getStartPC());
362 
363  // Align the "stack_min" to a page boundary.
364  memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
365 }
366 
367 void
368 Sparc64Process::argsInit(int intSize, int pageSize)
369 {
370  SparcProcess::argsInit<uint64_t>(pageSize);
371 
372  // Stuff the trap handlers into the process address space
373  initVirtMem->writeBlob(fillStart,
374  fillHandler64, sizeof(MachInst) * numFillInsts);
375  initVirtMem->writeBlob(spillStart,
377 }
378 
379 void
380 Sparc32Process::argsInit(int intSize, int pageSize)
381 {
382  SparcProcess::argsInit<uint32_t>(pageSize);
383 
384  // Stuff the trap handlers into the process address space
385  initVirtMem->writeBlob(fillStart,
386  fillHandler32, sizeof(MachInst) * numFillInsts);
387  initVirtMem->writeBlob(spillStart,
389 }
SparcISA::MachInst
uint32_t MachInst
Definition: types.hh:38
SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: miscregs.hh:62
roundDown
T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:150
process.hh
system.hh
Process::envp
std::vector< std::string > envp
Definition: process.hh:212
SparcISA::fillHandler64
const MachInst fillHandler64[numFillInsts]
Definition: handlers.hh:43
Process::gid
uint64_t gid()
Definition: process.hh:82
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
Process
Definition: process.hh:65
M5_AT_UID
@ M5_AT_UID
Definition: aux_vector.hh:69
Sparc64Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:123
handlers.hh
ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:52
Process::argv
std::vector< std::string > argv
Definition: process.hh:211
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
SparcISA::spillHandler32
const MachInst spillHandler32[numSpillInsts]
Definition: handlers.hh:151
M5_AT_PAGESZ
@ M5_AT_PAGESZ
Definition: aux_vector.hh:64
M5_AT_SECURE
@ M5_AT_SECURE
Definition: aux_vector.hh:76
M5_AT_PHENT
@ M5_AT_PHENT
Definition: aux_vector.hh:62
ArmISA::GuestByteOrder
const ByteOrder GuestByteOrder
Definition: isa_traits.hh:50
process_impl.hh
SparcISA::INTREG_CLEANWIN
@ INTREG_CLEANWIN
Definition: registers.hh:78
M5_AT_EUID
@ M5_AT_EUID
Definition: aux_vector.hh:70
SparcISA::MISCREG_FSR
@ MISCREG_FSR
Floating Point Status Register.
Definition: miscregs.hh:83
std::vector
STL vector class.
Definition: stl.hh:37
SparcISA::ASI_PRIMARY
@ ASI_PRIMARY
Definition: asi.hh:163
Process::initVirtMem
std::unique_ptr< SETranslatingPortProxy > initVirtMem
Definition: process.hh:172
SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:41
Process::egid
uint64_t egid()
Definition: process.hh:83
Loader::ElfObject
Definition: elf_object.hh:59
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
SparcProcess::StackBias
const Addr StackBias
Definition: process.hh:45
SparcISA::spillHandler64
const MachInst spillHandler64[numSpillInsts]
Definition: handlers.hh:115
SparcISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:41
M5_AT_ENTRY
@ M5_AT_ENTRY
Definition: aux_vector.hh:67
SparcISA
Definition: asi.cc:31
M5_AT_BASE
@ M5_AT_BASE
Definition: aux_vector.hh:65
Loader::ObjectFile
Definition: object_file.hh:74
M5_AT_PHNUM
@ M5_AT_PHNUM
Definition: aux_vector.hh:63
SparcISA::INTREG_CANRESTORE
@ INTREG_CANRESTORE
Definition: registers.hh:77
elf_object.hh
AuxVector
Definition: aux_vector.hh:38
SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: miscregs.hh:43
Loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:112
syscall_return.hh
SparcISA::INTREG_WSTATE
@ INTREG_WSTATE
Definition: registers.hh:80
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
EmulationPageTable
Definition: page_table.hh:49
SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: miscregs.hh:63
SparcProcess::spillStart
Addr spillStart
Definition: process.hh:48
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:237
SparcProcess::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:64
asi.hh
isa_traits.hh
M5_AT_FLAGS
@ M5_AT_FLAGS
Definition: aux_vector.hh:66
SparcISA::INTREG_CANSAVE
@ INTREG_CANSAVE
Definition: registers.hh:76
SparcISA::numSpillInsts
const int numSpillInsts
Definition: handlers.hh:41
SparcISA::MISCREG_MMU_LSU_CTRL
@ MISCREG_MMU_LSU_CTRL
Definition: miscregs.hh:89
M5_AT_RANDOM
@ M5_AT_RANDOM
Definition: aux_vector.hh:78
types.hh
SparcProcess::fillStart
Addr fillStart
Definition: process.hh:48
Sparc64Process::argsInit
void argsInit(int intSize, int pageSize)
Definition: process.cc:368
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
Process::objFile
::Loader::ObjectFile * objFile
Definition: process.hh:208
Process::getBias
Addr getBias()
Definition: process.cc:469
SparcISA::numFillInsts
const int numFillInsts
Definition: handlers.hh:40
name
const std::string & name()
Definition: trace.cc:48
Process::contextIds
std::vector< ContextID > contextIds
Definition: process.hh:157
Sparc32Process::argsInit
void argsInit(int intSize, int pageSize)
Definition: process.cc:380
SparcProcess::argsInit
void argsInit(int pageSize)
Definition: process.cc:138
SparcProcess::SparcProcess
SparcProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile, Addr _StackBias)
Definition: process.cc:50
M5_AT_GID
@ M5_AT_GID
Definition: aux_vector.hh:71
System::threads
Threads threads
Definition: system.hh:304
ArmISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:53
aux_vector.hh
SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: miscregs.hh:42
ArmISA::StackPointerReg
const int StackPointerReg
Definition: registers.hh:106
Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:277
roundUp
T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:131
Process::_pid
uint64_t _pid
Definition: process.hh:263
htobe
T htobe(T value)
Definition: byteswap.hh:143
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
SparcISA::fillHandler32
const MachInst fillHandler32[numFillInsts]
Definition: handlers.hh:79
logging.hh
Process::euid
uint64_t euid()
Definition: process.hh:81
Process::getStartPC
Addr getStartPC()
Definition: process.cc:477
Sparc32Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:108
registers.hh
M5_AT_HWCAP
@ M5_AT_HWCAP
Definition: aux_vector.hh:74
SimObject::params
const Params & params() const
Definition: sim_object.hh:168
ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
Process::system
System * system
Definition: process.hh:160
SparcISA::MISCREG_MMU_P_CONTEXT
@ MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: miscregs.hh:86
Process::uid
uint64_t uid()
Definition: process.hh:80
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:219
M5_AT_CLKTCK
@ M5_AT_CLKTCK
Definition: aux_vector.hh:75
page_table.hh
SparcISA::INTREG_OTHERWIN
@ INTREG_OTHERWIN
Definition: registers.hh:79
copyStringArray
void copyStringArray(std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
Definition: process_impl.hh:40
M5_AT_EGID
@ M5_AT_EGID
Definition: aux_vector.hh:72
object_file.hh
thread_context.hh
Process::memState
std::shared_ptr< MemState > memState
Definition: process.hh:274
RegVal
uint64_t RegVal
Definition: types.hh:174
M5_AT_PHDR
@ M5_AT_PHDR
Definition: aux_vector.hh:61
SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: miscregs.hh:65

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