thread_context.hh

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/*
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 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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 * not be construed as granting a license to any other intellectual
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#ifndef __CPU_THREAD_CONTEXT_HH__
#define __CPU_THREAD_CONTEXT_HH__
 
#include <iostream>
#include <string>
 
#include "arch/generic/htm.hh"
#include "arch/generic/isa.hh"
#include "arch/registers.hh"
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "cpu/pc_event.hh"
#include "cpu/reg_class.hh"
 
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
namespace TheISA
{
    class Decoder;
}
class BaseCPU;
class BaseMMU;
class BaseTLB;
class CheckerCPU;
class Checkpoint;
class PortProxy;
class Process;
class System;
 
class ThreadContext : public PCEventScope
{
  protected:
    bool useForClone = false;
 
  public:
 
    bool getUseForClone() { return useForClone; }
 
    void setUseForClone(bool new_val) { useForClone = new_val; }
 
    enum Status
    {
        Active,
 
        Suspended,
 
        Halting,
 
        Halted
    };
 
    virtual ~ThreadContext() { };
 
    virtual BaseCPU *getCpuPtr() = 0;
 
    virtual int cpuId() const = 0;
 
    virtual uint32_t socketId() const = 0;
 
    virtual int threadId() const = 0;
 
    virtual void setThreadId(int id) = 0;
 
    virtual ContextID contextId() const = 0;
 
    virtual void setContextId(ContextID id) = 0;
 
    virtual BaseMMU *getMMUPtr() = 0;
 
    virtual CheckerCPU *getCheckerCpuPtr() = 0;
 
    virtual BaseISA *getIsaPtr() = 0;
 
    virtual TheISA::Decoder *getDecoderPtr() = 0;
 
    virtual System *getSystemPtr() = 0;
 
    virtual PortProxy &getPhysProxy() = 0;
 
    virtual PortProxy &getVirtProxy() = 0;
 
    virtual void initMemProxies(ThreadContext *tc) = 0;
 
    virtual Process *getProcessPtr() = 0;
 
    virtual void setProcessPtr(Process *p) = 0;
 
    virtual Status status() const = 0;
 
    virtual void setStatus(Status new_status) = 0;
 
    virtual void activate() = 0;
 
    virtual void suspend() = 0;
 
    virtual void halt() = 0;
 
    void quiesce();
 
    void quiesceTick(Tick resume);
 
    virtual void takeOverFrom(ThreadContext *old_context) = 0;
 
    virtual void regStats(const std::string &name) {};
 
    virtual void scheduleInstCountEvent(Event *event, Tick count) = 0;
    virtual void descheduleInstCountEvent(Event *event) = 0;
    virtual Tick getCurrentInstCount() = 0;
 
    // Not necessarily the best location for these...
    // Having an extra function just to read these is obnoxious
    virtual Tick readLastActivate() = 0;
    virtual Tick readLastSuspend() = 0;
 
    virtual void copyArchRegs(ThreadContext *tc) = 0;
 
    virtual void clearArchRegs() = 0;
 
    //
    // New accessors for new decoder.
    //
    virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
 
    virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
 
    virtual const TheISA::VecRegContainer&
        readVecReg(const RegId& reg) const = 0;
    virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
 
    virtual ConstVecLane8
    readVec8BitLaneReg(const RegId& reg) const = 0;
 
    virtual ConstVecLane16
    readVec16BitLaneReg(const RegId& reg) const = 0;
 
    virtual ConstVecLane32
    readVec32BitLaneReg(const RegId& reg) const = 0;
 
    virtual ConstVecLane64
    readVec64BitLaneReg(const RegId& reg) const = 0;
 
    virtual void setVecLane(const RegId& reg,
            const LaneData<LaneSize::Byte>& val) = 0;
    virtual void setVecLane(const RegId& reg,
            const LaneData<LaneSize::TwoByte>& val) = 0;
    virtual void setVecLane(const RegId& reg,
            const LaneData<LaneSize::FourByte>& val) = 0;
    virtual void setVecLane(const RegId& reg,
            const LaneData<LaneSize::EightByte>& val) = 0;
    virtual const TheISA::VecElem& readVecElem(const RegId& reg) const = 0;
 
    virtual const TheISA::VecPredRegContainer& readVecPredReg(
            const RegId& reg) const = 0;
    virtual TheISA::VecPredRegContainer& getWritableVecPredReg(
            const RegId& reg) = 0;
 
    virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
 
    virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
 
    virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
 
    virtual void setVecReg(const RegId& reg,
            const TheISA::VecRegContainer& val) = 0;
 
    virtual void setVecElem(const RegId& reg, const TheISA::VecElem& val) = 0;
 
    virtual void setVecPredReg(const RegId& reg,
            const TheISA::VecPredRegContainer& val) = 0;
 
    virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
 
    virtual TheISA::PCState pcState() const = 0;
 
    virtual void pcState(const TheISA::PCState &val) = 0;
 
    void
    setNPC(Addr val)
    {
        TheISA::PCState pc_state = pcState();
        pc_state.setNPC(val);
        pcState(pc_state);
    }
 
    virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
 
    virtual Addr instAddr() const = 0;
 
    virtual Addr nextInstAddr() const = 0;
 
    virtual MicroPC microPC() const = 0;
 
    virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
 
    virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
 
    virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
 
    virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
 
    virtual RegId flattenRegId(const RegId& reg_id) const = 0;
 
    // Also not necessarily the best location for these two.  Hopefully will go
    // away once we decide upon where st cond failures goes.
    virtual unsigned readStCondFailures() const = 0;
 
    virtual void setStCondFailures(unsigned sc_failures) = 0;
 
    // Same with st cond failures.
    virtual Counter readFuncExeInst() const = 0;
 
    // This function exits the thread context in the CPU and returns
    // 1 if the CPU has no more active threads (meaning it's OK to exit);
    // Used in syscall-emulation mode when a  thread calls the exit syscall.
    virtual int exit() { return 1; };
 
    static void compare(ThreadContext *one, ThreadContext *two);
 
    virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
    virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
 
    virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
    virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
 
    virtual const TheISA::VecRegContainer&
        readVecRegFlat(RegIndex idx) const = 0;
    virtual TheISA::VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
    virtual void setVecRegFlat(RegIndex idx,
            const TheISA::VecRegContainer& val) = 0;
 
    virtual const TheISA::VecElem& readVecElemFlat(RegIndex idx,
            const ElemIndex& elem_idx) const = 0;
    virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
            const TheISA::VecElem& val) = 0;
 
    virtual const TheISA::VecPredRegContainer &
        readVecPredRegFlat(RegIndex idx) const = 0;
    virtual TheISA::VecPredRegContainer& getWritableVecPredRegFlat(
            RegIndex idx) = 0;
    virtual void setVecPredRegFlat(RegIndex idx,
            const TheISA::VecPredRegContainer& val) = 0;
 
    virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
    virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
    // hardware transactional memory
    virtual void htmAbortTransaction(uint64_t htm_uid,
                                     HtmFailureFaultCause cause) = 0;
    virtual BaseHTMCheckpointPtr& getHtmCheckpointPtr() = 0;
    virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) = 0;
};
 
void serialize(const ThreadContext &tc, CheckpointOut &cp);
void unserialize(ThreadContext &tc, CheckpointIn &cp);
 
void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
 
#endif