gem5  v21.0.0.0
All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
base_gic.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012-2013, 2017-2018 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
42 #ifndef __DEV_ARM_BASE_GIC_H__
43 #define __DEV_ARM_BASE_GIC_H__
44 
45 #include <unordered_map>
46 
47 #include "arch/arm/system.hh"
48 #include "dev/io_device.hh"
49 
50 #include "enums/ArmInterruptType.hh"
51 
52 class Platform;
53 class RealView;
54 class ThreadContext;
55 class ArmInterruptPin;
56 class ArmSPI;
57 class ArmPPI;
58 
59 struct ArmInterruptPinParams;
60 struct ArmPPIParams;
61 struct ArmSPIParams;
62 struct BaseGicParams;
63 
64 class BaseGic : public PioDevice
65 {
66  public:
67  typedef BaseGicParams Params;
68  enum class GicVersion { GIC_V2, GIC_V3, GIC_V4 };
69 
70  BaseGic(const Params &p);
71  virtual ~BaseGic();
72  void init() override;
73 
74  const Params &params() const;
75 
84  virtual void sendInt(uint32_t num) = 0;
85 
92  virtual void sendPPInt(uint32_t num, uint32_t cpu) = 0;
93  virtual void clearPPInt(uint32_t num, uint32_t cpu) = 0;
94 
103  virtual void clearInt(uint32_t num) = 0;
104 
105  ArmSystem *
106  getSystem() const
107  {
108  return (ArmSystem *) sys;
109  }
110 
112  virtual bool supportsVersion(GicVersion version) = 0;
113 
114  protected:
117 };
118 
120 {
121  public:
122  virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
123  virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
124 
125  virtual void writeDistributor(ContextID ctx, Addr daddr,
126  uint32_t data) = 0;
127  virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
128 };
129 
138 {
139  public:
140  ArmInterruptPinGen(const ArmInterruptPinParams &p);
141 
142  virtual ArmInterruptPin* get(ThreadContext *tc = nullptr) = 0;
143 };
144 
151 {
152  public:
153  ArmSPIGen(const ArmSPIParams &p);
154 
155  ArmInterruptPin* get(ThreadContext *tc = nullptr) override;
156  protected:
158 };
159 
166 {
167  public:
168  PARAMS(ArmPPI);
169  ArmPPIGen(const Params &p);
170 
171  ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
172  protected:
173  std::unordered_map<ContextID, ArmPPI*> pins;
174 };
175 
180 {
181  friend class ArmInterruptPinGen;
182  protected:
183  ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc);
184 
185  public: /* Public interface */
194 
196  uint32_t num() const { return intNum; }
197 
199  bool active() const { return _active; }
200 
202  virtual void raise() = 0;
204  virtual void clear() = 0;
205 
206  public: /* Serializable interface */
207  void serialize(CheckpointOut &cp) const override;
208  void unserialize(CheckpointIn &cp) override;
209 
210  protected:
217  ContextID targetContext() const;
218 
224 
227 
229  const uint32_t intNum;
230 
232  const ArmInterruptType triggerType;
233 
235  bool _active;
236 };
237 
238 class ArmSPI : public ArmInterruptPin
239 {
240  friend class ArmSPIGen;
241  private:
242  ArmSPI(const ArmSPIParams &p);
243 
244  public:
245  void raise() override;
246  void clear() override;
247 };
248 
249 class ArmPPI : public ArmInterruptPin
250 {
251  friend class ArmPPIGen;
252  private:
253  ArmPPI(const ArmPPIParams &p, ThreadContext *tc);
254 
255  public:
256  void raise() override;
257  void clear() override;
258 };
259 
260 #endif
io_device.hh
BaseGic::Params
BaseGicParams Params
Definition: base_gic.hh:67
ArmPPIGen
Private Peripheral Interrupt Generator Since PPIs are banked in the GIC, this class is capable of gen...
Definition: base_gic.hh:165
SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:162
ArmSPI::ArmSPI
ArmSPI(const ArmSPIParams &p)
Definition: base_gic.cc:157
ArmSPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:171
RealView
Definition: realview.hh:57
ArmSPIGen::ArmSPIGen
ArmSPIGen(const ArmSPIParams &p)
Definition: base_gic.cc:83
ArmInterruptPinGen::get
virtual ArmInterruptPin * get(ThreadContext *tc=nullptr)=0
data
const char data[]
Definition: circlebuf.test.cc:47
ArmPPIGen::pins
std::unordered_map< ContextID, ArmPPI * > pins
Definition: base_gic.hh:173
ArmInterruptPin::clear
virtual void clear()=0
Clear a signalled interrupt.
Serializable
Basic support for object serialization.
Definition: serialize.hh:175
ArmInterruptPin::setThreadContext
void setThreadContext(ThreadContext *tc)
Set the thread context owning this interrupt.
Definition: base_gic.cc:129
ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:237
ArmPPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:100
ArmPPI::ArmPPI
ArmPPI(const ArmPPIParams &p, ThreadContext *tc)
Definition: base_gic.cc:177
ArmInterruptPin::_active
bool _active
True if interrupt pin is active, false otherwise.
Definition: base_gic.hh:235
ArmInterruptPin::ArmInterruptPin
ArmInterruptPin(const ArmInterruptPinParams &p, ThreadContext *tc)
Definition: base_gic.cc:120
system.hh
BaseGic::supportsVersion
virtual bool supportsVersion(GicVersion version)=0
Check if version supported.
ArmPPIGen::PARAMS
PARAMS(ArmPPI)
BaseGic::params
const Params & params() const
Definition: base_gic.cc:73
ArmInterruptPin::num
uint32_t num() const
Get interrupt number.
Definition: base_gic.hh:196
PioDevice::sys
System * sys
Definition: io_device.hh:102
ArmInterruptPin::intNum
const uint32_t intNum
Interrupt number to generate.
Definition: base_gic.hh:229
BaseGic::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base_gic.cc:66
ArmInterruptPin::triggerType
const ArmInterruptType triggerType
Interrupt triggering type.
Definition: base_gic.hh:232
ArmSPIGen::get
ArmInterruptPin * get(ThreadContext *tc=nullptr) override
Definition: base_gic.cc:89
ArmSPIGen
Shared Peripheral Interrupt Generator It is capable of generating one interrupt only: it maintains a ...
Definition: base_gic.hh:150
cp
Definition: cprintf.cc:37
PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:99
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
BaseGicRegisters
Definition: base_gic.hh:119
ArmInterruptPin::targetContext
ContextID targetContext() const
Get the target context ID of this interrupt.
Definition: base_gic.cc:138
ArmInterruptPinGen
This SimObject is instantiated in the python world and serves as an ArmInterruptPin generator.
Definition: base_gic.hh:137
ArmPPI::clear
void clear() override
Clear a signalled interrupt.
Definition: base_gic.cc:191
BaseGic::platform
Platform * platform
Platform this GIC belongs to.
Definition: base_gic.hh:116
ArmInterruptPinGen::ArmInterruptPinGen
ArmInterruptPinGen(const ArmInterruptPinParams &p)
Definition: base_gic.cc:78
BaseGicRegisters::writeCpu
virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data)=0
BaseGicRegisters::writeDistributor
virtual void writeDistributor(ContextID ctx, Addr daddr, uint32_t data)=0
Platform
Definition: platform.hh:49
ArmInterruptPin::threadContext
const ThreadContext * threadContext
Pointer to the thread context that owns this interrupt in case it is a thread-/CPU-private interrupt.
Definition: base_gic.hh:223
BaseGic::clearPPInt
virtual void clearPPInt(uint32_t num, uint32_t cpu)=0
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
ArmInterruptPin::platform
RealView *const platform
Arm platform to use for interrupt generation.
Definition: base_gic.hh:226
ArmInterruptPin::active
bool active() const
True if interrupt pin is active, false otherwise.
Definition: base_gic.hh:199
BaseGic::sendInt
virtual void sendInt(uint32_t num)=0
Post an interrupt from a device that is connected to the GIC.
BaseGic::~BaseGic
virtual ~BaseGic()
Definition: base_gic.cc:61
BaseGic::clearInt
virtual void clearInt(uint32_t num)=0
Clear an interrupt from a device that is connected to the GIC.
ArmSystem
Definition: system.hh:59
BaseGicRegisters::readDistributor
virtual uint32_t readDistributor(ContextID ctx, Addr daddr)=0
BaseGic
Definition: base_gic.hh:64
ArmSPIGen::pin
ArmSPI * pin
Definition: base_gic.hh:157
BaseGic::GicVersion::GIC_V3
@ GIC_V3
ArmInterruptPin
Generic representation of an Arm interrupt pin.
Definition: base_gic.hh:179
BaseGic::BaseGic
BaseGic(const Params &p)
Definition: base_gic.cc:47
BaseGic::GicVersion::GIC_V2
@ GIC_V2
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:64
BaseGic::getSystem
ArmSystem * getSystem() const
Definition: base_gic.hh:106
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
BaseGic::sendPPInt
virtual void sendPPInt(uint32_t num, uint32_t cpu)=0
Interface call for private peripheral interrupts.
ArmPPIGen::ArmPPIGen
ArmPPIGen(const Params &p)
Definition: base_gic.cc:94
CheckpointIn
Definition: serialize.hh:68
ArmInterruptPin::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: base_gic.cc:146
ArmSPI
Definition: base_gic.hh:238
BaseGic::GicVersion
GicVersion
Definition: base_gic.hh:68
ArmPPI
Definition: base_gic.hh:249
ArmInterruptPin::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: base_gic.cc:152
BaseGic::GicVersion::GIC_V4
@ GIC_V4
BaseGicRegisters::readCpu
virtual uint32_t readCpu(ContextID ctx, Addr daddr)=0
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:141

Generated on Tue Mar 23 2021 19:41:25 for gem5 by doxygen 1.8.17