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static_inst.cc
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28 
29 #include "cpu/static_inst.hh"
30 
31 #include <iostream>
32 
33 #include "sim/core.hh"
34 
35 namespace {
36 
37 static TheISA::ExtMachInst nopMachInst;
38 
39 class NopStaticInst : public StaticInst
40 {
41  public:
42  NopStaticInst() : StaticInst("gem5 nop", nopMachInst, No_OpClass)
43  {}
44 
45  Fault
46  execute(ExecContext *xc, Trace::InstRecord *traceData) const override
47  {
48  return NoFault;
49  }
50 
51  void
52  advancePC(TheISA::PCState &pcState) const override
53  {
54  pcState.advance();
55  }
56 
57  std::string
59  const Loader::SymbolTable *symtab) const override
60  {
61  return mnemonic;
62  }
63 
64  private:
65 };
66 
67 }
68 
71 
73 {
75  delete cachedDisassembly;
76 }
77 
78 bool
80  TheISA::PCState &tgt) const
81 {
82  if (isDirectCtrl()) {
83  tgt = branchTarget(pc);
84  return true;
85  }
86 
87  if (isIndirectCtrl()) {
88  tgt = branchTarget(tc);
89  return true;
90  }
91 
92  return false;
93 }
94 
97 {
98  panic("StaticInst::fetchMicroop() called on instruction "
99  "that is not microcoded.");
100 }
101 
104 {
105  panic("StaticInst::branchTarget() called on instruction "
106  "that is not a PC-relative branch.");
107 }
108 
111 {
112  panic("StaticInst::branchTarget() called on instruction "
113  "that is not an indirect branch.");
114 }
115 
116 const std::string &
118 {
119  if (!cachedDisassembly)
120  cachedDisassembly = new std::string(generateDisassembly(pc, symtab));
121 
122  return *cachedDisassembly;
123 }
124 
125 void
126 StaticInst::printFlags(std::ostream &outs,
127  const std::string &separator) const
128 {
129  bool printed_a_flag = false;
130 
131  for (unsigned int flag = IsNop; flag < Num_Flags; flag++) {
132  if (flags[flag]) {
133  if (printed_a_flag)
134  outs << separator;
135 
136  outs << FlagsStrings[flag];
137  printed_a_flag = true;
138  }
139  }
140 }
StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:100
StaticInst::isDirectCtrl
bool isDirectCtrl() const
Definition: static_inst.hh:182
StaticInst::advancePC
virtual void advancePC(TheISA::PCState &pcState) const =0
StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:85
StaticInst::hasBranchTarget
bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
Return true if the instruction is a control transfer, and if so, return the target address as well.
Definition: static_inst.cc:79
Loader::SymbolTable
Definition: symtab.hh:58
Trace::InstRecord
Definition: insttracer.hh:55
StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const Loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:117
StaticInst::cachedDisassembly
std::string * cachedDisassembly
String representation of disassembly (lazily evaluated via disassemble()).
Definition: static_inst.hh:290
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
StaticInst::branchTarget
virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:103
StaticInst::printFlags
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
Definition: static_inst.cc:126
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:246
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:70
StaticInst::~StaticInst
virtual ~StaticInst()
Definition: static_inst.cc:72
StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:284
static_inst.hh
StaticInst::isIndirectCtrl
bool isIndirectCtrl() const
Definition: static_inst.hh:183
NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:251
core.hh
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
StaticInst::nullStaticInstPtr
static StaticInstPtr nullStaticInstPtr
Pointer to a statically allocated "null" instruction object.
Definition: static_inst.hh:253
StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:96
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
RefCountingPtr< StaticInst >
StaticInst::execute
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
MicroPC
uint16_t MicroPC
Definition: types.hh:150
StaticInst::nopStaticInstPtr
static StaticInstPtr nopStaticInstPtr
Pointer to a statically allocated generic "nop" instruction object.
Definition: static_inst.hh:256
StaticInst::generateDisassembly
virtual std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const =0
Internal function to generate disassembly string.
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
MipsISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:39

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