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mmu.hh
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37 
38 #ifndef __ARCH_GENERIC_MMU_HH__
39 #define __ARCH_GENERIC_MMU_HH__
40 
41 #include "arch/generic/tlb.hh"
42 
43 #include "params/BaseMMU.hh"
44 
45 class BaseMMU : public SimObject
46 {
47  protected:
48  typedef BaseMMUParams Params;
49 
50  BaseMMU(const Params &p)
51  : SimObject(p), dtb(p.dtb), itb(p.itb)
52  {}
53 
54  BaseTLB*
56  {
57  if (mode == BaseTLB::Execute)
58  return itb;
59  else
60  return dtb;
61  }
62 
63  public:
64  void
66  {
67  dtb->flushAll();
68  itb->flushAll();
69  }
70 
71  void
72  demapPage(Addr vaddr, uint64_t asn)
73  {
74  itb->demapPage(vaddr, asn);
75  dtb->demapPage(vaddr, asn);
76  }
77 
78  Fault
81  {
82  return getTlb(mode)->translateAtomic(req, tc, mode);
83  }
84 
85  void
88  {
89  return getTlb(mode)->translateTiming(req, tc, translation, mode);
90  }
91 
92  Fault
95  {
96  return getTlb(mode)->translateFunctional(req, tc, mode);
97  }
98 
99  Fault
101  BaseTLB::Mode mode) const
102  {
103  return getTlb(mode)->finalizePhysical(req, tc, mode);
104  }
105 
106  virtual void takeOverFrom(BaseMMU *old_mmu);
107 
108  public:
111 };
112 
113 #endif
BaseMMU
Definition: mmu.hh:45
BaseTLB::translateAtomic
virtual Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)=0
BaseMMU::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Definition: mmu.hh:93
tlb.hh
BaseTLB::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)=0
BaseTLB::Mode
Mode
Definition: tlb.hh:57
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:86
BaseMMU::dtb
BaseTLB * dtb
Definition: mmu.hh:109
BaseTLB
Definition: tlb.hh:50
BaseMMU::flushAll
void flushAll()
Definition: mmu.hh:65
BaseMMU::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) const
Definition: mmu.hh:100
BaseMMU::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseTLB::Translation *translation, BaseTLB::Mode mode)
Definition: mmu.hh:86
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
BaseMMU::takeOverFrom
virtual void takeOverFrom(BaseMMU *old_mmu)
Definition: mmu.cc:47
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:246
MipsISA::vaddr
vaddr
Definition: pra_constants.hh:275
BaseTLB::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition: tlb.hh:96
ArmISA::mode
Bitfield< 4, 0 > mode
Definition: miscregs_types.hh:70
BaseMMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Definition: mmu.hh:79
BaseTLB::Translation
Definition: tlb.hh:59
BaseMMU::Params
BaseMMUParams Params
Definition: mmu.hh:48
BaseMMU::getTlb
BaseTLB * getTlb(BaseTLB::Mode mode) const
Definition: mmu.hh:55
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:148
BaseTLB::demapPage
virtual void demapPage(Addr vaddr, uint64_t asn)=0
BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.hh:72
BaseMMU::itb
BaseTLB * itb
Definition: mmu.hh:110
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
BaseTLB::Execute
@ Execute
Definition: tlb.hh:57
BaseTLB::finalizePhysical
virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const =0
Do post-translation physical address finalization.
BaseTLB::flushAll
virtual void flushAll()=0
Remove all entries from the TLB.
BaseMMU::BaseMMU
BaseMMU(const Params &p)
Definition: mmu.hh:50
SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:141

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