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arch
generic
mmu.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2020 ARM Limited
3
* All rights reserved.
4
*
5
* The license below extends only to copyright in the software and shall
6
* not be construed as granting a license to any other intellectual
7
* property including but not limited to intellectual property relating
8
* to a hardware implementation of the functionality of the software
9
* licensed hereunder. You may use the software subject to the license
10
* terms below provided that you ensure that this notice is replicated
11
* unmodified and in its entirety in all distributions of the software,
12
* modified or unmodified, in source code or in binary form.
13
*
14
* Redistribution and use in source and binary forms, with or without
15
* modification, are permitted provided that the following conditions are
16
* met: redistributions of source code must retain the above copyright
17
* notice, this list of conditions and the following disclaimer;
18
* redistributions in binary form must reproduce the above copyright
19
* notice, this list of conditions and the following disclaimer in the
20
* documentation and/or other materials provided with the distribution;
21
* neither the name of the copyright holders nor the names of its
22
* contributors may be used to endorse or promote products derived from
23
* this software without specific prior written permission.
24
*
25
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
*/
37
38
#ifndef __ARCH_GENERIC_MMU_HH__
39
#define __ARCH_GENERIC_MMU_HH__
40
41
#include "
arch/generic/tlb.hh
"
42
43
#include "params/BaseMMU.hh"
44
45
class
BaseMMU
:
public
SimObject
46
{
47
protected
:
48
typedef
BaseMMUParams
Params
;
49
50
BaseMMU
(
const
Params
&
p
)
51
:
SimObject
(
p
),
dtb
(
p
.
dtb
),
itb
(
p
.
itb
)
52
{}
53
54
BaseTLB
*
55
getTlb
(
BaseTLB::Mode
mode
)
const
56
{
57
if
(
mode
==
BaseTLB::Execute
)
58
return
itb
;
59
else
60
return
dtb
;
61
}
62
63
public
:
64
void
65
flushAll
()
66
{
67
dtb
->
flushAll
();
68
itb
->
flushAll
();
69
}
70
71
void
72
demapPage
(
Addr
vaddr
, uint64_t asn)
73
{
74
itb
->
demapPage
(
vaddr
, asn);
75
dtb
->
demapPage
(
vaddr
, asn);
76
}
77
78
Fault
79
translateAtomic
(
const
RequestPtr
&req,
ThreadContext
*tc,
80
BaseTLB::Mode
mode
)
81
{
82
return
getTlb
(
mode
)->
translateAtomic
(req, tc,
mode
);
83
}
84
85
void
86
translateTiming
(
const
RequestPtr
&req,
ThreadContext
*tc,
87
BaseTLB::Translation
*translation,
BaseTLB::Mode
mode
)
88
{
89
return
getTlb
(
mode
)->
translateTiming
(req, tc, translation,
mode
);
90
}
91
92
Fault
93
translateFunctional
(
const
RequestPtr
&req,
ThreadContext
*tc,
94
BaseTLB::Mode
mode
)
95
{
96
return
getTlb
(
mode
)->
translateFunctional
(req, tc,
mode
);
97
}
98
99
Fault
100
finalizePhysical
(
const
RequestPtr
&req,
ThreadContext
*tc,
101
BaseTLB::Mode
mode
)
const
102
{
103
return
getTlb
(
mode
)->
finalizePhysical
(req, tc,
mode
);
104
}
105
106
virtual
void
takeOverFrom
(
BaseMMU
*old_mmu);
107
108
public
:
109
BaseTLB
*
dtb
;
110
BaseTLB
*
itb
;
111
};
112
113
#endif
BaseMMU
Definition:
mmu.hh:45
BaseTLB::translateAtomic
virtual Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)=0
BaseMMU::translateFunctional
Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Definition:
mmu.hh:93
tlb.hh
BaseTLB::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)=0
BaseTLB::Mode
Mode
Definition:
tlb.hh:57
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition:
request.hh:86
BaseMMU::dtb
BaseTLB * dtb
Definition:
mmu.hh:109
BaseTLB
Definition:
tlb.hh:50
BaseMMU::flushAll
void flushAll()
Definition:
mmu.hh:65
BaseMMU::finalizePhysical
Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) const
Definition:
mmu.hh:100
BaseMMU::translateTiming
void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseTLB::Translation *translation, BaseTLB::Mode mode)
Definition:
mmu.hh:86
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:88
BaseMMU::takeOverFrom
virtual void takeOverFrom(BaseMMU *old_mmu)
Definition:
mmu.cc:47
Fault
std::shared_ptr< FaultBase > Fault
Definition:
types.hh:246
MipsISA::vaddr
vaddr
Definition:
pra_constants.hh:275
BaseTLB::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
Definition:
tlb.hh:96
ArmISA::mode
Bitfield< 4, 0 > mode
Definition:
miscregs_types.hh:70
BaseMMU::translateAtomic
Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
Definition:
mmu.hh:79
BaseTLB::Translation
Definition:
tlb.hh:59
BaseMMU::Params
BaseMMUParams Params
Definition:
mmu.hh:48
BaseMMU::getTlb
BaseTLB * getTlb(BaseTLB::Mode mode) const
Definition:
mmu.hh:55
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:148
BaseTLB::demapPage
virtual void demapPage(Addr vaddr, uint64_t asn)=0
BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition:
mmu.hh:72
BaseMMU::itb
BaseTLB * itb
Definition:
mmu.hh:110
MipsISA::p
Bitfield< 0 > p
Definition:
pra_constants.hh:323
BaseTLB::Execute
@ Execute
Definition:
tlb.hh:57
BaseTLB::finalizePhysical
virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, Mode mode) const =0
Do post-translation physical address finalization.
BaseTLB::flushAll
virtual void flushAll()=0
Remove all entries from the TLB.
BaseMMU::BaseMMU
BaseMMU(const Params &p)
Definition:
mmu.hh:50
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:141
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