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SimpleExecContext Class Reference

#include <exec_context.hh>

Inheritance diagram for SimpleExecContext:
ExecContext

Classes

struct  ExecContextStats
 

Public Member Functions

 SimpleExecContext (BaseSimpleCPU *_cpu, SimpleThread *_thread)
 Constructor. More...
 
RegVal readIntRegOperand (const StaticInst *si, int idx) override
 Reads an integer register. More...
 
void setIntRegOperand (const StaticInst *si, int idx, RegVal val) override
 Sets an integer register to a value. More...
 
RegVal readFloatRegOperandBits (const StaticInst *si, int idx) override
 Reads a floating point register in its binary format, instead of by value. More...
 
void setFloatRegOperandBits (const StaticInst *si, int idx, RegVal val) override
 Sets the bits of a floating point register of single width to a binary value. More...
 
const TheISA::VecRegContainer & readVecRegOperand (const StaticInst *si, int idx) const override
 Reads a vector register. More...
 
TheISA::VecRegContainer & getWritableVecRegOperand (const StaticInst *si, int idx) override
 Reads a vector register for modification. More...
 
void setVecRegOperand (const StaticInst *si, int idx, const TheISA::VecRegContainer &val) override
 Sets a vector register to a value. More...
 
TheISA::VecElem readVecElemOperand (const StaticInst *si, int idx) const override
 Reads an element of a vector register. More...
 
void setVecElemOperand (const StaticInst *si, int idx, const TheISA::VecElem val) override
 Sets an element of a vector register to a value. More...
 
const TheISA::VecPredRegContainer & readVecPredRegOperand (const StaticInst *si, int idx) const override
 Predicate registers interface. More...
 
TheISA::VecPredRegContainer & getWritableVecPredRegOperand (const StaticInst *si, int idx) override
 Gets destination predicate register operand for modification. More...
 
void setVecPredRegOperand (const StaticInst *si, int idx, const TheISA::VecPredRegContainer &val) override
 Sets a destination predicate register operand to a value. More...
 
RegVal readCCRegOperand (const StaticInst *si, int idx) override
 
void setCCRegOperand (const StaticInst *si, int idx, RegVal val) override
 
RegVal readMiscRegOperand (const StaticInst *si, int idx) override
 
void setMiscRegOperand (const StaticInst *si, int idx, RegVal val) override
 
RegVal readMiscReg (int misc_reg) override
 Reads a miscellaneous register, handling any architectural side effects due to reading that register. More...
 
void setMiscReg (int misc_reg, RegVal val) override
 Sets a miscellaneous register, handling any architectural side effects due to writing that register. More...
 
TheISA::PCState pcState () const override
 
void pcState (const TheISA::PCState &val) override
 
Fault readMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
 Perform an atomic memory read operation. More...
 
Fault initiateMemRead (Addr addr, unsigned int size, Request::Flags flags, const std::vector< bool > &byte_enable) override
 Initiate a timing memory read operation. More...
 
Fault writeMem (uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector< bool > &byte_enable) override
 For atomic-mode contexts, perform an atomic memory write operation. More...
 
Fault amoMem (Addr addr, uint8_t *data, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation) More...
 
Fault initiateMemAMO (Addr addr, unsigned int size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override
 For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation) More...
 
Fault initiateHtmCmd (Request::Flags flags) override
 Initiate an HTM command, e.g. More...
 
void setStCondFailures (unsigned int sc_failures) override
 Sets the number of consecutive store conditional failures. More...
 
unsigned int readStCondFailures () const override
 Returns the number of consecutive store conditional failures. More...
 
ThreadContext * tcBase () const override
 Returns a pointer to the ThreadContext. More...
 
bool readPredicate () const override
 
void setPredicate (bool val) override
 
bool readMemAccPredicate () const override
 
void setMemAccPredicate (bool val) override
 
uint64_t getHtmTransactionUid () const override
 
uint64_t newHtmTransactionUid () const override
 
bool inHtmTransactionalState () const override
 
uint64_t getHtmTransactionalDepth () const override
 
void demapPage (Addr vaddr, uint64_t asn) override
 Invalidate a page in the DTLB and ITLB. More...
 
void armMonitor (Addr address) override
 
bool mwait (PacketPtr pkt) override
 
void mwaitAtomic (ThreadContext *tc) override
 
AddressMonitor * getAddrMonitor () override
 
template<typename VE >
VecLaneT< VE, true > readVecLaneOperand (const StaticInst *si, int idx) const
 Vector Register Lane Interfaces. More...
 
virtual ConstVecLane8 readVec8BitLaneOperand (const StaticInst *si, int idx) const override
 Reads source vector 8bit operand. More...
 
virtual ConstVecLane16 readVec16BitLaneOperand (const StaticInst *si, int idx) const override
 Reads source vector 16bit operand. More...
 
virtual ConstVecLane32 readVec32BitLaneOperand (const StaticInst *si, int idx) const override
 Reads source vector 32bit operand. More...
 
virtual ConstVecLane64 readVec64BitLaneOperand (const StaticInst *si, int idx) const override
 Reads source vector 64bit operand. More...
 
template<typename LD >
void setVecLaneOperandT (const StaticInst *si, int idx, const LD &val)
 Write a lane of the destination vector operand. More...
 
virtual void setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val) override
 Write a lane of the destination vector operand. More...
 
virtual void setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val) override
 Write a lane of the destination vector operand. More...
 
virtual void setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val) override
 Write a lane of the destination vector operand. More...
 
virtual void setVecLaneOperand (const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val) override
 Write a lane of the destination vector operand. More...
 
Integer Register Interfaces
Floating Point Register Interfaces
Condition Code Registers
Misc Register Interfaces
PC Control
Memory Interface
ARM-Specific Interfaces
X86-Specific Interfaces

Public Attributes

BaseSimpleCPU * cpu
 
SimpleThread * thread
 
Addr fetchOffset
 
bool stayAtPC
 
TheISA::PCState predPC
 
Counter numInst
 PER-THREAD STATS. More...
 
Counter numOp
 
Counter numLoad
 
Counter lastIcacheStall
 
Counter lastDcacheStall
 
SimpleExecContext::ExecContextStats execContextStats
 

Detailed Description

Definition at line 57 of file exec_context.hh.

Constructor & Destructor Documentation

◆ SimpleExecContext()

SimpleExecContext::SimpleExecContext ( BaseSimpleCPU *  _cpu,
SimpleThread *  _thread 
)
inline

Constructor.

Definition at line 268 of file exec_context.hh.

Member Function Documentation

◆ amoMem()

Fault SimpleExecContext::amoMem ( Addr  addr,
uint8_t *  data,
unsigned int  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlineoverridevirtual

For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic Read-Modify-Write Memory Operation)

Reimplemented from ExecContext.

Definition at line 566 of file exec_context.hh.

References X86ISA::addr, BaseSimpleCPU::amoMem(), cpu, and data.

◆ armMonitor()

void SimpleExecContext::armMonitor ( Addr  address)
inlineoverridevirtual

Implements ExecContext.

Definition at line 668 of file exec_context.hh.

References BaseCPU::armMonitor(), cpu, thread, and SimpleThread::threadId().

◆ demapPage()

void SimpleExecContext::demapPage ( Addr  vaddr,
uint64_t  asn 
)
inlineoverridevirtual

Invalidate a page in the DTLB and ITLB.

Implements ExecContext.

Definition at line 662 of file exec_context.hh.

References SimpleThread::demapPage(), thread, and MipsISA::vaddr.

◆ getAddrMonitor()

AddressMonitor* SimpleExecContext::getAddrMonitor ( )
inlineoverridevirtual

Implements ExecContext.

Definition at line 686 of file exec_context.hh.

References cpu, BaseCPU::getCpuAddrMonitor(), thread, and SimpleThread::threadId().

◆ getHtmTransactionalDepth()

uint64_t SimpleExecContext::getHtmTransactionalDepth ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 652 of file exec_context.hh.

References SimpleThread::htmTransactionStarts, SimpleThread::htmTransactionStops, and thread.

Referenced by inHtmTransactionalState().

◆ getHtmTransactionUid()

uint64_t SimpleExecContext::getHtmTransactionUid ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 634 of file exec_context.hh.

References ThreadContext::getHtmCheckpointPtr(), and tcBase().

Referenced by TimingSimpleCPU::advanceInst(), TimingSimpleCPU::completeDataAccess(), TimingSimpleCPU::initiateHtmCmd(), TimingSimpleCPU::sendData(), and TimingSimpleCPU::sendSplitData().

◆ getWritableVecPredRegOperand()

TheISA::VecPredRegContainer& SimpleExecContext::getWritableVecPredRegOperand ( const StaticInst *  si,
int  idx 
)
inlineoverridevirtual

Gets destination predicate register operand for modification.

Implements ExecContext.

Definition at line 447 of file exec_context.hh.

References execContextStats, SimpleThread::getWritableVecPredReg(), SimpleExecContext::ExecContextStats::numVecPredRegWrites, X86ISA::reg, ArmISA::si, and thread.

◆ getWritableVecRegOperand()

TheISA::VecRegContainer& SimpleExecContext::getWritableVecRegOperand ( const StaticInst *  si,
int  idx 
)
inlineoverridevirtual

Reads a vector register for modification.

Implements ExecContext.

Definition at line 328 of file exec_context.hh.

References execContextStats, SimpleThread::getWritableVecReg(), SimpleExecContext::ExecContextStats::numVecRegWrites, X86ISA::reg, ArmISA::si, and thread.

◆ inHtmTransactionalState()

bool SimpleExecContext::inHtmTransactionalState ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 646 of file exec_context.hh.

References getHtmTransactionalDepth().

Referenced by TimingSimpleCPU::advanceInst(), BaseSimpleCPU::checkForInterrupts(), TimingSimpleCPU::completeDataAccess(), TimingSimpleCPU::completeIfetch(), TimingSimpleCPU::sendData(), TimingSimpleCPU::sendSplitData(), and TimingSimpleCPU::switchOut().

◆ initiateHtmCmd()

Fault SimpleExecContext::initiateHtmCmd ( Request::Flags  flags)
inlineoverridevirtual

Initiate an HTM command, e.g.

tell Ruby we're starting/stopping a transaction

Implements ExecContext.

Definition at line 579 of file exec_context.hh.

References cpu, and BaseSimpleCPU::initiateHtmCmd().

◆ initiateMemAMO()

Fault SimpleExecContext::initiateMemAMO ( Addr  addr,
unsigned int  size,
Request::Flags  flags,
AtomicOpFunctorPtr  amo_op 
)
inlineoverridevirtual

For timing-mode contexts, initiate an atomic AMO (atomic read-modify-write memory operation)

Reimplemented from ExecContext.

Definition at line 572 of file exec_context.hh.

References X86ISA::addr, cpu, and BaseSimpleCPU::initiateMemAMO().

◆ initiateMemRead()

Fault SimpleExecContext::initiateMemRead ( Addr  addr,
unsigned int  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable 
)
inlineoverridevirtual

Initiate a timing memory read operation.

Must be overridden for exec contexts that support timing memory mode. Not pure virtual since exec contexts that only support atomic memory mode need not override (though in that case this function should never be called).

Reimplemented from ExecContext.

Definition at line 546 of file exec_context.hh.

References X86ISA::addr, cpu, and BaseSimpleCPU::initiateMemRead().

◆ mwait()

bool SimpleExecContext::mwait ( PacketPtr  pkt)
inlineoverridevirtual

Implements ExecContext.

Definition at line 674 of file exec_context.hh.

References cpu, BaseCPU::mwait(), thread, and SimpleThread::threadId().

◆ mwaitAtomic()

void SimpleExecContext::mwaitAtomic ( ThreadContext *  tc)
inlineoverridevirtual

Implements ExecContext.

Definition at line 680 of file exec_context.hh.

References cpu, SimpleThread::mmu, BaseCPU::mwaitAtomic(), thread, and SimpleThread::threadId().

◆ newHtmTransactionUid()

uint64_t SimpleExecContext::newHtmTransactionUid ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 640 of file exec_context.hh.

References ThreadContext::getHtmCheckpointPtr(), and tcBase().

Referenced by TimingSimpleCPU::completeIfetch().

◆ pcState() [1/2]

TheISA::PCState SimpleExecContext::pcState ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 524 of file exec_context.hh.

References SimpleThread::pcState(), and thread.

◆ pcState() [2/2]

void SimpleExecContext::pcState ( const TheISA::PCState &  val)
inlineoverridevirtual

Implements ExecContext.

Definition at line 530 of file exec_context.hh.

References SimpleThread::pcState(), thread, and X86ISA::val.

◆ readCCRegOperand()

RegVal SimpleExecContext::readCCRegOperand ( const StaticInst *  si,
int  idx 
)
inlineoverridevirtual

Implements ExecContext.

Definition at line 466 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numCCRegReads, SimpleThread::readCCReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readFloatRegOperandBits()

RegVal SimpleExecContext::readFloatRegOperandBits ( const StaticInst *  si,
int  idx 
)
inlineoverridevirtual

Reads a floating point register in its binary format, instead of by value.

Implements ExecContext.

Definition at line 297 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numFpRegReads, SimpleThread::readFloatReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readIntRegOperand()

RegVal SimpleExecContext::readIntRegOperand ( const StaticInst *  si,
int  idx 
)
inlineoverridevirtual

Reads an integer register.

Implements ExecContext.

Definition at line 276 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numIntRegReads, SimpleThread::readIntReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readMem()

Fault SimpleExecContext::readMem ( Addr  addr,
uint8_t *  data,
unsigned int  size,
Request::Flags  flags,
const std::vector< bool > &  byte_enable 
)
inlineoverridevirtual

Perform an atomic memory read operation.

Must be overridden for exec contexts that support atomic memory mode. Not pure virtual since exec contexts that only support timing memory mode need not override (though in that case this function should never be called).

Reimplemented from ExecContext.

Definition at line 536 of file exec_context.hh.

References X86ISA::addr, cpu, data, and BaseSimpleCPU::readMem().

◆ readMemAccPredicate()

bool SimpleExecContext::readMemAccPredicate ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 622 of file exec_context.hh.

References SimpleThread::readMemAccPredicate(), and thread.

◆ readMiscReg()

RegVal SimpleExecContext::readMiscReg ( int  misc_reg)
inlineoverridevirtual

Reads a miscellaneous register, handling any architectural side effects due to reading that register.

Implements ExecContext.

Definition at line 506 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numIntRegReads, SimpleThread::readMiscReg(), and thread.

◆ readMiscRegOperand()

RegVal SimpleExecContext::readMiscRegOperand ( const StaticInst *  si,
int  idx 
)
inlineoverridevirtual

Implements ExecContext.

Definition at line 484 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numIntRegReads, SimpleThread::readMiscReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readPredicate()

bool SimpleExecContext::readPredicate ( ) const
inlineoverridevirtual

Implements ExecContext.

Definition at line 606 of file exec_context.hh.

References SimpleThread::readPredicate(), and thread.

◆ readStCondFailures()

unsigned int SimpleExecContext::readStCondFailures ( ) const
inlineoverridevirtual

Returns the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 597 of file exec_context.hh.

References SimpleThread::readStCondFailures(), and thread.

◆ readVec16BitLaneOperand()

virtual ConstVecLane16 SimpleExecContext::readVec16BitLaneOperand ( const StaticInst *  si,
int  idx 
) const
inlineoverridevirtual

Reads source vector 16bit operand.

Implements ExecContext.

Definition at line 367 of file exec_context.hh.

References ArmISA::si.

◆ readVec32BitLaneOperand()

virtual ConstVecLane32 SimpleExecContext::readVec32BitLaneOperand ( const StaticInst *  si,
int  idx 
) const
inlineoverridevirtual

Reads source vector 32bit operand.

Implements ExecContext.

Definition at line 373 of file exec_context.hh.

References ArmISA::si.

◆ readVec64BitLaneOperand()

virtual ConstVecLane64 SimpleExecContext::readVec64BitLaneOperand ( const StaticInst *  si,
int  idx 
) const
inlineoverridevirtual

Reads source vector 64bit operand.

Implements ExecContext.

Definition at line 379 of file exec_context.hh.

References ArmISA::si.

◆ readVec8BitLaneOperand()

virtual ConstVecLane8 SimpleExecContext::readVec8BitLaneOperand ( const StaticInst *  si,
int  idx 
) const
inlineoverridevirtual

Reads source vector 8bit operand.

Implements ExecContext.

Definition at line 361 of file exec_context.hh.

References ArmISA::si.

◆ readVecElemOperand()

TheISA::VecElem SimpleExecContext::readVecElemOperand ( const StaticInst *  si,
int  idx 
) const
inlineoverridevirtual

Reads an element of a vector register.

Implements ExecContext.

Definition at line 418 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numVecRegReads, SimpleThread::readVecElem(), X86ISA::reg, ArmISA::si, and thread.

◆ readVecLaneOperand()

template<typename VE >
VecLaneT<VE, true> SimpleExecContext::readVecLaneOperand ( const StaticInst *  si,
int  idx 
) const
inline

Vector Register Lane Interfaces.

Reads source vector lane.

Definition at line 352 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numVecRegReads, SimpleThread::readVecLane(), X86ISA::reg, ArmISA::si, and thread.

◆ readVecPredRegOperand()

const TheISA::VecPredRegContainer& SimpleExecContext::readVecPredRegOperand ( const StaticInst *  si,
int  idx 
) const
inlineoverridevirtual

Predicate registers interface.

Reads source predicate register operand.

Implements ExecContext.

Definition at line 438 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numVecPredRegReads, SimpleThread::readVecPredReg(), X86ISA::reg, ArmISA::si, and thread.

◆ readVecRegOperand()

const TheISA::VecRegContainer& SimpleExecContext::readVecRegOperand ( const StaticInst *  si,
int  idx 
) const
inlineoverridevirtual

Reads a vector register.

Implements ExecContext.

Definition at line 318 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numVecRegReads, SimpleThread::readVecReg(), X86ISA::reg, ArmISA::si, and thread.

◆ setCCRegOperand()

void SimpleExecContext::setCCRegOperand ( const StaticInst *  si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Implements ExecContext.

Definition at line 475 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numCCRegWrites, X86ISA::reg, SimpleThread::setCCReg(), ArmISA::si, thread, and X86ISA::val.

◆ setFloatRegOperandBits()

void SimpleExecContext::setFloatRegOperandBits ( const StaticInst *  si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets the bits of a floating point register of single width to a binary value.

Implements ExecContext.

Definition at line 308 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numFpRegWrites, X86ISA::reg, SimpleThread::setFloatReg(), ArmISA::si, thread, and X86ISA::val.

◆ setIntRegOperand()

void SimpleExecContext::setIntRegOperand ( const StaticInst *  si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Sets an integer register to a value.

Implements ExecContext.

Definition at line 286 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numIntRegWrites, X86ISA::reg, SimpleThread::setIntReg(), ArmISA::si, thread, and X86ISA::val.

◆ setMemAccPredicate()

void SimpleExecContext::setMemAccPredicate ( bool  val)
inlineoverridevirtual

Implements ExecContext.

Definition at line 628 of file exec_context.hh.

References SimpleThread::setMemAccPredicate(), thread, and X86ISA::val.

Referenced by BaseSimpleCPU::preExecute().

◆ setMiscReg()

void SimpleExecContext::setMiscReg ( int  misc_reg,
RegVal  val 
)
inlineoverridevirtual

Sets a miscellaneous register, handling any architectural side effects due to writing that register.

Implements ExecContext.

Definition at line 517 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numIntRegWrites, SimpleThread::setMiscReg(), thread, and X86ISA::val.

◆ setMiscRegOperand()

void SimpleExecContext::setMiscRegOperand ( const StaticInst *  si,
int  idx,
RegVal  val 
)
inlineoverridevirtual

Implements ExecContext.

Definition at line 493 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numIntRegWrites, X86ISA::reg, SimpleThread::setMiscReg(), ArmISA::si, thread, and X86ISA::val.

◆ setPredicate()

void SimpleExecContext::setPredicate ( bool  val)
inlineoverridevirtual

Implements ExecContext.

Definition at line 612 of file exec_context.hh.

References cpu, Trace::InstRecord::setPredicate(), SimpleThread::setPredicate(), thread, BaseSimpleCPU::traceData, and X86ISA::val.

Referenced by BaseSimpleCPU::preExecute().

◆ setStCondFailures()

void SimpleExecContext::setStCondFailures ( unsigned int  sc_failures)
inlineoverridevirtual

Sets the number of consecutive store conditional failures.

Implements ExecContext.

Definition at line 588 of file exec_context.hh.

References SimpleThread::setStCondFailures(), and thread.

◆ setVecElemOperand()

void SimpleExecContext::setVecElemOperand ( const StaticInst *  si,
int  idx,
const TheISA::VecElem  val 
)
inlineoverridevirtual

Sets an element of a vector register to a value.

Implements ExecContext.

Definition at line 428 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numVecRegWrites, X86ISA::reg, SimpleThread::setVecElem(), ArmISA::si, thread, and X86ISA::val.

◆ setVecLaneOperand() [1/4]

virtual void SimpleExecContext::setVecLaneOperand ( const StaticInst *  si,
int  idx,
const LaneData< LaneSize::Byte > &  val 
)
inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 396 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperand() [2/4]

virtual void SimpleExecContext::setVecLaneOperand ( const StaticInst *  si,
int  idx,
const LaneData< LaneSize::EightByte > &  val 
)
inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 411 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperand() [3/4]

virtual void SimpleExecContext::setVecLaneOperand ( const StaticInst *  si,
int  idx,
const LaneData< LaneSize::FourByte > &  val 
)
inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 406 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperand() [4/4]

virtual void SimpleExecContext::setVecLaneOperand ( const StaticInst *  si,
int  idx,
const LaneData< LaneSize::TwoByte > &  val 
)
inlineoverridevirtual

Write a lane of the destination vector operand.

Implements ExecContext.

Definition at line 401 of file exec_context.hh.

References setVecLaneOperandT(), ArmISA::si, and X86ISA::val.

◆ setVecLaneOperandT()

template<typename LD >
void SimpleExecContext::setVecLaneOperandT ( const StaticInst *  si,
int  idx,
const LD &  val 
)
inline

Write a lane of the destination vector operand.

Definition at line 386 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numVecRegWrites, X86ISA::reg, SimpleThread::setVecLane(), ArmISA::si, thread, and X86ISA::val.

Referenced by setVecLaneOperand().

◆ setVecPredRegOperand()

void SimpleExecContext::setVecPredRegOperand ( const StaticInst *  si,
int  idx,
const TheISA::VecPredRegContainer &  val 
)
inlineoverridevirtual

Sets a destination predicate register operand to a value.

Implements ExecContext.

Definition at line 456 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numVecPredRegWrites, X86ISA::reg, SimpleThread::setVecPredReg(), ArmISA::si, thread, and X86ISA::val.

◆ setVecRegOperand()

void SimpleExecContext::setVecRegOperand ( const StaticInst *  si,
int  idx,
const TheISA::VecRegContainer &  val 
)
inlineoverridevirtual

Sets a vector register to a value.

Implements ExecContext.

Definition at line 338 of file exec_context.hh.

References execContextStats, SimpleExecContext::ExecContextStats::numVecRegWrites, X86ISA::reg, SimpleThread::setVecReg(), ArmISA::si, thread, and X86ISA::val.

◆ tcBase()

ThreadContext* SimpleExecContext::tcBase ( ) const
inlineoverridevirtual

Returns a pointer to the ThreadContext.

Implements ExecContext.

Definition at line 603 of file exec_context.hh.

References SimpleThread::getTC(), and thread.

Referenced by getHtmTransactionUid(), and newHtmTransactionUid().

◆ writeMem()

Fault SimpleExecContext::writeMem ( uint8_t *  data,
unsigned int  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
const std::vector< bool > &  byte_enable 
)
inlineoverridevirtual

For atomic-mode contexts, perform an atomic memory write operation.

For timing-mode contexts, initiate a timing memory write operation.

Implements ExecContext.

Definition at line 556 of file exec_context.hh.

References X86ISA::addr, cpu, data, and BaseSimpleCPU::writeMem().

Member Data Documentation

◆ cpu

BaseSimpleCPU* SimpleExecContext::cpu

Definition at line 60 of file exec_context.hh.

Referenced by amoMem(), armMonitor(), SimpleExecContext::ExecContextStats::ExecContextStats(), getAddrMonitor(), initiateHtmCmd(), initiateMemAMO(), initiateMemRead(), mwait(), mwaitAtomic(), readMem(), setPredicate(), and writeMem().

◆ execContextStats

SimpleExecContext::ExecContextStats SimpleExecContext::execContextStats

Referenced by BaseSimpleCPU::advancePC(), BaseSimpleCPU::countInst(), getWritableVecPredRegOperand(), getWritableVecRegOperand(), BaseSimpleCPU::postExecute(), BaseSimpleCPU::preExecute(), readCCRegOperand(), readFloatRegOperandBits(), readIntRegOperand(), readMiscReg(), readMiscRegOperand(), readVecElemOperand(), readVecLaneOperand(), readVecPredRegOperand(), readVecRegOperand(), setCCRegOperand(), setFloatRegOperandBits(), setIntRegOperand(), setMiscReg(), setMiscRegOperand(), setVecElemOperand(), setVecLaneOperandT(), setVecPredRegOperand(), and setVecRegOperand().

◆ fetchOffset

Addr SimpleExecContext::fetchOffset

Definition at line 64 of file exec_context.hh.

Referenced by BaseSimpleCPU::advancePC(), BaseSimpleCPU::checkForInterrupts(), BaseSimpleCPU::preExecute(), and BaseSimpleCPU::setupFetchRequest().

◆ lastDcacheStall

Counter SimpleExecContext::lastDcacheStall

Definition at line 80 of file exec_context.hh.

◆ lastIcacheStall

Counter SimpleExecContext::lastIcacheStall

Definition at line 78 of file exec_context.hh.

◆ numInst

Counter SimpleExecContext::numInst

PER-THREAD STATS.

Definition at line 73 of file exec_context.hh.

Referenced by BaseSimpleCPU::countInst(), TimingSimpleCPU::htmSendAbortSignal(), TimingSimpleCPU::initiateHtmCmd(), and BaseSimpleCPU::preExecute().

◆ numLoad

Counter SimpleExecContext::numLoad

Definition at line 76 of file exec_context.hh.

Referenced by BaseSimpleCPU::postExecute().

◆ numOp

Counter SimpleExecContext::numOp

Definition at line 74 of file exec_context.hh.

Referenced by BaseSimpleCPU::countInst().

◆ predPC

TheISA::PCState SimpleExecContext::predPC

Definition at line 70 of file exec_context.hh.

Referenced by BaseSimpleCPU::advancePC(), and BaseSimpleCPU::preExecute().

◆ stayAtPC

bool SimpleExecContext::stayAtPC

Definition at line 67 of file exec_context.hh.

Referenced by TimingSimpleCPU::advanceInst(), AtomicSimpleCPU::isCpuDrained(), TimingSimpleCPU::isCpuDrained(), BaseSimpleCPU::preExecute(), TimingSimpleCPU::switchOut(), and AtomicSimpleCPU::tick().

◆ thread

SimpleThread* SimpleExecContext::thread

Definition at line 61 of file exec_context.hh.

Referenced by BaseSimpleCPU::advancePC(), AtomicSimpleCPU::amoMem(), armMonitor(), BaseSimpleCPU::checkForInterrupts(), TimingSimpleCPU::completeDataAccess(), TimingSimpleCPU::completeIfetch(), BaseSimpleCPU::countInst(), demapPage(), TimingSimpleCPU::fetch(), getAddrMonitor(), getHtmTransactionalDepth(), getWritableVecPredRegOperand(), getWritableVecRegOperand(), TimingSimpleCPU::handleReadPacket(), TimingSimpleCPU::handleWritePacket(), TimingSimpleCPU::htmSendAbortSignal(), TimingSimpleCPU::initiateHtmCmd(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), AtomicSimpleCPU::isCpuDrained(), TimingSimpleCPU::isCpuDrained(), mwait(), mwaitAtomic(), pcState(), BaseSimpleCPU::preExecute(), readCCRegOperand(), readFloatRegOperandBits(), readIntRegOperand(), AtomicSimpleCPU::readMem(), readMemAccPredicate(), readMiscReg(), readMiscRegOperand(), readPredicate(), readStCondFailures(), readVecElemOperand(), readVecLaneOperand(), readVecPredRegOperand(), readVecRegOperand(), TimingSimpleCPU::sendData(), setCCRegOperand(), setFloatRegOperandBits(), setIntRegOperand(), setMemAccPredicate(), setMiscReg(), setMiscRegOperand(), setPredicate(), setStCondFailures(), BaseSimpleCPU::setupFetchRequest(), setVecElemOperand(), setVecLaneOperandT(), setVecPredRegOperand(), setVecRegOperand(), TimingSimpleCPU::switchOut(), tcBase(), AtomicSimpleCPU::tick(), AtomicSimpleCPU::writeMem(), and TimingSimpleCPU::writeMem().

The documentation for this class was generated from the following file:
Generated on Tue Jun 22 2021 15:28:44 for gem5 by doxygen 1.8.17