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arch
generic
isa.hh
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2020 ARM Limited
3
* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
8
* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright 2020 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
19
* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
21
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_GENERIC_ISA_HH__
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#define __ARCH_GENERIC_ISA_HH__
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#include "
sim/sim_object.hh
"
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class
ThreadContext
;
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class
BaseISA
:
public
SimObject
48
{
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protected
:
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using
SimObject::SimObject
;
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52
ThreadContext
*
tc
=
nullptr
;
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54
public
:
55
virtual
void
takeOverFrom
(
ThreadContext
*new_tc,
ThreadContext
*old_tc) {}
56
virtual
void
setThreadContext
(
ThreadContext
*_tc) {
tc
= _tc; }
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virtual
uint64_t
getExecutingAsid
()
const
{
return
0; }
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virtual
bool
inUserMode
()
const
= 0;
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};
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#endif // __ARCH_GENERIC_ISA_HH__
BaseISA::inUserMode
virtual bool inUserMode() const =0
BaseISA::setThreadContext
virtual void setThreadContext(ThreadContext *_tc)
Definition:
isa.hh:56
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:88
sim_object.hh
BaseISA::tc
ThreadContext * tc
Definition:
isa.hh:52
BaseISA::getExecutingAsid
virtual uint64_t getExecutingAsid() const
Definition:
isa.hh:58
BaseISA::takeOverFrom
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition:
isa.hh:55
SimObject::SimObject
SimObject(const Params &p)
Definition:
sim_object.cc:52
BaseISA
Definition:
isa.hh:47
SimObject
Abstract superclass for simulation objects.
Definition:
sim_object.hh:141
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