The SimObject API.

These methods relate to the SimObject interface. More...

Functions
const Params &	SimObject::params () const
	SimObject::SimObject (const Params &p)
virtual const std::string	SimObject::name () const
virtual void	SimObject::init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...
virtual void	SimObject::regProbePoints ()
	Register probe points for this object. More...
virtual void	SimObject::regProbeListeners ()
	Register probe listeners for this object. More...
ProbeManager *	SimObject::getProbeManager ()
	Get the probe manager for this object. More...
virtual Port &	SimObject::getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index. More...
virtual void	SimObject::startup ()
	startup() is the final initialization call before simulation. More...
virtual void	SimObject::memWriteback ()
	Write back dirty buffers to memory using functional writes. More...
virtual void	SimObject::memInvalidate ()
	Invalidate the contents of memory buffers. More...
static SimObject *	SimObject::find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Variables
const SimObjectParams &	SimObject::_params
	Cached copy of the object parameters. More...

Detailed Description

These methods relate to the SimObject interface.

Function Documentation

find()

SimObject * SimObject::find ( const char *  name )

static

Find the SimObject with the given name and return a pointer to it.

Primarily used for interactive debugging. Argument is char* rather than std::string to make it callable from gdb.

Definition at line 168 of file sim_object.cc.

References ArmISA::i, SimObject::name(), and SimObject::simObjectList.

Referenced by LdsState::getLdsChunk(), X86KvmCPU::getMsrIntersection(), LdsState::releaseSpace(), and LdsState::reserveSpace().

getPort()

Port & SimObject::getPort ( const std::string &  if_name, PortID  idx = InvalidPortID  )

virtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns

A reference to the given port

Reimplemented in SMMUv3, SMMUv3DeviceInterface, QoS::MemSinkCtrl, BaseCache, ArmISA::TableWalker, MemCtrl, IGbE, BaseXBar, NSGigE, SimpleCache, Bridge, X86ISA::GpuTLB, SimpleMemobj, BaseTrafficGen, DmaDevice, System, GPUCoalescer, Sinic::Device, X86ISA::Interrupts, DistEtherLink, BaseCPU, DRAMsim3, DRAMSim2, TLBCoalescer, SimpleMemory, X86ISA::Walker, RiscvISA::Walker, CopyEngine, RubyPort, EtherLink, Clint, PioDevice, ExternalSlave, X86ISA::I8042, FastModel::GIC, ProtocolTester, ExternalMaster, X86ISA::I82094AA, RubyTester, FastModel::CortexA76Cluster, FastModel::CortexR52Cluster, EtherTapBase, X86ISA::I8259, X86ISA::Cmos, CommMonitor, MemTest, FastModel::CortexA76, RiscvRTC, X86ISA::I8254, FastModel::CortexR52, RubyDirectedTester, MemDelay, MemCheckerMonitor, EtherBus, GarnetSyntheticTraffic, AddrMapper, EtherSwitch, SerialLink, AbstractController, ComputeUnit, SCMI::Platform, Gicv3Its, LdsState, MessageBuffer, and Network.

Definition at line 120 of file sim_object.cc.

References fatal, and SimObject::name().

Referenced by CxxConfigManager::bindPort(), EtherSwitch::getPort(), AddrMapper::getPort(), GarnetSyntheticTraffic::getPort(), MemCheckerMonitor::getPort(), MemDelay::getPort(), RubyDirectedTester::getPort(), FastModel::CortexR52::getPort(), MemTest::getPort(), CommMonitor::getPort(), EtherTapBase::getPort(), FastModel::CortexR52Cluster::getPort(), FastModel::CortexA76Cluster::getPort(), RubyTester::getPort(), SMMUv3DeviceInterface::getPort(), ExternalMaster::getPort(), ProtocolTester::getPort(), ExternalSlave::getPort(), PioDevice::getPort(), QoS::MemSinkCtrl::getPort(), EtherLink::getPort(), RubyPort::getPort(), RiscvISA::Walker::getPort(), X86ISA::Walker::getPort(), SimpleMemory::getPort(), DRAMSim2::getPort(), SMMUv3::getPort(), DRAMsim3::getPort(), BaseCPU::getPort(), X86ISA::Interrupts::getPort(), DistEtherLink::getPort(), BaseTrafficGen::getPort(), SimpleMemobj::getPort(), SCMI::Platform::getPort(), SerialLink::getPort(), Bridge::getPort(), SimpleCache::getPort(), BaseXBar::getPort(), MemCtrl::getPort(), ComputeUnit::getPort(), ArmISA::TableWalker::getPort(), and BaseCache::getPort().

getProbeManager()

ProbeManager * SimObject::getProbeManager

(

)

Get the probe manager for this object.

Probes generate traces. A trace is a file that keeps a log of events. For example, we can have a probe listener for an address and the trace will be a file that has time stamps for all the reads and writes to that address.

Definition at line 114 of file sim_object.cc.

References SimObject::probeManager.

Referenced by Prefetcher::Base::addEventProbe(), Prefetcher::PIF::addEventProbeRetiredInsts(), BPredUnit::pmuProbePoint(), BaseCPU::pmuProbePoint(), Compressor::FrequentValues::regProbeListeners(), Prefetcher::Base::regProbeListeners(), CommMonitor::regProbePoints(), PowerModel::regProbePoints(), AtomicSimpleCPU::regProbePoints(), BaseCPU::regProbePoints(), ArmISA::TLB::regProbePoints(), BaseCache::regProbePoints(), and ThermalDomain::setSubSystem().

init()

void SimObject::init ( )

virtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented in NVMInterface, BaseCache, MultiperspectivePerceptron, ArmISA::TableWalker, DRAMInterface, MemCtrl, IGbE, ComputeUnit, Bridge, BaseCPU, StatisticalCorrector, LoopPredictor, BaseTrafficGen, DmaDevice, ArmISA::TLB, DistEtherLink, MultiperspectivePerceptronTAGE, DRAMsim3, X86ISA::Interrupts, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, DRAMSim2, SimpleMemory, SMMUv3, CpuLocalTimer, RubyPort, QoS::MemSinkCtrl, Clint, ExternalSlave, EnergyCtrl, PioDevice, Plic, ExternalMaster, MinorCPU, TrafficGen, ProtocolTester, Gicv3, RubyTester, Iris::BaseCPU, BaseSimpleCPU, CheckerCPU, X86ISA::I82094AA, RubySystem, BaseKvmCPU, RubyDirectedTester, CommMonitor, Process, BaseGic, LTAGE, MemCheckerMonitor, MemDelay, QoS::Policy, AddrMapper, TAGEBase, QoS::FixedPriorityPolicy, DMASequencer, GarnetSyntheticTraffic, Pc, AtomicSimpleCPU, TimingSimpleCPU, NoMaliGpu, sc_gem5::Kernel, X86ISA::I8259, CoherentXBar, SerialLink, Wavefront, Shader, TraceCPU, GarnetExtLink, AbstractController, SimPoint, Switch, RubyPortProxy, CacheMemory, Router, SimpleNetwork, DirectoryMemory, WireBuffer, GarnetNetwork, EtherDump, BasicLink, GarnetIntLink, and BasicRouter.

Definition at line 70 of file sim_object.cc.

Referenced by GarnetNetwork::init(), SimpleNetwork::init(), LTAGE::init(), QoS::MemSinkCtrl::init(), SimpleMemory::init(), DRAMSim2::init(), DRAMsim3::init(), BaseTrafficGen::init(), CoherentXBar::init(), DRAMInterface::init(), NVMInterface::init(), CxxConfigManager::instantiate(), and BaseTags::BaseTagStats::regStats().

memInvalidate()

virtual void SimObject::memInvalidate ( )

inlinevirtual

Invalidate the contents of memory buffers.

When the switching to hardware virtualized CPU models, we need to make sure that we don't have any cached state in the system that might become stale when we return. This method is used to flush all such state back to main memory.

@warn This does not cause any dirty state to be written back to memory.

Reimplemented in BaseCache, and BaseTLB.

Definition at line 311 of file sim_object.hh.

memWriteback()

virtual void SimObject::memWriteback ( )

inlinevirtual

Write back dirty buffers to memory using functional writes.

After returning, an object implementing this method should have written all its dirty data back to memory. This method is typically used to prepare a system with caches for checkpointing.

Reimplemented in BaseCache, MinorCPU, and RubySystem.

Definition at line 296 of file sim_object.hh.

name()

virtual const std::string SimObject::name ( ) const

inlinevirtual

Reimplemented in ElasticTrace, and SimpleTrace.

Definition at line 182 of file sim_object.hh.

References SimObject::params().

Referenced by System::_getRequestorId(), Terminal::accept(), VncServer::accept(), Cache::access(), BaseCache::access(), ArmISA::PMU::addEventProbe(), Prefetcher::Base::addEventProbe(), Prefetcher::PIF::addEventProbeRetiredInsts(), PowerDomain::addFollower(), NetworkInterface::addInPort(), Router::addInPort(), ProbeManager::addListener(), ArmISA::PMU::RegularEvent::addMicroarchitectureProbe(), NetworkInterface::addOutPort(), ProbeManager::addPoint(), HSADriver::allocateQueue(), SMMUv3DeviceInterface::atsRecvAtomic(), SMMUv3DeviceInterface::atsRecvTimingReq(), HSADevice::attachDriver(), CxxConfigManager::bindPort(), CxxConfigManager::bindRequestPort(), NetworkInterface::calculateVC(), ArmSemihosting::callTmpNam(), X86ISA::I8237::Channel::ChannelAddrReg::ChannelAddrReg(), X86ISA::I8237::Channel::ChannelRemainingReg::ChannelRemainingReg(), TraceCPU::checkAndSchedExitEvent(), Trace::X86NativeTrace::checkR11Reg(), Trace::X86NativeTrace::checkRcxReg(), DVFSHandler::clkPeriodAtPerfLevel(), SrcClockDomain::clockPeriod(), RealViewOsc::clockPeriod(), CoherentXBar::CoherentXBar(), MemTest::completeRequest(), GenericTimer::CoreTimers::CoreTimers(), Sinic::Base::cpuIntrPost(), NSGigE::cpuIntrPost(), OutputUnit::decrement_credit(), Linux::devRandom(), DistEtherLink::DistEtherLink(), Pl111::dmaDone(), BaseStackTrace::dump(), FUPool::dump(), ArmKvmCPU::dumpKvmStateCoProc(), PciIoBar::EndBitUnion(), MessageBuffer::enqueue(), EtherLink::EtherLink(), EtherSwitch::EtherSwitch(), X86ISA::GpuTLB::exitCallback(), ComputeUnit::exitCallback(), SimObject::find(), BaseXBar::findPort(), BaseCache::functionalAccess(), HSADevice::functionalReadHsaSignal(), GicV2::getCpuTarget(), SMMUv3DeviceInterface::getPort(), FastModel::GIC::getPort(), SMMUv3::getPort(), SimObject::getPort(), MathExprPowerModel::getStatValue(), ArmSemihosting::getSTDIO(), BaseCache::handleFill(), SimpleCache::handleRequest(), Cache::handleSnoop(), X86ISA::I8042::I8042(), X86ISA::I82094AA::I82094AA(), X86ISA::I8254::I8254(), X86ISA::I8259::I8259(), OutputUnit::increment_credit(), InputUnit::increment_credit(), AbstractController::init(), ExternalMaster::init(), PioDevice::init(), ExternalSlave::init(), TraceCPU::init(), CpuLocalTimer::init(), DRAMSim2::init(), DRAMsim3::init(), DmaDevice::init(), BaseTrafficGen::init(), CoherentXBar::init(), MemCtrl::init(), DRAMInterface::init(), BaseCache::init(), Process::initState(), AbstractMemory::initState(), System::leafRequestorName(), Terminal::listen(), VncServer::listen(), Sequencer::llscLoadLinked(), Sequencer::llscStoreConditional(), SimObject::loadState(), System::lookupRequestorId(), GarnetNetwork::makeExtInLink(), GarnetNetwork::makeExtOutLink(), GarnetNetwork::makeInternalLink(), AbstractController::mapAddressToDownstreamMachine(), MemTraceProbe::MemTraceProbe(), SMMUDeviceRetryEvent::name(), SimpleTrace::name(), SCMI::Protocol::name(), CopyEngine::CopyEngineChannel::name(), ElasticTrace::name(), SimpleThread::name(), VirtIOConsole::TermRecvQueue::name(), RiscvISA::Walker::WalkerState::name(), X86ISA::Walker::WalkerState::name(), VirtIOConsole::TermTransQueue::name(), BaseRemoteGDB::name(), VirtIO9PBase::FSQueue::name(), VirtIOBlock::RequestQueue::name(), ItsProcess::name(), ArmISA::TableWalker::WalkerState::name(), Network::Network(), NoncoherentXBar::NoncoherentXBar(), BaseTrafficGen::noProgress(), MemTest::noRequest(), MemTest::noResponse(), Linux::openSpecialFile(), TrafficGen::parseConfig(), PciMemBar::PciMemBar(), VoltageDomain::perfLevel(), SrcClockDomain::perfLevel(), Minor::Pipeline::Pipeline(), BPredUnit::pmuProbePoint(), BaseCPU::pmuProbePoint(), PowerDomain::PowerDomain(), BasicRouter::print(), SimpleExtLink::print(), GarnetIntLink::print(), BasicLink::print(), SimpleIntLink::print(), GarnetExtLink::print(), RubyPrefetcher::print(), CacheMemory::print(), MessageBuffer::print(), System::printSystems(), CPUProgressEvent::process(), TLBCoalescer::processProbeTLBEvent(), ProtocolTester::ProtocolTester(), PowerDomain::pwrStateChangeCallback(), HDLcd::pxlFrameDone(), AmbaFake::read(), IsaFake::read(), UFSHostDevice::readCallback(), PciDevice::readConfig(), UFSHostDevice::readDevice(), IdeDisk::readDisk(), CacheMemory::recordCacheContents(), SMMUv3DeviceInterface::recvAtomic(), NoncoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicBackdoor(), CoherentXBar::recvAtomicSnoop(), NoncoherentXBar::recvFunctional(), SimpleMemory::recvFunctional(), SerialLink::SerialLinkResponsePort::recvFunctional(), DRAMSim2::recvFunctional(), Bridge::BridgeResponsePort::recvFunctional(), DRAMsim3::recvFunctional(), QoS::MemSinkCtrl::recvFunctional(), CoherentXBar::recvFunctional(), CoherentXBar::recvFunctionalSnoop(), EtherSwitch::Interface::recvPacket(), BaseXBar::recvRangeChange(), SMMUv3DeviceInterface::recvTimingReq(), CoherentXBar::recvTimingReq(), MemCheckerMonitor::recvTimingResp(), AddrMapper::recvTimingResp(), BaseCache::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), HWScheduler::registerNewQueue(), BaseCPU::registerThreadContexts(), HTMSequencer::regStats(), Compressor::BaseDictionaryCompressor::DictionaryStats::regStats(), GarnetNetwork::regStats(), Router::regStats(), QoS::MemCtrl::MemCtrlStats::regStats(), BaseCPU::regStats(), BaseXBar::regStats(), ProbeManager::removeListener(), UFSHostDevice::requestHandler(), TrafficGen::resolveFile(), RubyPort::RubyPort(), VoltageDomain::sanitiseVoltages(), NetworkInterface::scheduleFlit(), RubySystem::serialize(), CowDiskImage::serialize(), BaseTrafficGen::serialize(), SimObject::serializeAll(), Cache::serviceMSHRTargets(), PowerState::set(), PowerState::setControlledDomain(), WireBuffer::setDescription(), PowerDomain::setFollowerPowerStates(), LdsState::setParent(), ArmISA::TLB::setTestInterface(), Shader::ShaderStats::ShaderStats(), SimpleCache::SimpleCache(), SrcClockDomain::SrcClockDomain(), MemTraceProbe::startup(), PowerDomain::startup(), BaseKvmCPU::startup(), ArmISA::FsLinux::startup(), VoltageDomain::startup(), System::stripSystemName(), HSADevice::submitAgentDispatchPkt(), HSADevice::submitDispatchPkt(), HSADevice::submitVendorPkt(), GarnetSyntheticTraffic::tick(), MemTest::tick(), Prefetcher::Queued::translationComplete(), DrainManager::tryDrain(), RubyPort::trySendRetries(), Sinic::Base::unserialize(), BaseTrafficGen::unserialize(), NSGigE::unserialize(), BaseTrafficGen::update(), DerivedClockDomain::updateClockPeriod(), HSADevice::updateHsaSignal(), TraceCPU::updateNumOps(), UncoalescedTable::updateResources(), VncInput::VncInput(), VoltageDomain::voltage(), DVFSHandler::voltageAtPerfLevel(), VoltageDomain::VoltageDomain(), InputUnit::wakeup(), NetworkLink::wakeup(), AmbaFake::write(), IsaFake::write(), PciDevice::writeConfig(), UFSHostDevice::writeDevice(), and IdeDisk::writeDisk().

params()

const Params& SimObject::params ( ) const

inline

Returns

This function returns the cached copy of the object parameters.

Definition at line 168 of file sim_object.hh.

References SimObject::_params.

Referenced by Switch::addOutPort(), ArmProcess::ArmProcess(), BPredUnit::BPredUnit(), ArmISA::ISA::clear(), GarnetNetwork::collateStats(), VirtIO9PSocket::connectSocket(), FastModel::CortexR52Cluster::CortexR52Cluster(), Iris::CPU< CortexA76TC >::CPU(), GenericTimer::createTimers(), SMMUv3DeviceInterface::drain(), ArmISA::TableWalker::drainResume(), PseudoInst::dumpresetstats(), PseudoInst::dumpstats(), MaltaIO::frequency(), ArmPPIGen::get(), System::getGuestByteOrder(), IdeController::IdeController(), AbstractController::init(), MinorCPU::init(), CpuLocalTimer::init(), BaseCPU::init(), MultiperspectivePerceptron::init(), RiscvISA::FsLinux::initState(), FastModel::CortexA76::initState(), ArmISA::FsFreebsd::initState(), KernelWorkload::initState(), ArmISA::FsLinux::initState(), ArmISA::FsWorkload::initState(), AbstractMemory::initState(), Iob::Iob(), AbstractMemory::isNull(), KernelWorkload::KernelWorkload(), KvmVM::KvmVM(), LdsState::LdsState(), PseudoInst::loadsymbol(), PseudoInst::m5checkpoint(), MinorCPU::MinorCPU(), MipsProcess::MipsProcess(), CommMonitor::MonitorStats::MonitorStats(), SimObject::name(), Network::Network(), RawDiskImage::notifyFork(), CowDiskImage::notifyFork(), PowerProcess::PowerProcess(), Process::Process(), AmbaFake::read(), IsaFake::read(), RealViewCtrl::read(), NSGigE::read(), PseudoInst::readfile(), RubySystem::registerRequestorIDs(), BaseMemProbe::regProbeListeners(), Sinic::Device::reset(), PseudoInst::resetstats(), RiscvProcess::RiscvProcess(), FastModel::CortexR52::set_evs_param(), FastModel::CortexA76::set_evs_param(), FastModel::CortexR52::setCluster(), FastModel::CortexA76::setCluster(), CheckerCPU::setSystem(), ArmISA::PMU::setThreadContext(), SimpleCache::SimpleCache(), SimpleIndirectPredictor::SimpleIndirectPredictor(), SMMUv3::SMMUv3(), SparcProcess::SparcProcess(), StackDistProbe::StackDistProbeStats::StackDistProbeStats(), VirtIO9PDiod::startDiod(), BaseArmKvmCPU::startup(), BaseKvmCPU::startup(), ArmISA::FsLinux::startup(), Root::startup(), BaseCPU::startup(), BaseKvmCPU::startupThread(), System::System(), Topology::Topology(), Process::tryLoaders(), VirtIO9PBase::VirtIO9PBase(), BaseCPU::waitForRemoteGDB(), PseudoInst::workbegin(), PseudoInst::workend(), AmbaFake::write(), IsaFake::write(), and IGbE::write().

regProbeListeners()

void SimObject::regProbeListeners ( )

virtual

Register probe listeners for this object.

No probe listeners by default, so do nothing in base.

Reimplemented in Prefetcher::Base, Compressor::FrequentValues, ArmISA::PMU, BaseMemProbe, ElasticTrace, SimPoint, and SimpleTrace.

Definition at line 109 of file sim_object.cc.

Referenced by CxxConfigManager::instantiate().

regProbePoints()

void SimObject::regProbePoints ( )

virtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented in BaseCache, ArmISA::TLB, BaseCPU, AtomicSimpleCPU, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, CommMonitor, BPredUnit, and PowerModel.

Definition at line 101 of file sim_object.cc.

Referenced by CxxConfigManager::instantiate().

SimObject()

SimObject::SimObject

(

const Params &

p

)

Definition at line 52 of file sim_object.cc.

References SimObject::probeManager, and SimObject::simObjectList.

startup()

void SimObject::startup ( )

virtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented in DRAMInterface, ArmISA::ISA, MemCtrl, BaseCPU, SrcClockDomain, DistEtherLink, System, DRAMsim3, RealViewOsc, FullO3CPU< Impl >, FullO3CPU< O3CPUImpl >, DRAMSim2, Prefetcher::AccessMapPatternMatching, MuxingKvmGic, ThermalModel, Root, EnergyCtrl, MaltaIO, MinorCPU, X86ISA::I8254, VoltageDomain, ArmISA::FsLinux, X86ISA::Cmos, FVPBasePwrCtrl, RubySystem, ArmV8KvmCPU, MathExprPowerModel, BaseKvmCPU, RiscvRTC, CommMonitor, PowerDomain, MemTraceProbe, BaseArmKvmCPU, sc_gem5::Kernel, X86KvmCPU, VirtIO9PSocket, VirtIO9PDiod, HelloObject, and ArmKvmCPU.

Definition at line 93 of file sim_object.cc.

Referenced by FVPBasePwrCtrl::startup(), ArmISA::FsLinux::startup(), MuxingKvmGic::startup(), System::startup(), CxxConfigManager::startup(), and ArmISA::ISA::startup().

Variable Documentation

_params

const SimObjectParams& SimObject::_params

protected

Cached copy of the object parameters.

Definition at line 159 of file sim_object.hh.

Referenced by PMAChecker::params(), BaseGic::params(), and SimObject::params().