hybrid_gen.hh

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/*
 * Copyright (c) 2020 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed here under.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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#ifndef __CPU_TRAFFIC_GEN_HYBRID_GEN_HH__
#define __CPU_TRAFFIC_GEN_HYBRID_GEN_HH__
 
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "base_gen.hh"
#include "enums/AddrMap.hh"
#include "mem/packet.hh"
 
class HybridGen : public BaseGen
{
 
  public:
 
    HybridGen(SimObject &obj,
           RequestorID requestor_id, Tick _duration,
           Addr start_addr_dram, Addr end_addr_dram,
           Addr blocksize_dram,
           Addr start_addr_nvm, Addr end_addr_nvm,
           Addr blocksize_nvm,
           Addr cacheline_size,
           Tick min_period, Tick max_period,
           uint8_t read_percent, Addr data_limit,
           unsigned int num_seq_pkts_dram, unsigned int page_size_dram,
           unsigned int nbr_of_banks_dram, unsigned int nbr_of_banks_util_dram,
           unsigned int num_seq_pkts_nvm, unsigned int buffer_size_nvm,
           unsigned int nbr_of_banks_nvm, unsigned int nbr_of_banks_util_nvm,
           Enums::AddrMap addr_mapping,
           unsigned int nbr_of_ranks_dram,
           unsigned int nbr_of_ranks_nvm,
           uint8_t nvm_percent);
 
    void enter();
 
    PacketPtr getNextPacket();
 
    void genStartAddr(unsigned int new_bank , unsigned int new_rank);
 
    Tick nextPacketTick(bool elastic, Tick delay) const;
 
  protected:
    const Addr startAddrDram;
 
    const Addr endAddrDram;
 
    const Addr blocksizeDram;
 
    const Addr startAddrNvm;
 
    const Addr endAddrNvm;
 
    const Addr blocksizeNvm;
 
    const Addr cacheLineSize;
 
    const Tick minPeriod;
    const Tick maxPeriod;
 
    const uint8_t readPercent;
 
    const Addr dataLimit;
 
    const unsigned int numSeqPktsDram;
    const unsigned int numSeqPktsNvm;
 
    unsigned int countNumSeqPkts;
 
    Addr addr;
 
    const unsigned int pageSizeDram;
 
    const unsigned int pageBitsDram;
 
    const unsigned int bankBitsDram;
 
    const unsigned int blockBitsDram;
 
    const unsigned int nbrOfBanksDram;
 
    const unsigned int nbrOfBanksUtilDram;
 
    const unsigned int bufferSizeNvm;
 
    const unsigned int pageBitsNvm;
 
    const unsigned int bankBitsNvm;
 
    const unsigned int blockBitsNvm;
 
    const unsigned int nbrOfBanksNvm;
 
    const unsigned int nbrOfBanksUtilNvm;
 
    Enums::AddrMap addrMapping;
 
    const unsigned int nbrOfRanksDram;
 
    const unsigned int rankBitsDram;
 
    const unsigned int nbrOfRanksNvm;
 
    const unsigned int rankBitsNvm;
 
    const uint8_t nvmPercent;
 
    bool isRead;
 
    bool isNvm;
 
    Addr dataManipulated;
 
    unsigned int numSeqPkts;
 
    Addr startAddr;
 
    Addr endAddr;
 
    Addr blocksize;
 
    unsigned int pageSize;
 
    unsigned int pageBits;
 
    unsigned int bankBits;
 
    unsigned int blockBits;
 
    unsigned int nbrOfBanks;
 
    unsigned int nbrOfBanksUtil;
 
    unsigned int nbrOfRanks;
 
    unsigned int rankBits;
 
};
 
#endif