mem_sink.hh

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/*
 * Copyright (c) 2018-2020 ARM Limited
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 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
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 * this software without specific prior written permission.
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 * Author: Matteo Andreozzi
 */
 
 
#ifndef __MEM_QOS_MEM_SINK_HH__
#define __MEM_QOS_MEM_SINK_HH__
 
#include "mem/abstract_mem.hh"
#include "mem/qos/mem_ctrl.hh"
#include "mem/qport.hh"
#include "params/QoSMemSinkCtrl.hh"
 
struct QoSMemSinkInterfaceParams;
class QoSMemSinkInterface;
 
namespace QoS {
 
class MemSinkCtrl : public MemCtrl
{
  protected:
    using PacketQueue = std::deque<PacketPtr>;
 
  private:
    class MemoryPort : public QueuedResponsePort
    {
      private:
        MemSinkCtrl& memory;
 
        RespPacketQueue queue;
 
      public:
        MemoryPort(const std::string&, MemSinkCtrl&);
 
      protected:
        Tick recvAtomic(PacketPtr pkt);
 
        void recvFunctional(PacketPtr pkt);
 
        bool recvTimingReq(PacketPtr pkt);
 
        AddrRangeList getAddrRanges() const;
 
    };
 
  public:
    MemSinkCtrl(const QoSMemSinkCtrlParams &);
 
    virtual ~MemSinkCtrl();
 
    DrainState drain() override;
 
    Port &getPort(const std::string &if_name, PortID=InvalidPortID) override;
 
    void init() override;
 
  protected:
    const Tick requestLatency;
 
    const Tick responseLatency;
 
    const uint64_t memoryPacketSize;
 
    const uint64_t readBufferSize;
 
    const uint64_t writeBufferSize;
 
    MemoryPort port;
 
    QoSMemSinkInterface* const interface;
 
    bool retryRdReq;
 
    bool retryWrReq;
 
    Tick nextRequest;
 
    struct MemSinkCtrlStats : public Stats::Group
    {
        MemSinkCtrlStats(Stats::Group *parent);
 
        Stats::Scalar numReadRetries;
 
        Stats::Scalar numWriteRetries;
    };
 
    std::vector<PacketQueue> readQueue;
 
    std::vector<PacketQueue> writeQueue;
 
    void processNextReqEvent();
 
    EventWrapper<
        MemSinkCtrl,
        &MemSinkCtrl::processNextReqEvent> nextReqEvent;
 
    inline bool readQueueFull(const uint64_t packets) const;
 
    inline bool writeQueueFull(const uint64_t packets) const;
 
    Tick recvAtomic(PacketPtr pkt);
 
    void recvFunctional(PacketPtr pkt);
 
    bool recvTimingReq(PacketPtr pkt);
 
    MemSinkCtrlStats stats;
};
 
} // namespace QoS
 
class QoSMemSinkInterface : public AbstractMemory
{
  public:
    void setMemCtrl(QoS::MemSinkCtrl* _ctrl) { ctrl = _ctrl; };
 
    QoS::MemSinkCtrl* ctrl;
 
    QoSMemSinkInterface(const QoSMemSinkInterfaceParams &_p);
};
 
 
#endif /* __MEM_QOS_MEM_SINK_HH__ */