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tlbi_op.cc
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37 
38 #include "arch/arm/tlbi_op.hh"
39 
40 #include "arch/arm/mmu.hh"
41 #include "cpu/checker/cpu.hh"
42 
43 namespace ArmISA {
44 
45 void
46 TLBIALL::operator()(ThreadContext* tc)
47 {
48  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
49  inHost = (hcr.tge == 1 && hcr.e2h == 1);
50  el2Enabled = EL2Enabled(tc);
51 
52  getMMUPtr(tc)->flush(*this);
53 
54  // If CheckerCPU is connected, need to notify it of a flush
55  CheckerCPU *checker = tc->getCheckerCpuPtr();
56  if (checker) {
57  getMMUPtr(checker)->flush(*this);
58  }
59 }
60 
61 void
62 ITLBIALL::operator()(ThreadContext* tc)
63 {
64  el2Enabled = EL2Enabled(tc);
65  getMMUPtr(tc)->iflush(*this);
66 }
67 
68 void
69 DTLBIALL::operator()(ThreadContext* tc)
70 {
71  el2Enabled = EL2Enabled(tc);
72  getMMUPtr(tc)->dflush(*this);
73 }
74 
75 void
76 TLBIALLEL::operator()(ThreadContext* tc)
77 {
78  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
79  inHost = (hcr.tge == 1 && hcr.e2h == 1);
80  getMMUPtr(tc)->flush(*this);
81 
82  // If CheckerCPU is connected, need to notify it of a flush
83  CheckerCPU *checker = tc->getCheckerCpuPtr();
84  if (checker) {
85  getMMUPtr(checker)->flush(*this);
86  }
87 }
88 
89 void
90 TLBIVMALL::operator()(ThreadContext* tc)
91 {
92  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
93  inHost = (hcr.tge == 1 && hcr.e2h == 1);
94 
95  getMMUPtr(tc)->flush(*this);
96 
97  // If CheckerCPU is connected, need to notify it of a flush
98  CheckerCPU *checker = tc->getCheckerCpuPtr();
99  if (checker) {
100  getMMUPtr(checker)->flush(*this);
101  }
102 }
103 
104 void
105 TLBIASID::operator()(ThreadContext* tc)
106 {
107  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
108  inHost = (hcr.tge == 1 && hcr.e2h == 1);
109  el2Enabled = EL2Enabled(tc);
110 
111  getMMUPtr(tc)->flush(*this);
112  CheckerCPU *checker = tc->getCheckerCpuPtr();
113  if (checker) {
114  getMMUPtr(checker)->flush(*this);
115  }
116 }
117 
118 void
119 ITLBIASID::operator()(ThreadContext* tc)
120 {
121  el2Enabled = EL2Enabled(tc);
122  getMMUPtr(tc)->iflush(*this);
123 }
124 
125 void
126 DTLBIASID::operator()(ThreadContext* tc)
127 {
128  el2Enabled = EL2Enabled(tc);
129  getMMUPtr(tc)->dflush(*this);
130 }
131 
132 void
133 TLBIALLN::operator()(ThreadContext* tc)
134 {
135  getMMUPtr(tc)->flush(*this);
136 
137  CheckerCPU *checker = tc->getCheckerCpuPtr();
138  if (checker) {
139  getMMUPtr(checker)->flush(*this);
140  }
141 }
142 
143 void
144 TLBIMVAA::operator()(ThreadContext* tc)
145 {
146  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
147  inHost = (hcr.tge == 1 && hcr.e2h == 1);
148  getMMUPtr(tc)->flush(*this);
149 
150  CheckerCPU *checker = tc->getCheckerCpuPtr();
151  if (checker) {
152  getMMUPtr(checker)->flush(*this);
153  }
154 }
155 
156 void
157 TLBIMVA::operator()(ThreadContext* tc)
158 {
159  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
160  inHost = (hcr.tge == 1 && hcr.e2h == 1);
161  getMMUPtr(tc)->flush(*this);
162 
163  CheckerCPU *checker = tc->getCheckerCpuPtr();
164  if (checker) {
165  getMMUPtr(checker)->flush(*this);
166  }
167 }
168 
169 void
170 ITLBIMVA::operator()(ThreadContext* tc)
171 {
172  getMMUPtr(tc)->iflush(*this);
173 }
174 
175 void
176 DTLBIMVA::operator()(ThreadContext* tc)
177 {
178  getMMUPtr(tc)->dflush(*this);
179 }
180 
181 void
182 TLBIIPA::operator()(ThreadContext* tc)
183 {
184  getMMUPtr(tc)->flush(*this);
185 
186  CheckerCPU *checker = tc->getCheckerCpuPtr();
187  if (checker) {
188  getMMUPtr(checker)->flush(*this);
189  }
190 }
191 
192 } // namespace ArmISA
ArmISA::TLBIALL::inHost
bool inHost
Definition: tlbi_op.hh:95
ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:314
ArmISA::DTLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:126
ArmISA::MMU::flush
void flush(const OP &tlbi_op)
Definition: mmu.hh:84
ArmISA::TLBIALLEL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:76
CheckerCPU
CheckerCPU class.
Definition: cpu.hh:85
ArmISA::getMMUPtr
MMU * getMMUPtr(T *tc)
Definition: mmu.hh:113
ArmISA::TLBIMVAA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:144
ArmISA
Definition: ccregs.hh:41
ArmISA::TLBIALL::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:96
ArmISA::TLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:46
ArmISA::MMU::dflush
void dflush(const OP &tlbi_op)
Definition: mmu.hh:99
ArmISA::TLBIMVA::inHost
bool inHost
Definition: tlbi_op.hh:254
mmu.hh
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
ArmISA::TLBIASID::el2Enabled
bool el2Enabled
Definition: tlbi_op.hh:179
ArmISA::ITLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:119
ArmISA::TLBIMVAA::inHost
bool inHost
Definition: tlbi_op.hh:237
cpu.hh
tlbi_op.hh
ArmISA::ITLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:62
ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: miscregs.hh:582
ArmISA::TLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:157
ArmISA::TLBIALLEL::inHost
bool inHost
Definition: tlbi_op.hh:141
ArmISA::TLBIALLN::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:133
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
ArmISA::DTLBIALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:69
ArmISA::DTLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:176
ArmISA::TLBIASID::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:105
ArmISA::TLBIVMALL::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:90
ArmISA::TLBIASID::inHost
bool inHost
Definition: tlbi_op.hh:178
ArmISA::ITLBIMVA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:170
ArmISA::TLBIVMALL::inHost
bool inHost
Definition: tlbi_op.hh:161
ArmISA::MMU::iflush
void iflush(const OP &tlbi_op)
Definition: mmu.hh:92
ArmISA::TLBIIPA::operator()
void operator()(ThreadContext *tc) override
Definition: tlbi_op.cc:182
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