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ArmISA::TLBIIPA Class Reference

TLB Invalidate by Intermediate Physical Address. More...

#include <tlbi_op.hh>

Inheritance diagram for ArmISA::TLBIIPA:
ArmISA::TLBIOp

Public Member Functions

 TLBIIPA (ExceptionLevel _targetEL, bool _secure, Addr _addr)
 
void operator() (ThreadContext *tc) override
 
TLBIMVAA makeStage2 () const
 TLBIIPA is basically a TLBIMVAA for stage2 TLBs. More...
 
- Public Member Functions inherited from ArmISA::TLBIOp
 TLBIOp (ExceptionLevel _targetEL, bool _secure)
 
virtual ~TLBIOp ()
 
void broadcast (ThreadContext *tc)
 Broadcast the TLB Invalidate operation to all TLBs in the Arm system. More...
 

Public Attributes

Addr addr
 
- Public Attributes inherited from ArmISA::TLBIOp
bool secureLookup
 
ExceptionLevel targetEL
 

Detailed Description

TLB Invalidate by Intermediate Physical Address.

Definition at line 286 of file tlbi_op.hh.

Constructor & Destructor Documentation

◆ TLBIIPA()

ArmISA::TLBIIPA::TLBIIPA ( ExceptionLevel  _targetEL,
bool  _secure,
Addr  _addr 
)
inline

Definition at line 289 of file tlbi_op.hh.

Member Function Documentation

◆ makeStage2()

TLBIMVAA ArmISA::TLBIIPA::makeStage2 ( ) const
inline

TLBIIPA is basically a TLBIMVAA for stage2 TLBs.

Definition at line 297 of file tlbi_op.hh.

References addr, ArmISA::EL1, and ArmISA::TLBIOp::secureLookup.

Referenced by ArmISA::TLB::flush().

◆ operator()()

void ArmISA::TLBIIPA::operator() ( ThreadContext tc)
overridevirtual

Reimplemented from ArmISA::TLBIOp.

Definition at line 182 of file tlbi_op.cc.

References ArmISA::MMU::flush(), ThreadContext::getCheckerCpuPtr(), and ArmISA::getMMUPtr().

Member Data Documentation

◆ addr

Addr ArmISA::TLBIIPA::addr

Definition at line 302 of file tlbi_op.hh.

Referenced by makeStage2().


The documentation for this class was generated from the following files:

Generated on Tue Jun 22 2021 15:28:49 for gem5 by doxygen 1.8.17