gem5  v21.1.0.2
HTMSequencer.hh
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37 
38 #ifndef __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__
39 #define __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__
40 
41 #include <cassert>
42 #include <iostream>
43 
44 #include "mem/htm.hh"
45 #include "mem/ruby/protocol/HtmCallbackMode.hh"
46 #include "mem/ruby/protocol/HtmFailedInCacheReason.hh"
49 #include "params/RubyHTMSequencer.hh"
50 
51 namespace gem5
52 {
53 
54 namespace ruby
55 {
56 
57 class HTMSequencer : public Sequencer
58 {
59  public:
60  HTMSequencer(const RubyHTMSequencerParams &p);
61  ~HTMSequencer();
62 
63  // callback to acknowledge HTM requests and
64  // notify cpu core when htm transaction fails in cache
65  void htmCallback(Addr,
66  const HtmCallbackMode,
67  const HtmFailedInCacheReason);
68 
69  bool empty() const override;
70  void print(std::ostream& out) const override;
71  void regStats() override;
72  void wakeup() override;
73 
74  private:
84  HtmCacheFailure htmRetCodeConversion(const HtmFailedInCacheReason rc);
85 
86  void rubyHtmCallback(PacketPtr pkt, const HtmFailedInCacheReason fail_r);
87 
88  RequestStatus insertRequest(PacketPtr pkt,
89  RubyRequestType primary_type,
90  RubyRequestType secondary_type) override;
91 
92  // Private copy constructor and assignment operator
93  HTMSequencer(const HTMSequencer& obj);
94  HTMSequencer& operator=(const HTMSequencer& obj);
95 
96  // table/queue for hardware transactional memory commands
97  // these do not have an address so a deque/queue is used instead.
99 
102 
109 };
110 
111 inline std::ostream&
112 operator<<(std::ostream& out, const HTMSequencer& obj)
113 {
114  obj.print(out);
115  out << std::flush;
116  return out;
117 }
118 
119 } // namespace ruby
120 } // namespace gem5
121 
122 #endif // __MEM_RUBY_SYSTEM_HTMSEQUENCER_HH__
gem5::ruby::HTMSequencer::~HTMSequencer
~HTMSequencer()
Definition: HTMSequencer.cc:106
gem5::ruby::Sequencer
Definition: Sequencer.hh:86
gem5::ruby::HTMSequencer::print
void print(std::ostream &out) const override
Definition: HTMSequencer.cc:334
gem5::ruby::operator<<
std::ostream & operator<<(std::ostream &os, const BoolVec &myvector)
Definition: BoolVec.cc:49
htm.hh
gem5::HtmCacheFailure
HtmCacheFailure
Definition: htm.hh:59
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::ruby::HTMSequencer
Definition: HTMSequencer.hh:57
gem5::ruby::HTMSequencer::regStats
void regStats() override
Callback to set stat parameters.
Definition: HTMSequencer.cc:213
gem5::ruby::HTMSequencer::htmRetCodeConversion
HtmCacheFailure htmRetCodeConversion(const HtmFailedInCacheReason rc)
Htm return code conversion.
Definition: HTMSequencer.cc:52
gem5::ruby::HTMSequencer::operator=
HTMSequencer & operator=(const HTMSequencer &obj)
gem5::ruby::HTMSequencer::m_htmstart_instruction
Counter m_htmstart_instruction
Definition: HTMSequencer.hh:101
gem5::ruby::HTMSequencer::m_htm_transaction_cycles
statistics::Histogram m_htm_transaction_cycles
Histogram of cycle latencies of HTM transactions.
Definition: HTMSequencer.hh:104
gem5::ruby::HTMSequencer::insertRequest
RequestStatus insertRequest(PacketPtr pkt, RubyRequestType primary_type, RubyRequestType secondary_type) override
Definition: HTMSequencer.cc:346
gem5::statistics::Histogram
A simple histogram stat.
Definition: statistics.hh:2123
gem5::ruby::HTMSequencer::m_htmstart_tick
Tick m_htmstart_tick
Definition: HTMSequencer.hh:100
gem5::PowerISA::rc
Bitfield< 0 > rc
Definition: types.hh:87
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ruby::HTMSequencer::htmCallback
void htmCallback(Addr, const HtmCallbackMode, const HtmFailedInCacheReason)
Definition: HTMSequencer.cc:111
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ruby::HTMSequencer::empty
bool empty() const override
Definition: HTMSequencer.cc:313
gem5::ruby::HTMSequencer::m_htmCmdRequestTable
std::deque< SequencerRequest * > m_htmCmdRequestTable
Definition: HTMSequencer.hh:98
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ruby::HTMSequencer::m_htm_transaction_instructions
statistics::Histogram m_htm_transaction_instructions
Histogram of instruction lengths of HTM transactions.
Definition: HTMSequencer.hh:106
gem5::ruby::HTMSequencer::HTMSequencer
HTMSequencer(const RubyHTMSequencerParams &p)
Definition: HTMSequencer.cc:69
gem5::ruby::HTMSequencer::rubyHtmCallback
void rubyHtmCallback(PacketPtr pkt, const HtmFailedInCacheReason fail_r)
Definition: HTMSequencer.cc:247
gem5::ruby::HTMSequencer::wakeup
void wakeup() override
Definition: HTMSequencer.cc:283
std::deque
STL deque class.
Definition: stl.hh:44
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::ruby::HTMSequencer::m_htm_transaction_abort_cause
statistics::Vector m_htm_transaction_abort_cause
Causes for HTM transaction aborts.
Definition: HTMSequencer.hh:108
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
RubyPort.hh
Sequencer.hh

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