gem5  v21.1.0.2
types.hh
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29 
30 #ifndef __ARCH_POWER_TYPES_HH__
31 #define __ARCH_POWER_TYPES_HH__
32 
33 #include <cstdint>
34 
35 #include "arch/power/pcstate.hh"
36 #include "base/bitunion.hh"
37 
38 namespace gem5
39 {
40 
41 namespace PowerISA
42 {
43 
44 typedef uint32_t MachInst;
45 
47 
48  // Registers
49  Bitfield<25, 21> rs;
50  Bitfield<20, 16> ra;
51 
52  // Shifts and masks
53  Bitfield<15, 11> sh;
54  Bitfield<1> shn;
55  Bitfield<10, 6> mb;
56  Bitfield<5> mbn;
57  Bitfield< 5, 1> me;
58  Bitfield<5> men;
59 
60  // Immediate fields
61  Bitfield<15, 0> si;
62  Bitfield<15, 0> ui;
63  Bitfield<15, 0> d;
64  Bitfield<15, 2> ds;
65  Bitfield<15, 6> d0;
66  Bitfield<20, 16> d1;
67  Bitfield< 1, 0> d2;
68 
69  // Compare fields
70  Bitfield<21> l;
71 
72  // Special purpose register identifier
73  Bitfield<20, 11> spr;
74  Bitfield<25, 23> bf;
75  Bitfield<20, 18> bfa;
76 
77  // Branch instruction fields
78  Bitfield<1> aa;
79  Bitfield<15, 2> bd;
80  Bitfield<20, 16> bi;
81  Bitfield<12, 11> bh;
82  Bitfield<25, 21> bo;
83  Bitfield<25, 2> li;
84  Bitfield<0> lk;
85 
86  // Record bits
87  Bitfield<0> rc;
88  Bitfield<10> oe;
89 
90  // Condition register fields
91  Bitfield<25, 21> bt;
92  Bitfield<20, 16> ba;
93  Bitfield<15, 11> bb;
94 
95  // Trap instruction fields
96  Bitfield<25, 21> to;
97 
98  // FXM field for mtcrf instruction
99  Bitfield<19, 12> fxm;
101 
102 // typedef uint64_t LargestRead;
103 // // Need to use 64 bits to make sure that read requests get handled properly
104 
105 // typedef int RegContextParam;
106 // typedef int RegContextVal;
107 
108 } // namespace PowerISA
109 } // namespace gem5
110 
112 
113 template<>
114 struct hash<gem5::PowerISA::ExtMachInst> : public hash<uint32_t>
115 {
116  size_t operator()(const gem5::PowerISA::ExtMachInst &emi) const {
117  return hash<uint32_t>::operator()((uint32_t)emi);
118  };
119 };
120 
121 } // namespace std
122 
123 #endif // __ARCH_POWER_TYPES_HH__
gem5::PowerISA::ui
Bitfield< 15, 0 > ui
Definition: types.hh:62
gem5::PowerISA::lk
Bitfield< 0 > lk
Definition: types.hh:84
gem5::PowerISA::fxm
Bitfield< 19, 12 > fxm
Definition: types.hh:99
gem5::PowerISA::d
Bitfield< 15, 0 > d
Definition: types.hh:63
gem5::PowerISA::ba
Bitfield< 20, 16 > ba
Definition: types.hh:92
gem5::SparcISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:42
gem5::PowerISA::bh
Bitfield< 12, 11 > bh
Definition: types.hh:81
gem5::PowerISA::bf
Bitfield< 25, 23 > bf
Definition: types.hh:74
gem5::PowerISA::bd
Bitfield< 15, 2 > bd
Definition: types.hh:79
gem5::PowerISA::bfa
Bitfield< 20, 18 > bfa
Definition: types.hh:75
gem5::PowerISA::bt
Bitfield< 25, 21 > bt
Definition: types.hh:91
gem5::PowerISA::bi
Bitfield< 20, 16 > bi
Definition: types.hh:80
gem5::PowerISA::men
Bitfield< 5 > men
Definition: types.hh:58
std::hash< gem5::PowerISA::ExtMachInst >::operator()
size_t operator()(const gem5::PowerISA::ExtMachInst &emi) const
Definition: types.hh:116
gem5::PowerISA::me
Bitfield< 12 > me
Definition: misc.hh:113
gem5::PowerISA::li
Bitfield< 25, 2 > li
Definition: types.hh:83
gem5::namespace
gem5::auxv::AuxVector< IntType > namespace
Definition: aux_vector.hh:136
gem5::PowerISA::to
Bitfield< 25, 21 > to
Definition: types.hh:96
gem5::PowerISA::rc
Bitfield< 0 > rc
Definition: types.hh:87
gem5::PowerISA::ds
Bitfield< 15, 2 > ds
Definition: types.hh:64
gem5::PowerISA::aa
Bitfield< 1 > aa
Definition: types.hh:78
gem5::PowerISA::mb
Bitfield< 10, 6 > mb
Definition: types.hh:55
pcstate.hh
gem5::PowerISA::ra
Bitfield< 20, 16 > ra
Definition: types.hh:50
gem5::PowerISA::sh
Bitfield< 15, 11 > sh
Definition: types.hh:53
gem5::PowerISA::oe
Bitfield< 7 > oe
Definition: misc.hh:95
gem5::PowerISA::bo
Bitfield< 25, 21 > bo
Definition: types.hh:82
bitunion.hh
gem5::PowerISA::d1
Bitfield< 20, 16 > d1
Definition: types.hh:66
gem5::PowerISA::d2
Bitfield< 1, 0 > d2
Definition: types.hh:67
gem5::PowerISA::si
Bitfield< 15, 0 > si
Definition: types.hh:61
gem5::PowerISA::spr
Bitfield< 20, 11 > spr
Definition: types.hh:73
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::PowerISA::MachInst
uint32_t MachInst
Definition: types.hh:44
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
gem5::PowerISA::bb
Bitfield< 15, 11 > bb
Definition: types.hh:93
gem5::PowerISA::EndBitUnion
EndBitUnion(Cr) BitUnion32(Xer) Bitfield< 31 > so
gem5::PowerISA::d0
Bitfield< 15, 6 > d0
Definition: types.hh:65
gem5::PowerISA::rs
rs
Definition: types.hh:49
gem5::PowerISA::mbn
Bitfield< 5 > mbn
Definition: types.hh:56
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PowerISA::BitUnion32
BitUnion32(Cr) SubBitUnion(cr0
gem5::PowerISA::shn
Bitfield< 1 > shn
Definition: types.hh:54
gem5::PowerISA::l
Bitfield< 21 > l
Definition: types.hh:70

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