gem5 v24.0.0.0
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Namespaces | |
namespace | garnet |
Typedefs | |
typedef std::vector< bool > | BoolVec |
typedef std::vector< int > | IntVec |
typedef unsigned int | LinkID |
typedef unsigned int | NodeID |
typedef unsigned int | SwitchID |
typedef std::string | PortDirection |
typedef std::vector< std::vector< std::vector< int > > > | Matrix |
typedef std::map< std::pair< SwitchID, SwitchID >, std::vector< LinkEntry > > | LinkMap |
typedef AddressProfiler::AddressMap | AddressMap |
typedef std::shared_ptr< Message > | MsgPtr |
typedef std::list< PacketPtr > | PerInstPackets |
Functions | |
Addr | bitSelect (Addr addr, unsigned int small, unsigned int big) |
Addr | maskLowOrderBits (Addr addr, unsigned int number) |
Addr | getOffset (Addr addr) |
Addr | makeLineAddress (Addr addr) |
Addr | makeLineAddress (Addr addr, int cacheLineBits) |
Addr | makeNextStrideAddress (Addr addr, int stride) |
std::string | printAddress (Addr addr) |
std::ostream & | operator<< (std::ostream &os, const BoolVec &myvector) |
std::ostream & | operator<< (std::ostream &out, const Consumer &obj) |
std::ostream & | operator<< (std::ostream &out, const DataBlock &obj) |
bool | operator== (const DataBlock &obj1, const DataBlock &obj2) |
template<typename RespType , typename DataType > | |
std::ostream & | operator<< (std::ostream &out, const ExpectedMap< RespType, DataType > &obj) |
bool | node_less_then_eq (const Histogram *n1, const Histogram *n2) |
std::ostream & | operator<< (std::ostream &out, const Histogram &obj) |
std::ostream & | operator<< (std::ostream &os, const IntVec &myvector) |
std::string | MachineIDToString (MachineID machine) |
bool | operator== (const MachineID &obj1, const MachineID &obj2) |
bool | operator!= (const MachineID &obj1, const MachineID &obj2) |
::std::ostream & | operator<< (::std::ostream &out, const MachineID &obj) |
std::ostream & | operator<< (std::ostream &out, const NetDest &obj) |
std::ostream & | operator<< (std::ostream &out, const Set &obj) |
std::ostream & | operator<< (std::ostream &out, const SubBlock &obj) |
template<class T > | |
std::ostream & | operator<< (std::ostream &out, const TriggerQueue< T > &obj) |
std::ostream & | operator<< (std::ostream &out, const WriteMask &obj) |
std::ostream & | operator<< (std::ostream &out, const BasicLink &obj) |
std::ostream & | operator<< (std::ostream &out, const BasicRouter &obj) |
Tick | random_time () |
std::ostream & | operator<< (std::ostream &out, const MessageBuffer &obj) |
std::ostream & | operator<< (std::ostream &out, const Network &obj) |
std::ostream & | operator<< (std::ostream &out, const PerfectSwitch &obj) |
std::ostream & | operator<< (std::ostream &out, const SimpleExtLink &obj) |
std::ostream & | operator<< (std::ostream &out, const SimpleIntLink &obj) |
std::ostream & | operator<< (std::ostream &out, const SimpleNetwork &obj) |
std::ostream & | operator<< (std::ostream &out, const Switch &obj) |
static int | network_message_to_size (Message *net_msg_ptr) |
std::ostream & | operator<< (std::ostream &out, const Throttle &obj) |
std::ostream & | operator<< (std::ostream &out, const Topology &obj) |
std::ostream & | operator<< (std::ostream &out, const AccessTraceForAddress &obj) |
AccessTraceForAddress & | lookupTraceForAddress (Addr addr, AddressMap &record_map) |
void | printSorted (std::ostream &out, int num_of_sequencers, const AddressMap &record_map, std::string description, Profiler *profiler) |
std::ostream & | operator<< (std::ostream &out, const AddressProfiler &obj) |
bool | node_less_then_eq (const StoreTrace *n1, const StoreTrace *n2) |
std::ostream & | operator<< (std::ostream &out, const StoreTrace &obj) |
std::ostream & | operator<< (std::ostream &out, const AbstractCacheEntry &obj) |
bool | operator> (const MsgPtr &lhs, const MsgPtr &rhs) |
std::ostream & | operator<< (std::ostream &out, const Message &obj) |
std::ostream & | operator<< (std::ostream &out, const RubyRequest &obj) |
NetDest | broadcast (MachineType type) |
MachineID | mapAddressToRange (Addr addr, MachineType type, int low_bit, int num_bits, int cluster_id=0) |
NodeID | machineIDToNodeID (MachineID machID) |
MachineType | machineIDToMachineType (MachineID machID) |
int | machineCount (MachineType machType) |
MachineID | createMachineID (MachineType type, NodeID id) |
MachineID | MachineTypeAndNodeIDToMachineID (MachineType type, NodeID node) |
Cycles | zero_time () |
Cycles | intToCycles (int c) |
Tick | intToTick (int c) |
NodeID | intToID (int nodenum) |
int | IDToInt (NodeID id) |
int | addressToInt (Addr addr) |
Addr | intToAddress (int addr) |
int | mod (int val, int mod) |
int | max_tokens () |
bool | isWriteRequest (RubyRequestType type) |
bool | isDataReadRequest (RubyRequestType type) |
bool | isReadRequest (RubyRequestType type) |
bool | isHtmCmdRequest (RubyRequestType type) |
bool | isTlbiCmdRequest (RubyRequestType type) |
RubyRequestType | htmCmdToRubyRequestType (const Packet *pkt) |
RubyRequestType | tlbiCmdToRubyRequestType (const Packet *pkt) |
int | addressOffset (Addr addr, Addr base) |
bool | testAndRead (Addr addr, DataBlock &blk, Packet *pkt) |
This function accepts an address, a data block and a packet. | |
bool | testAndReadMask (Addr addr, DataBlock &blk, WriteMask &mask, Packet *pkt) |
This function accepts an address, a data block, a write mask and a packet. | |
bool | testAndWrite (Addr addr, DataBlock &blk, Packet *pkt) |
This function accepts an address, a data block and a packet. | |
int | countBoolVec (BoolVec bVec) |
RequestorID | getRequestorID (RequestPtr req) |
std::ostream & | operator<< (std::ostream &out, const CacheMemory &obj) |
std::ostream & | operator<< (std::ostream &out, const DirectoryMemory &obj) |
template<class ENTRY > | |
std::ostream & | operator<< (std::ostream &out, const PerfectCacheLineState< ENTRY > &obj) |
template<class ENTRY > | |
std::ostream & | operator<< (std::ostream &out, const PerfectCacheMemory< ENTRY > &obj) |
std::ostream & | operator<< (std::ostream &out, const PersistentTable &obj) |
std::ostream & | operator<< (std::ostream &out, const PersistentTableEntry &obj) |
template<class ENTRY > | |
std::ostream & | operator<< (std::ostream &out, const TBETable< ENTRY > &obj) |
std::ostream & | operator<< (std::ostream &out, const TimerTable &obj) |
std::ostream & | operator<< (std::ostream &out, const WireBuffer &obj) |
bool | compareTraceRecords (const TraceRecord *n1, const TraceRecord *n2) |
std::ostream & | operator<< (std::ostream &out, const TraceRecord &obj) |
template<class KEY , class VALUE > | |
std::ostream & | operator<< (std::ostream &out, const std::unordered_map< KEY, VALUE > &map) |
std::ostream & | operator<< (std::ostream &out, const GPUCoalescer &obj) |
template<class VALUE > | |
std::ostream & | operator<< (std::ostream &out, const std::deque< VALUE > &queue) |
std::ostream & | operator<< (std::ostream &out, const HTMSequencer &obj) |
std::ostream & | operator<< (std::ostream &out, const SequencerRequest &obj) |
std::ostream & | operator<< (std::ostream &out, const Sequencer &obj) |
Variables | |
const int | PRIORITY_SWITCH_LIMIT = 128 |
const int | MESSAGE_SIZE_MULTIPLIER = 1000 |
const int | BROADCAST_SCALING = 1 |
const int | INFINITE_LATENCY = 10000 |
Definition at line 44 of file AddressProfiler.cc.
typedef std::vector<bool> gem5::ruby::BoolVec |
Definition at line 50 of file BoolVec.hh.
typedef std::vector<int> gem5::ruby::IntVec |
typedef unsigned int gem5::ruby::LinkID |
Definition at line 41 of file TypeDefines.hh.
typedef std::map<std::pair<SwitchID, SwitchID>, std::vector<LinkEntry> > gem5::ruby::LinkMap |
Definition at line 76 of file Topology.hh.
typedef std::vector<std::vector<std::vector<int> > > gem5::ruby::Matrix |
Definition at line 66 of file Topology.hh.
typedef std::shared_ptr<Message> gem5::ruby::MsgPtr |
Definition at line 60 of file Message.hh.
typedef unsigned int gem5::ruby::NodeID |
Definition at line 42 of file TypeDefines.hh.
typedef std::list<PacketPtr> gem5::ruby::PerInstPackets |
Definition at line 65 of file GPUCoalescer.hh.
typedef std::string gem5::ruby::PortDirection |
Definition at line 44 of file TypeDefines.hh.
typedef unsigned int gem5::ruby::SwitchID |
Definition at line 43 of file TypeDefines.hh.
Definition at line 212 of file RubySlicc_Util.hh.
References gem5::X86ISA::addr, gem5::X86ISA::base, and gem5::ArmISA::offset.
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Definition at line 89 of file RubySlicc_Util.hh.
References gem5::X86ISA::addr.
Definition at line 41 of file Address.cc.
References gem5::X86ISA::addr, and gem5::bits().
Referenced by gem5::CheckTable::addCheck(), gem5::ruby::CacheMemory::addressToCacheSet(), getOffset(), and mapAddressToRange().
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Definition at line 45 of file RubySlicc_ComponentMapping.hh.
References gem5::ruby::NetDest::add(), gem5::ArmISA::i, and gem5::X86ISA::type.
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Definition at line 125 of file CacheRecorder.hh.
References gem5::ruby::TraceRecord::m_time.
Referenced by gem5::ruby::CacheRecorder::aggregateRecords().
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Definition at line 308 of file RubySlicc_Util.hh.
References gem5::X86ISA::count, and gem5::ArmISA::e.
Definition at line 87 of file RubySlicc_ComponentMapping.hh.
References gem5::X86ISA::type.
Definition at line 54 of file Address.cc.
References gem5::X86ISA::addr, bitSelect(), and gem5::ruby::RubySystem::getBlockSizeBits().
Referenced by gem5::ruby::GPUCoalescer::hitCallback(), gem5::ruby::Sequencer::hitCallback(), gem5::ruby::SubBlock::internalMergeFrom(), gem5::ruby::SubBlock::internalMergeTo(), gem5::ruby::Sequencer::issueRequest(), gem5::ruby::RubyPrefetcherProxy::notifyPfFill(), gem5::ruby::RubyPrefetcherProxy::notifyPfHit(), gem5::ruby::RubyPrefetcherProxy::notifyPfMiss(), gem5::ruby::RubyPort::MemResponsePort::recvAtomic(), gem5::ruby::AbstractController::serviceMemoryQueue(), gem5::ruby::DataBlock::setData(), and gem5::ruby::MessageBuffer::stallMessage().
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Definition at line 320 of file RubySlicc_Util.hh.
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Definition at line 179 of file RubySlicc_Util.hh.
References panic, and gem5::Packet::req.
Referenced by gem5::ruby::Sequencer::makeRequest().
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Definition at line 82 of file RubySlicc_Util.hh.
References gem5::ArmISA::id.
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Definition at line 96 of file RubySlicc_Util.hh.
References gem5::X86ISA::addr.
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Definition at line 70 of file RubySlicc_Util.hh.
References gem5::ArmISA::c.
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Definition at line 75 of file RubySlicc_Util.hh.
References gem5::ArmISA::id.
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Definition at line 72 of file RubySlicc_Util.hh.
References gem5::ArmISA::c.
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Definition at line 131 of file RubySlicc_Util.hh.
References gem5::X86ISA::type.
Referenced by isReadRequest().
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Definition at line 153 of file RubySlicc_Util.hh.
References gem5::X86ISA::type.
Referenced by gem5::ruby::HTMSequencer::htmCallback(), and gem5::ruby::HTMSequencer::insertRequest().
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Definition at line 142 of file RubySlicc_Util.hh.
References isDataReadRequest(), and gem5::X86ISA::type.
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Definition at line 166 of file RubySlicc_Util.hh.
References gem5::X86ISA::type.
Referenced by gem5::ruby::Sequencer::insertRequest().
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Definition at line 114 of file RubySlicc_Util.hh.
References gem5::X86ISA::type.
AccessTraceForAddress & gem5::ruby::lookupTraceForAddress | ( | Addr | addr, |
AddressMap & | record_map ) |
Definition at line 50 of file AddressProfiler.cc.
References gem5::X86ISA::addr, gem5::ArmISA::i, gem5::MipsISA::r, and gem5::ruby::AccessTraceForAddress::setAddress().
Referenced by gem5::ruby::AddressProfiler::addTraceSample(), and gem5::ruby::AddressProfiler::profileRetry().
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Definition at line 81 of file RubySlicc_ComponentMapping.hh.
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Definition at line 75 of file RubySlicc_ComponentMapping.hh.
References gem5::ruby::MachineID::type.
Definition at line 69 of file RubySlicc_ComponentMapping.hh.
References gem5::ruby::MachineID::num.
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Definition at line 73 of file MachineID.hh.
References gem5::csprintf(), gem5::ruby::MachineID::num, and gem5::ruby::MachineID::type.
Referenced by gem5::ruby::RubySystem::registerMachineID(), and gem5::ruby::RubySystem::registerRequestorIDs().
Definition at line 94 of file RubySlicc_ComponentMapping.hh.
References gem5::X86ISA::type.
Definition at line 60 of file Address.cc.
References gem5::X86ISA::addr, gem5::ruby::RubySystem::getBlockSizeBits(), and gem5::mbits().
Referenced by gem5::ruby::CacheMemory::addressToCacheSet(), gem5::ruby::AddressProfiler::addTraceSample(), gem5::ruby::CacheMemory::allocate(), gem5::ruby::PerfectCacheMemory< ENTRY >::allocate(), gem5::ruby::GPUCoalescer::atomicCallback(), gem5::ruby::Sequencer::atomicCallback(), gem5::ruby::CacheMemory::cacheAvail(), gem5::ruby::CacheMemory::cacheProbe(), gem5::ruby::PerfectCacheMemory< ENTRY >::changePermission(), gem5::ruby::CacheMemory::checkResourceAvailable(), gem5::ruby::GPUCoalescer::coalescePacket(), gem5::ruby::RubyPrefetcherProxy::completePrefetch(), gem5::ruby::PersistentTable::countReadStarvingForAddress(), gem5::ruby::PersistentTable::countStarvingForAddress(), gem5::ruby::PerfectCacheMemory< ENTRY >::deallocate(), gem5::ruby::PersistentTable::findSmallest(), gem5::ruby::CacheMemory::findTagInSet(), gem5::ruby::CacheMemory::findTagInSetIgnorePermissions(), gem5::ruby::RubySystem::functionalRead(), gem5::ruby::RubySystem::functionalWrite(), gem5::ruby::PerfectCacheMemory< ENTRY >::getPermission(), gem5::ruby::GPUCoalescer::hitCallback(), gem5::ruby::Sequencer::hitCallback(), gem5::ruby::HTMSequencer::htmCallback(), gem5::ruby::RubyPrefetcher::initializeStream(), gem5::FetchUnit::initiateFetch(), gem5::ruby::Sequencer::insertRequest(), gem5::ruby::PersistentTable::isLocked(), gem5::ruby::TBETable< ENTRY >::isPresent(), gem5::ruby::DMASequencer::issueNext(), gem5::ruby::VIPERCoalescer::issueRequest(), gem5::ruby::PerfectCacheMemory< ENTRY >::isTagPresent(), gem5::ruby::Sequencer::llscCheckMonitor(), gem5::ruby::CacheMemory::lookup(), gem5::ruby::CacheMemory::lookup(), gem5::ruby::PerfectCacheMemory< ENTRY >::lookup(), gem5::ruby::PerfectCacheMemory< ENTRY >::lookup(), makeNextStrideAddress(), gem5::ruby::DMASequencer::makeRequest(), gem5::ruby::Sequencer::makeRequest(), gem5::ruby::PersistentTable::markEntries(), gem5::FetchUnit::FetchBufDesc::nextFetchAddr(), gem5::ruby::RubyPrefetcher::observeMiss(), gem5::ruby::PersistentTable::okToIssueStarving(), gem5::Check::performCallback(), gem5::ruby::PersistentTable::persistentRequestLock(), gem5::ruby::PersistentTable::persistentRequestUnlock(), printAddress(), gem5::ruby::GPUCoalescer::readCallback(), gem5::ruby::Sequencer::readCallback(), gem5::ruby::RubyPort::MemResponsePort::recvFunctional(), gem5::ruby::ALUFreeListArray::reserve(), gem5::ruby::RubyRequest::RubyRequest(), gem5::ruby::RubyRequest::RubyRequest(), gem5::ruby::RubyRequest::RubyRequest(), gem5::ruby::TimerTable::set(), gem5::ruby::CacheMemory::setMRU(), gem5::ruby::CacheMemory::setMRU(), testAndRead(), testAndReadMask(), testAndWrite(), gem5::ruby::ALUFreeListArray::tryAccess(), gem5::ruby::PersistentTable::typeOfSmallest(), gem5::ruby::TimerTable::unset(), gem5::ruby::GPUCoalescer::writeCallback(), gem5::ruby::Sequencer::writeCallback(), and gem5::ruby::VIPERCoalescer::writeCompleteCallback().
Definition at line 66 of file Address.cc.
References gem5::X86ISA::addr, and maskLowOrderBits().
Definition at line 73 of file Address.cc.
References gem5::X86ISA::addr, gem5::ruby::RubySystem::getBlockSizeBytes(), makeLineAddress(), and gem5::ArmISA::stride.
Referenced by gem5::ruby::RubyPrefetcher::accessUnitFilter(), gem5::ruby::RubyPrefetcher::getPrefetchEntry(), gem5::ruby::RubyPrefetcher::initializeStream(), and gem5::ruby::RubyPrefetcher::issueNextPrefetch().
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Definition at line 56 of file RubySlicc_ComponentMapping.hh.
References gem5::X86ISA::addr, bitSelect(), gem5::ruby::MachineID::num, and gem5::X86ISA::type.
Definition at line 48 of file Address.cc.
References gem5::X86ISA::addr, and gem5::mbits().
Referenced by makeLineAddress().
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Definition at line 108 of file RubySlicc_Util.hh.
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Definition at line 103 of file RubySlicc_Util.hh.
References gem5::X86ISA::mod, and gem5::X86ISA::val.
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Definition at line 317 of file Throttle.cc.
References BROADCAST_SCALING, gem5::ruby::Message::getDestination(), gem5::ruby::Message::getMessageSize(), gem5::ruby::NetDest::isBroadcast(), MESSAGE_SIZE_MULTIPLIER, and gem5::ruby::Network::MessageSizeType_to_int().
Referenced by gem5::ruby::Throttle::operateVnet().
Definition at line 239 of file Histogram.cc.
References gem5::ruby::Histogram::size().
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Definition at line 83 of file StoreTrace.hh.
References gem5::ruby::StoreTrace::getTotal().
Definition at line 85 of file MachineID.hh.
References gem5::ruby::MachineID::num, and gem5::ruby::MachineID::type.
std::ostream & gem5::ruby::operator<< | ( | ::std::ostream & | out, |
const MachineID & | obj ) |
Definition at line 93 of file MachineID.hh.
References gem5::ruby::MachineID::num, and gem5::ruby::MachineID::type.
std::ostream & gem5::ruby::operator<< | ( | std::ostream & | os, |
const BoolVec & | myvector ) |
Definition at line 49 of file BoolVec.cc.
References gem5::ArmISA::e, and gem5::X86ISA::os.
std::ostream & gem5::ruby::operator<< | ( | std::ostream & | os, |
const IntVec & | myvector ) |
Definition at line 43 of file IntVec.cc.
References gem5::X86ISA::os.
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Definition at line 131 of file AbstractCacheEntry.hh.
References gem5::ruby::AbstractCacheEntry::print().
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Definition at line 86 of file AccessTraceForAddress.hh.
References gem5::ruby::AccessTraceForAddress::print().
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Definition at line 113 of file AddressProfiler.hh.
References gem5::ruby::AddressProfiler::print().
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Definition at line 67 of file BasicLink.hh.
References gem5::ruby::BasicLink::print().
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Definition at line 62 of file BasicRouter.hh.
References gem5::ruby::BasicRouter::print().
std::ostream & gem5::ruby::operator<< | ( | std::ostream & | out, |
const CacheMemory & | obj ) |
Definition at line 62 of file CacheMemory.cc.
References gem5::ruby::CacheMemory::print().
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Definition at line 100 of file Consumer.hh.
References gem5::ruby::Consumer::print().
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Definition at line 142 of file DataBlock.hh.
References gem5::ruby::DataBlock::print().
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Definition at line 115 of file DirectoryMemory.hh.
References gem5::ruby::DirectoryMemory::print().
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Definition at line 230 of file ExpectedMap.hh.
References gem5::ruby::ExpectedMap< RespType, DataType >::print().
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Definition at line 538 of file GPUCoalescer.hh.
References gem5::ruby::GPUCoalescer::print().
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Definition at line 85 of file Histogram.hh.
References gem5::ruby::Histogram::print().
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Definition at line 110 of file HTMSequencer.hh.
References gem5::ruby::HTMSequencer::print().
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Definition at line 147 of file Message.hh.
References gem5::ruby::Message::print().
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Definition at line 299 of file MessageBuffer.hh.
References gem5::ruby::MessageBuffer::print().
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Definition at line 117 of file NetDest.hh.
References gem5::ruby::NetDest::print().
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Definition at line 181 of file Network.hh.
References gem5::ruby::Network::print().
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Definition at line 65 of file PerfectCacheMemory.hh.
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Definition at line 114 of file PerfectCacheMemory.hh.
References gem5::ruby::PerfectCacheMemory< ENTRY >::print().
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Definition at line 134 of file PerfectSwitch.hh.
References gem5::ruby::PerfectSwitch::print().
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Definition at line 90 of file PersistentTable.hh.
References gem5::ruby::PersistentTable::print().
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Definition at line 98 of file PersistentTable.hh.
References gem5::ruby::PersistentTableEntry::print().
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Definition at line 242 of file RubyRequest.hh.
References gem5::ruby::RubyRequest::print().
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Definition at line 363 of file Sequencer.hh.
References gem5::ruby::Sequencer::print().
std::ostream & gem5::ruby::operator<< | ( | std::ostream & | out, |
const SequencerRequest & | obj ) |
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Definition at line 227 of file Set.hh.
References gem5::ruby::Set::print().
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Definition at line 70 of file SimpleLink.hh.
References gem5::ruby::SimpleExtLink::print().
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Definition at line 91 of file SimpleLink.hh.
References gem5::ruby::SimpleIntLink::print().
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Definition at line 121 of file SimpleNetwork.hh.
References gem5::ruby::SimpleNetwork::print().
std::ostream & gem5::ruby::operator<< | ( | std::ostream & | out, |
const std::deque< VALUE > & | queue ) |
Definition at line 285 of file HTMSequencer.cc.
References gem5::ArmISA::i.
std::ostream & gem5::ruby::operator<< | ( | std::ostream & | out, |
const std::unordered_map< KEY, VALUE > & | map ) |
Definition at line 730 of file GPUCoalescer.cc.
References gem5::ArmISA::i.
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Definition at line 88 of file StoreTrace.hh.
References gem5::ruby::StoreTrace::print().
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Definition at line 79 of file SubBlock.hh.
References gem5::ruby::SubBlock::print().
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Definition at line 144 of file Switch.hh.
References gem5::ruby::Switch::print().
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Definition at line 92 of file TBETable.hh.
References gem5::ruby::TBETable< ENTRY >::print().
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Definition at line 158 of file Throttle.hh.
References gem5::ruby::Throttle::print().
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Definition at line 94 of file TimerTable.hh.
References gem5::ruby::TimerTable::print().
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Definition at line 121 of file Topology.hh.
References gem5::ruby::Topology::print().
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Definition at line 130 of file CacheRecorder.hh.
References gem5::ruby::TraceRecord::print().
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Definition at line 118 of file TriggerQueue.hh.
References gem5::ruby::TriggerQueue< T >::print().
std::ostream & gem5::ruby::operator<< | ( | std::ostream & | out, |
const WireBuffer & | obj ) |
Definition at line 49 of file WireBuffer.cc.
References gem5::ruby::WireBuffer::print().
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Definition at line 256 of file WriteMask.hh.
References gem5::ruby::WriteMask::print().
Definition at line 151 of file DataBlock.hh.
References gem5::ruby::DataBlock::equal().
Definition at line 79 of file MachineID.hh.
References gem5::ruby::MachineID::num, and gem5::ruby::MachineID::type.
Definition at line 136 of file Message.hh.
References gem5::ruby::Message::getMsgCounter(), gem5::MipsISA::l, and gem5::MipsISA::r.
std::string gem5::ruby::printAddress | ( | Addr | addr | ) |
Definition at line 80 of file Address.cc.
References gem5::X86ISA::addr, and makeLineAddress().
Referenced by gem5::DmaThread::hitCallback(), gem5::GpuWavefront::hitCallback(), gem5::ruby::Sequencer::hitCallback(), gem5::GpuWavefront::issueAtomicOps(), gem5::DmaThread::issueLoadOps(), gem5::GpuWavefront::issueLoadOps(), gem5::ruby::Sequencer::issueRequest(), gem5::ruby::VIPERCoalescer::issueRequest(), gem5::DmaThread::issueStoreOps(), gem5::GpuWavefront::issueStoreOps(), gem5::TesterThread::printOutstandingReqs(), gem5::ruby::GPUCoalescer::printRequestTable(), gem5::ruby::UncoalescedTable::printRequestTable(), gem5::ruby::Sequencer::recordMissLatency(), gem5::TesterThread::validateAtomicResp(), and gem5::TesterThread::validateLoadResp().
void gem5::ruby::printSorted | ( | std::ostream & | out, |
int | num_of_sequencers, | ||
const AddressMap & | record_map, | ||
std::string | description, | ||
Profiler * | profiler ) |
Definition at line 72 of file AddressProfiler.cc.
References gem5::ruby::Histogram::add(), gem5::ruby::Profiler::getAllInstructions(), gem5::ruby::AccessTraceForAddress::getTotal(), gem5::ruby::AccessTraceForAddress::getTouchedBy(), gem5::ArmISA::i, and gem5::ruby::AccessTraceForAddress::less_equal().
Referenced by gem5::ruby::AddressProfiler::printStats().
Tick gem5::ruby::random_time | ( | ) |
Definition at line 207 of file MessageBuffer.cc.
References gem5::Random::random(), and gem5::random_mt.
Referenced by gem5::ruby::MessageBuffer::enqueue().
This function accepts an address, a data block and a packet.
If the address range for the data block contains the address which the packet needs to read, then the data from the data block is written to the packet. True is returned if the data block was read, otherwise false is returned.
This is used during a functional access "search the world" operation. The functional access looks in every place that might hold a valid data block and, if it finds one, checks to see if it is holding the address the access is searching for. During the access check, the WriteMask could be in any state, including empty.
Definition at line 234 of file RubySlicc_Util.hh.
References gem5::X86ISA::addr, data, gem5::Packet::getAddr(), gem5::ruby::DataBlock::getByte(), gem5::Packet::getPtr(), gem5::Packet::getSize(), gem5::ArmISA::i, and makeLineAddress().
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This function accepts an address, a data block, a write mask and a packet.
If the valid address range for the data block contains the address which the packet needs to read, then the data from the data block is written to the packet. True is returned if any part of the data block was read, otherwise false is returned.
Definition at line 260 of file RubySlicc_Util.hh.
References gem5::X86ISA::addr, data, gem5::Packet::getAddr(), gem5::ruby::DataBlock::getByte(), gem5::Packet::getPtr(), gem5::Packet::getSize(), gem5::ArmISA::i, makeLineAddress(), and gem5::ArmISA::mask.
This function accepts an address, a data block and a packet.
If the address range for the data block contains the address which the packet needs to write, then the data from the packet is written to the data block. True is returned if the data block was written, otherwise false is returned.
Definition at line 289 of file RubySlicc_Util.hh.
References gem5::X86ISA::addr, data, gem5::Packet::getAddr(), gem5::Packet::getConstPtr(), gem5::Packet::getSize(), gem5::ArmISA::i, makeLineAddress(), and gem5::ruby::DataBlock::setByte().
Referenced by gem5::ruby::RubyRequest::functionalWrite().
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inline |
Definition at line 196 of file RubySlicc_Util.hh.
References panic, and gem5::Packet::req.
Referenced by gem5::ruby::Sequencer::makeRequest().
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inline |
Definition at line 68 of file RubySlicc_Util.hh.
const int gem5::ruby::BROADCAST_SCALING = 1 |
Definition at line 63 of file Throttle.cc.
Referenced by network_message_to_size().
const int gem5::ruby::INFINITE_LATENCY = 10000 |
Definition at line 47 of file Topology.cc.
Referenced by gem5::ruby::Topology::createLinks().
const int gem5::ruby::MESSAGE_SIZE_MULTIPLIER = 1000 |
Definition at line 61 of file Throttle.cc.
Referenced by network_message_to_size().
const int gem5::ruby::PRIORITY_SWITCH_LIMIT = 128 |
Definition at line 60 of file PerfectSwitch.cc.
Referenced by gem5::ruby::PerfectSwitch::wakeup(), and gem5::ruby::Throttle::wakeup().