gem5  v22.1.0.0
SimpleLTTarget1.h
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19 
20 #ifndef __SIMPLE_LT_TARGET1_H__
21 #define __SIMPLE_LT_TARGET1_H__
22 
23 #include "tlm.h"
24 #include <cassert>
25 #include <vector>
26 
28  public sc_core::sc_module,
29  public virtual tlm::tlm_fw_transport_if<>
30 {
31 public:
38 
39 public:
41 
42 public:
44  SimpleLTTarget1(sc_core::sc_module_name name, bool invalidate = false) :
46  socket("socket"),
47  m_invalidate(invalidate)
48  {
49  // Bind this target's interface to the target socket
50  socket(*this);
51  if (invalidate)
52  {
57  }
58  }
59 
61  {
62  //Target never calls wait, so we can do this
63  b_transport(trans, t);
64 
65  return tlm::TLM_COMPLETED;
66  }
67 
69  {
70  sc_dt::uint64 address = trans.get_address();
71  assert(address < 400);
72 
73  unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr());
74  if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
75  std::cout << name() << ": Received write request: A = 0x"
76  << std::hex << (unsigned int)address
77  << ", D = 0x" << data << std::dec
78  << " @ " << sc_core::sc_time_stamp() << std::endl;
79 
80  *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
82 
83  } else {
84  std::cout << name() << ": Received read request: A = 0x"
85  << std::hex << (unsigned int)address << std::dec
86  << " @ " << sc_core::sc_time_stamp() << std::endl;
87 
88  data = *reinterpret_cast<unsigned int*>(&mMem[address]);
90  }
91 
93 
94  trans.set_dmi_allowed(true);
95  }
96 
98  {
99  if (r.get_address() >= 400) return 0;
100 
101  unsigned int tmp = (int)r.get_address();
102  unsigned int num_bytes;
103  if (tmp + r.get_data_length() >= 400) {
104  num_bytes = 400 - tmp;
105 
106  } else {
107  num_bytes = r.get_data_length();
108  }
109  if (r.is_read()) {
110  for (unsigned int i = 0; i < num_bytes; ++i) {
111  r.get_data_ptr()[i] = mMem[i + tmp];
112  }
113 
114  } else {
115  for (unsigned int i = 0; i < num_bytes; ++i) {
116  mMem[i + tmp] = r.get_data_ptr()[i];
117  }
118  }
119  return num_bytes;
120  }
121 
123  tlm::tlm_dmi& dmi_data)
124  {
125  sc_dt::uint64 address = trans.get_address();
127  if (address < 400) {
128  dmi_data.allow_read_write();
129  dmi_data.set_start_address(0x0);
130  dmi_data.set_end_address(399);
131  dmi_data.set_dmi_ptr(mMem);
134  return true;
135 
136  } else {
137  // should not happen
138  dmi_data.set_start_address(trans.get_address());
139  dmi_data.set_end_address(trans.get_address());
140  return false;
141 
142  }
143  }
144 
146  {
147  sc_dt::uint64 start_address = 0x0;
148  sc_dt::uint64 end_address = 399;
149  socket->invalidate_direct_mem_ptr(start_address, end_address);
150  }
151 private:
152  unsigned char mMem[400];
156 };
157 
158 #endif
const char data[]
target_socket_type socket
tlm::tlm_generic_payload transaction_type
sync_enum_type nb_transport_fw(transaction_type &trans, phase_type &phase, sc_core::sc_time &t)
sc_core::sc_time m_invalidate_dmi_time
tlm::tlm_sync_enum sync_enum_type
void b_transport(transaction_type &trans, sc_core::sc_time &t)
unsigned int transport_dbg(transaction_type &r)
tlm::tlm_bw_transport_if bw_interface_type
tlm::tlm_fw_transport_if fw_interface_type
unsigned char mMem[400]
bool get_direct_mem_ptr(transaction_type &trans, tlm::tlm_dmi &dmi_data)
SimpleLTTarget1(sc_core::sc_module_name name, bool invalidate=false)
void invalidate_dmi_method()
tlm::tlm_phase phase_type
sc_core::sc_event m_invalidate_dmi_event
SC_HAS_PROCESS(SimpleLTTarget1)
tlm::tlm_target_socket< 32 > target_socket_type
sc_sensitive sensitive
Definition: sc_module.hh:210
void dont_initialize()
Definition: sc_module.cc:336
const char * name() const
Definition: sc_object.cc:44
void set_write_latency(sc_core::sc_time t)
Definition: dmi.hh:85
void set_dmi_ptr(unsigned char *p)
Definition: dmi.hh:81
void set_start_address(sc_dt::uint64 addr)
Definition: dmi.hh:82
void set_end_address(sc_dt::uint64 addr)
Definition: dmi.hh:83
void set_read_latency(sc_core::sc_time t)
Definition: dmi.hh:84
void allow_read_write()
Definition: dmi.hh:90
unsigned char * get_data_ptr() const
Definition: gp.hh:188
void set_dmi_allowed(bool dmi_allowed)
Definition: gp.hh:239
void set_response_status(const tlm_response_status response_status)
Definition: gp.hh:204
sc_dt::uint64 get_address() const
Definition: gp.hh:184
tlm_command get_command() const
Definition: gp.hh:180
Bitfield< 7 > i
Definition: misc_types.hh:67
Bitfield< 5 > r
Definition: pagetable.hh:60
Bitfield< 51 > t
Definition: pagetable.hh:56
@ SC_NS
Definition: sc_time.hh:43
const sc_time & sc_time_stamp()
Definition: sc_main.cc:127
uint64_t uint64
Definition: sc_nbdefs.hh:172
@ TLM_WRITE_COMMAND
Definition: gp.hh:85
@ TLM_OK_RESPONSE
Definition: gp.hh:91
tlm_sync_enum
Definition: fw_bw_ifs.hh:31
@ TLM_COMPLETED
Definition: fw_bw_ifs.hh:31
#define SC_METHOD(name)
Definition: sc_module.hh:303

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