57using stl_helpers::operator<<;
61 perfectSwitch(m_id, this,
p.virt_nets),
62 m_int_routing_latency(
p.int_routing_latency),
63 m_ext_routing_latency(
p.ext_routing_latency),
64 m_routing_unit(*
p.routing_unit), m_num_connected_buffers(0),
68 for (
auto& buffer :
p.port_buffers) {
89 const NetDest& routing_table_entry,
90 Cycles link_latency,
int link_weight,
99 if (physical_vnets_channels.size() > 0 && !out.empty()) {
104 physical_vnets_bandwidth.resize(out.size(), bw_multiplier);
108 physical_vnets_channels, physical_vnets_bandwidth,
112 throttles.size(), link_latency, bw_multiplier,
119 for (
int i = 0;
i < out.size(); ++
i) {
124 intermediateBuffers.push_back(buffer_ptr);
131 dst_inport, routing_latency, link_weight);
134 throttles.back().addLinks(intermediateBuffers, out);
147 for (
unsigned int type = MessageSizeType_FIRST;
148 type < MessageSizeType_NUM; ++
type) {
151 MessageSizeType_to_string(MessageSizeType(
type))).c_str());
158 MessageSizeType_to_string(MessageSizeType(
type))).c_str());
216 uint32_t num_functional_writes = 0;
220 return num_functional_writes;
225 : statistics::
Group(parent),
226 m_avg_utilization(this,
"percent_links_utilized")
Tick cyclesToTicks(Cycles c) const
Cycles is a wrapper class for representing cycle counts, i.e.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
void init_parent(Switch *parent_switch)
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
static uint32_t MessageSizeType_to_int(MessageSizeType size_type)
void init(SimpleNetwork *)
void addOutPort(const std::vector< MessageBuffer * > &out, const NetDest &routing_table_entry, const PortDirection &dst_inport, Tick routing_latency, int link_weight)
void addInPort(const std::vector< MessageBuffer * > &in)
int getEndpointBandwidth()
void addInPort(const std::vector< MessageBuffer * > &in)
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
BaseRoutingUnit & m_routing_unit
const Cycles m_int_routing_latency
PerfectSwitch perfectSwitch
bool functionalRead(Packet *)
uint32_t functionalWrite(Packet *)
SimpleNetwork * m_network_ptr
void print(std::ostream &out) const
const Cycles m_ext_routing_latency
unsigned m_num_connected_buffers
void addOutPort(const std::vector< MessageBuffer * > &out, const NetDest &routing_table_entry, Cycles link_latency, int link_weight, int bw_multiplier, bool is_external, PortDirection dst_inport="")
std::vector< MessageBuffer * > m_port_buffers
std::list< Throttle > throttles
void resetStats()
Callback to reset stats.
void regStats()
Callback to set stat parameters.
gem5::ruby::Switch::SwitchStats switchStats
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
const Params & params() const
virtual void regStats()
Callback to set stat parameters.
std::string PortDirection
const FlagsType nozero
Don't print if this is zero.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
uint64_t Tick
Tick count type.
std::string csprintf(const char *format, const Args &...args)
SwitchStats(statistics::Group *parent)
statistics::Formula m_avg_utilization
statistics::Formula * m_msg_bytes[MessageSizeType_NUM]
statistics::Formula * m_msg_counts[MessageSizeType_NUM]