gem5 v24.0.0.0
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Switch.cc
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1/*
2 * Copyright (c) 2020 Inria
3 * Copyright (c) 2019,2021 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
43
44#include <numeric>
45
46#include "base/cast.hh"
47#include "base/stl_helpers.hh"
50
51namespace gem5
52{
53
54namespace ruby
55{
56
57using stl_helpers::operator<<;
58
60 : BasicRouter(p),
61 perfectSwitch(m_id, this, p.virt_nets),
62 m_int_routing_latency(p.int_routing_latency),
63 m_ext_routing_latency(p.ext_routing_latency),
64 m_routing_unit(*p.routing_unit), m_num_connected_buffers(0),
65 switchStats(this)
66{
67 m_port_buffers.reserve(p.port_buffers.size());
68 for (auto& buffer : p.port_buffers) {
69 m_port_buffers.emplace_back(buffer);
70 }
71}
72
73void
80
81void
86
87void
89 const NetDest& routing_table_entry,
90 Cycles link_latency, int link_weight,
91 int bw_multiplier,
92 bool is_external,
93 PortDirection dst_inport)
94{
95 const std::vector<int> &physical_vnets_channels =
96 m_network_ptr->params().physical_vnets_channels;
97
98 // Create a throttle
99 if (physical_vnets_channels.size() > 0 && !out.empty()) {
100 // Assign a different bandwith for each vnet channel if specified by
101 // physical_vnets_bandwidth, otherwise all channels use bw_multiplier
102 std::vector<int> physical_vnets_bandwidth =
103 m_network_ptr->params().physical_vnets_bandwidth;
104 physical_vnets_bandwidth.resize(out.size(), bw_multiplier);
105
106 throttles.emplace_back(m_id, m_network_ptr->params().ruby_system,
107 throttles.size(), link_latency,
108 physical_vnets_channels, physical_vnets_bandwidth,
110 } else {
111 throttles.emplace_back(m_id, m_network_ptr->params().ruby_system,
112 throttles.size(), link_latency, bw_multiplier,
114 }
115
116 // Create one buffer per vnet (these are intermediaryQueues)
117 std::vector<MessageBuffer*> intermediateBuffers;
118
119 for (int i = 0; i < out.size(); ++i) {
121 MessageBuffer* buffer_ptr =
124 intermediateBuffers.push_back(buffer_ptr);
125 }
126
127 Tick routing_latency = is_external ? cyclesToTicks(m_ext_routing_latency) :
129 // Hook the queues to the PerfectSwitch
130 perfectSwitch.addOutPort(intermediateBuffers, routing_table_entry,
131 dst_inport, routing_latency, link_weight);
132
133 // Hook the queues to the Throttle
134 throttles.back().addLinks(intermediateBuffers, out);
135}
136
137void
139{
141
142 for (const auto& throttle : throttles) {
143 switchStats.m_avg_utilization += throttle.getUtilization();
144 }
146
147 for (unsigned int type = MessageSizeType_FIRST;
148 type < MessageSizeType_NUM; ++type) {
150 csprintf("msg_count.%s",
151 MessageSizeType_to_string(MessageSizeType(type))).c_str());
154 ;
155
157 csprintf("msg_bytes.%s",
158 MessageSizeType_to_string(MessageSizeType(type))).c_str());
161 ;
162
163 for (const auto& throttle : throttles) {
164 *(switchStats.m_msg_counts[type]) += throttle.getMsgCount(type);
165 }
168 Network::MessageSizeType_to_int(MessageSizeType(type)));
169 }
170}
171
172void
177
178void
183
184void
185Switch::print(std::ostream& out) const
186{
187 // FIXME printing
188 out << "[Switch]";
189}
190
191bool
193{
194 for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
196 return true;
197 }
198 return false;
199}
200
201bool
203{
204 bool read = false;
205 for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
207 read = true;
208 }
209 return read;
210}
211
212uint32_t
214{
215 // Access the buffers in the switch for performing a functional write
216 uint32_t num_functional_writes = 0;
217 for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
218 num_functional_writes += m_port_buffers[i]->functionalWrite(pkt);
219 }
220 return num_functional_writes;
221}
222
225 : statistics::Group(parent),
226 m_avg_utilization(this, "percent_links_utilized")
227{
228
229}
230
231} // namespace ruby
232} // namespace gem5
Tick cyclesToTicks(Cycles c) const
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
void init_parent(Switch *parent_switch)
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
static uint32_t MessageSizeType_to_int(MessageSizeType size_type)
Definition Network.cc:164
void init(SimpleNetwork *)
void addOutPort(const std::vector< MessageBuffer * > &out, const NetDest &routing_table_entry, const PortDirection &dst_inport, Tick routing_latency, int link_weight)
void addInPort(const std::vector< MessageBuffer * > &in)
void addInPort(const std::vector< MessageBuffer * > &in)
Definition Switch.cc:82
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition Switch.cc:74
BaseRoutingUnit & m_routing_unit
Definition Switch.hh:126
const Cycles m_int_routing_latency
Definition Switch.hh:123
PerfectSwitch perfectSwitch
Definition Switch.hh:119
SwitchParams Params
Definition Switch.hh:87
bool functionalRead(Packet *)
Definition Switch.cc:192
uint32_t functionalWrite(Packet *)
Definition Switch.cc:213
SimpleNetwork * m_network_ptr
Definition Switch.hh:120
void print(std::ostream &out) const
Definition Switch.cc:185
Switch(const Params &p)
Definition Switch.cc:59
const Cycles m_ext_routing_latency
Definition Switch.hh:124
unsigned m_num_connected_buffers
Definition Switch.hh:128
void addOutPort(const std::vector< MessageBuffer * > &out, const NetDest &routing_table_entry, Cycles link_latency, int link_weight, int bw_multiplier, bool is_external, PortDirection dst_inport="")
Definition Switch.cc:88
std::vector< MessageBuffer * > m_port_buffers
Definition Switch.hh:129
std::list< Throttle > throttles
Definition Switch.hh:121
void resetStats()
Callback to reset stats.
Definition Switch.cc:173
void collateStats()
Definition Switch.cc:179
void regStats()
Callback to set stat parameters.
Definition Switch.cc:138
gem5::ruby::Switch::SwitchStats switchStats
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
A formula for statistics that is calculated when printed.
Statistics container.
Definition group.hh:93
STL vector class.
Definition stl.hh:37
const Params & params() const
virtual void regStats()
Callback to set stat parameters.
Definition group.cc:68
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 0 > p
std::string PortDirection
const FlagsType nozero
Don't print if this is zero.
Definition info.hh:67
Temp constant(T val)
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Tick
Tick count type.
Definition types.hh:58
std::string csprintf(const char *format, const Args &...args)
Definition cprintf.hh:161
SwitchStats(statistics::Group *parent)
Definition Switch.cc:224
statistics::Formula m_avg_utilization
Definition Switch.hh:138
statistics::Formula * m_msg_bytes[MessageSizeType_NUM]
Definition Switch.hh:140
statistics::Formula * m_msg_counts[MessageSizeType_NUM]
Definition Switch.hh:139

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