gem5  v22.0.0.2
Switch.cc
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41 
43 
44 #include <numeric>
45 
46 #include "base/cast.hh"
47 #include "base/stl_helpers.hh"
50 
51 namespace gem5
52 {
53 
54 namespace ruby
55 {
56 
57 using stl_helpers::operator<<;
58 
60  : BasicRouter(p),
61  perfectSwitch(m_id, this, p.virt_nets),
62  m_int_routing_latency(p.int_routing_latency),
63  m_ext_routing_latency(p.ext_routing_latency),
64  m_routing_unit(*p.routing_unit), m_num_connected_buffers(0),
65  switchStats(this)
66 {
67  m_port_buffers.reserve(p.port_buffers.size());
68  for (auto& buffer : p.port_buffers) {
69  m_port_buffers.emplace_back(buffer);
70  }
71 }
72 
73 void
75 {
79 }
80 
81 void
83 {
85 }
86 
87 void
89  const NetDest& routing_table_entry,
90  Cycles link_latency, int link_weight,
91  int bw_multiplier,
92  bool is_external,
93  PortDirection dst_inport)
94 {
95  const std::vector<int> &physical_vnets_channels =
96  m_network_ptr->params().physical_vnets_channels;
97 
98  // Create a throttle
99  if (physical_vnets_channels.size() > 0 && !out.empty()) {
100  // Assign a different bandwith for each vnet channel if specified by
101  // physical_vnets_bandwidth, otherwise all channels use bw_multiplier
102  std::vector<int> physical_vnets_bandwidth =
103  m_network_ptr->params().physical_vnets_bandwidth;
104  physical_vnets_bandwidth.resize(out.size(), bw_multiplier);
105 
106  throttles.emplace_back(m_id, m_network_ptr->params().ruby_system,
107  throttles.size(), link_latency,
108  physical_vnets_channels, physical_vnets_bandwidth,
110  } else {
111  throttles.emplace_back(m_id, m_network_ptr->params().ruby_system,
112  throttles.size(), link_latency, bw_multiplier,
114  }
115 
116  // Create one buffer per vnet (these are intermediaryQueues)
117  std::vector<MessageBuffer*> intermediateBuffers;
118 
119  for (int i = 0; i < out.size(); ++i) {
120  assert(m_num_connected_buffers < m_port_buffers.size());
121  MessageBuffer* buffer_ptr =
124  intermediateBuffers.push_back(buffer_ptr);
125  }
126 
127  Tick routing_latency = is_external ? cyclesToTicks(m_ext_routing_latency) :
129  // Hook the queues to the PerfectSwitch
130  perfectSwitch.addOutPort(intermediateBuffers, routing_table_entry,
131  dst_inport, routing_latency, link_weight);
132 
133  // Hook the queues to the Throttle
134  throttles.back().addLinks(intermediateBuffers, out);
135 }
136 
137 void
139 {
141 
142  for (const auto& throttle : throttles) {
143  switchStats.m_avg_utilization += throttle.getUtilization();
144  }
146 
147  for (unsigned int type = MessageSizeType_FIRST;
148  type < MessageSizeType_NUM; ++type) {
150  csprintf("msg_count.%s",
151  MessageSizeType_to_string(MessageSizeType(type))).c_str());
154  ;
155 
157  csprintf("msg_bytes.%s",
158  MessageSizeType_to_string(MessageSizeType(type))).c_str());
161  ;
162 
163  for (const auto& throttle : throttles) {
164  *(switchStats.m_msg_counts[type]) += throttle.getMsgCount(type);
165  }
168  Network::MessageSizeType_to_int(MessageSizeType(type)));
169  }
170 }
171 
172 void
174 {
176 }
177 
178 void
180 {
182 }
183 
184 void
185 Switch::print(std::ostream& out) const
186 {
187  // FIXME printing
188  out << "[Switch]";
189 }
190 
191 bool
193 {
194  for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
195  if (m_port_buffers[i]->functionalRead(pkt))
196  return true;
197  }
198  return false;
199 }
200 
201 bool
203 {
204  bool read = false;
205  for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
206  if (m_port_buffers[i]->functionalRead(pkt, mask))
207  read = true;
208  }
209  return read;
210 }
211 
212 uint32_t
214 {
215  // Access the buffers in the switch for performing a functional write
216  uint32_t num_functional_writes = 0;
217  for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
218  num_functional_writes += m_port_buffers[i]->functionalWrite(pkt);
219  }
220  return num_functional_writes;
221 }
222 
223 Switch::
225  : statistics::Group(parent),
226  m_avg_utilization(this, "percent_links_utilized")
227 {
228 
229 }
230 
231 } // namespace ruby
232 } // namespace gem5
gem5::ruby::Switch::m_ext_routing_latency
const Cycles m_ext_routing_latency
Definition: Switch.hh:124
gem5::ruby::WriteMask
Definition: WriteMask.hh:59
gem5::ruby::Switch::addInPort
void addInPort(const std::vector< MessageBuffer * > &in)
Definition: Switch.cc:82
gem5::ruby::PortDirection
std::string PortDirection
Definition: TypeDefines.hh:44
gem5::ruby::Network::MessageSizeType_to_int
static uint32_t MessageSizeType_to_int(MessageSizeType size_type)
Definition: Network.cc:164
gem5::ruby::BasicRouter
Definition: BasicRouter.hh:45
gem5::ruby::PerfectSwitch::clearStats
void clearStats()
Definition: PerfectSwitch.cc:308
gem5::ruby::Switch::resetStats
void resetStats()
Callback to reset stats.
Definition: Switch.cc:173
gem5::ruby::Switch::Params
SwitchParams Params
Definition: Switch.hh:87
gem5::ruby::Switch::m_num_connected_buffers
unsigned m_num_connected_buffers
Definition: Switch.hh:128
gem5::statistics::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:68
gem5::ruby::Switch::m_port_buffers
std::vector< MessageBuffer * > m_port_buffers
Definition: Switch.hh:129
gem5::ruby::BasicRouter::init
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: BasicRouter.cc:45
gem5::ruby::BasicRouter::m_id
uint32_t m_id
Definition: BasicRouter.hh:58
SimpleNetwork.hh
cast.hh
gem5::ruby::Switch::collateStats
void collateStats()
Definition: Switch.cc:179
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
gem5::ruby::Switch::functionalWrite
uint32_t functionalWrite(Packet *)
Definition: Switch.cc:213
std::vector
STL vector class.
Definition: stl.hh:37
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::ruby::PerfectSwitch::collateStats
void collateStats()
Definition: PerfectSwitch.cc:312
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ruby::Switch::switchStats
gem5::ruby::Switch::SwitchStats switchStats
gem5::ruby::Switch::SwitchStats::m_msg_bytes
statistics::Formula * m_msg_bytes[MessageSizeType_NUM]
Definition: Switch.hh:140
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::statistics::constant
Temp constant(T val)
Definition: statistics.hh:2865
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::ruby::Switch::regStats
void regStats()
Callback to set stat parameters.
Definition: Switch.cc:138
gem5::ruby::PerfectSwitch::addInPort
void addInPort(const std::vector< MessageBuffer * > &in)
Definition: PerfectSwitch.cc:81
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ruby::Switch::functionalRead
bool functionalRead(Packet *)
Definition: Switch.cc:192
gem5::ruby::BaseRoutingUnit::init_parent
void init_parent(Switch *parent_switch)
Definition: BaseRoutingUnit.hh:89
gem5::Clocked::cyclesToTicks
Tick cyclesToTicks(Cycles c) const
Definition: clocked_object.hh:227
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::ruby::PerfectSwitch::init
void init(SimpleNetwork *)
Definition: PerfectSwitch.cc:71
gem5::ruby::Switch::SwitchStats::SwitchStats
SwitchStats(statistics::Group *parent)
Definition: Switch.cc:224
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::ruby::Switch::m_routing_unit
BaseRoutingUnit & m_routing_unit
Definition: Switch.hh:126
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ruby::Switch::SwitchStats::m_msg_counts
statistics::Formula * m_msg_counts[MessageSizeType_NUM]
Definition: Switch.hh:139
gem5::ruby::Switch::addOutPort
void addOutPort(const std::vector< MessageBuffer * > &out, const NetDest &routing_table_entry, Cycles link_latency, int link_weight, int bw_multiplier, bool is_external, PortDirection dst_inport="")
Definition: Switch.cc:88
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::ruby::Switch::perfectSwitch
PerfectSwitch perfectSwitch
Definition: Switch.hh:119
gem5::ruby::Switch::m_network_ptr
SimpleNetwork * m_network_ptr
Definition: Switch.hh:120
gem5::ruby::PerfectSwitch::addOutPort
void addOutPort(const std::vector< MessageBuffer * > &out, const NetDest &routing_table_entry, const PortDirection &dst_inport, Tick routing_latency, int link_weight)
Definition: PerfectSwitch.cc:122
gem5::ruby::Switch::SwitchStats::m_avg_utilization
statistics::Formula m_avg_utilization
Definition: Switch.hh:138
gem5::ruby::Switch::print
void print(std::ostream &out) const
Definition: Switch.cc:185
gem5::statistics::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:69
gem5::ruby::NetDest
Definition: NetDest.hh:45
MessageBuffer.hh
gem5::ruby::SimpleNetwork::getEndpointBandwidth
int getEndpointBandwidth()
Definition: SimpleNetwork.hh:72
Switch.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::statistics::DataWrap::flags
Derived & flags(Flags _flags)
Set the flags and marks this stat to print at the end of simulation.
Definition: statistics.hh:358
gem5::ruby::MessageBuffer
Definition: MessageBuffer.hh:74
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ruby::Switch::m_int_routing_latency
const Cycles m_int_routing_latency
Definition: Switch.hh:123
gem5::ruby::Switch::throttles
std::list< Throttle > throttles
Definition: Switch.hh:121
stl_helpers.hh
gem5::ruby::Switch::init
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: Switch.cc:74
gem5::ruby::Switch::Switch
Switch(const Params &p)
Definition: Switch.cc:59

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