gem5  v21.1.0.2
a9scu.cc
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37 
38 #include "dev/arm/a9scu.hh"
39 
40 #include "base/intmath.hh"
41 #include "base/trace.hh"
42 #include "mem/packet.hh"
43 #include "mem/packet_access.hh"
44 #include "sim/system.hh"
45 
46 namespace gem5
47 {
48 
50  : BasicPioDevice(p, 0x60)
51 {
52 }
53 
54 Tick
56 {
57  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
58  assert(pkt->getSize() == 4);
59  Addr daddr = pkt->getAddr() - pioAddr;
60 
61  switch(daddr) {
62  case Control:
63  pkt->setLE(1); // SCU already enabled
64  break;
65  case Config:
66  {
67  /* Without making a completely new SCU, we can use the core count
68  * field as 4 bits and inform the OS of up to 16 CPUs. Although
69  * the core count is technically bits [1:0] only, bits [3:2] are
70  * SBZ for future expansion like this.
71  */
72  int threads = sys->threads.size();
73  if (threads > 4) {
74  warn_once("A9SCU with >4 CPUs is unsupported");
75  fatal_if(threads > 15,
76  "Too many CPUs (%d) for A9SCU!", threads);
77  }
78  int smp_bits, core_cnt;
79  smp_bits = (1 << threads) - 1;
80  core_cnt = threads - 1;
81  pkt->setLE(smp_bits << 4 | core_cnt);
82  }
83  break;
84  default:
85  // Only configuration register is implemented
86  panic("Tried to read SCU at offset %#x\n", daddr);
87  break;
88  }
89  pkt->makeAtomicResponse();
90  return pioDelay;
91 
92 }
93 
94 Tick
96 {
97  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
98 
99  Addr daddr = pkt->getAddr() - pioAddr;
100  switch (daddr) {
101  default:
102  // Nothing implemented at this point
103  warn("Tried to write SCU at offset %#x\n", daddr);
104  break;
105  }
106  pkt->makeAtomicResponse();
107  return pioDelay;
108 }
109 
110 } // namespace gem5
gem5::BasicPioDevice::pioAddr
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:151
warn
#define warn(...)
Definition: logging.hh:245
gem5::System::Threads::size
int size() const
Definition: system.hh:216
a9scu.hh
system.hh
warn_once
#define warn_once(...)
Definition: logging.hh:249
gem5::A9SCU::Control
@ Control
Definition: a9scu.hh:56
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
packet.hh
gem5::A9SCU::write
virtual Tick write(PacketPtr pkt)
All writes are panic.
Definition: a9scu.cc:95
gem5::A9SCU::read
virtual Tick read(PacketPtr pkt)
Handle a read to the device.
Definition: a9scu.cc:55
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::A9SCU::A9SCU
A9SCU(const Params &p)
The constructor for RealView just registers itself with the MMU.
Definition: a9scu.cc:49
gem5::PioDevice::sys
System * sys
Definition: io_device.hh:105
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
packet_access.hh
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::BasicPioDevice::pioSize
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:154
trace.hh
gem5::Packet::setLE
void setLE(T v)
Set the value in the data pointer to v as little endian.
Definition: packet_access.hh:108
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
intmath.hh
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::A9SCU::Params
A9SCUParams Params
Definition: a9scu.hh:61
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::A9SCU::Config
@ Config
Definition: a9scu.hh:57

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