gem5  v22.0.0.2
gpu_static_inst.hh
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31 
32 #ifndef __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
33 #define __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
34 
40 #include "gpu-compute/wavefront.hh"
41 
42 namespace gem5
43 {
44 
45 namespace Gcn3ISA
46 {
48  {
49  public:
50  GCN3GPUStaticInst(const std::string &opcode);
52 
53  void generateDisassembly() override { disassembly = _opcode; }
54 
55  bool
56  isFlatScratchRegister(int opIdx) override
57  {
58  return isFlatScratchReg(opIdx);
59  }
60 
61  bool
62  isExecMaskRegister(int opIdx) override
63  {
64  return isExecMask(opIdx);
65  }
66 
67  void initOperandInfo() override { return; }
68  int getOperandSize(int opIdx) override { return 0; }
69 
77  int coalescerTokenCount() const override { return 1; }
78  ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
79 
80  protected:
81  void panicUnimplemented() const;
82 
89  }; // class GCN3GPUStaticInst
90 
91 } // namespace Gcn3ISA
92 } // namespace gem5
93 
94 #endif //__ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
gem5::Gcn3ISA::GCN3GPUStaticInst::generateDisassembly
void generateDisassembly() override
Definition: gpu_static_inst.hh:53
gem5::Gcn3ISA::GCN3GPUStaticInst::srcLiteral
ScalarRegU32 srcLiteral() const override
Definition: gpu_static_inst.hh:78
gem5::Gcn3ISA::GCN3GPUStaticInst::_srcLiteral
ScalarRegU32 _srcLiteral
if the instruction has a src literal - an immediate value that is part of the instruction stream - we...
Definition: gpu_static_inst.hh:88
gem5::GPUStaticInst::disassembly
std::string disassembly
Definition: gpu_static_inst.hh:299
gpu_registers.hh
gpu_static_inst.hh
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:61
gem5::Gcn3ISA::GCN3GPUStaticInst::isFlatScratchRegister
bool isFlatScratchRegister(int opIdx) override
Definition: gpu_static_inst.hh:56
gem5::Gcn3ISA::isExecMask
bool isExecMask(int opIdx)
Definition: registers.cc:198
wavefront.hh
gem5::GPUStaticInst::opcode
const std::string & opcode() const
Definition: gpu_static_inst.hh:263
vector_register_file.hh
gem5::Gcn3ISA::GCN3GPUStaticInst::initOperandInfo
void initOperandInfo() override
Definition: gpu_static_inst.hh:67
gem5::Gcn3ISA::GCN3GPUStaticInst::isExecMaskRegister
bool isExecMaskRegister(int opIdx) override
Definition: gpu_static_inst.hh:62
scalar_register_file.hh
operand.hh
gem5::Gcn3ISA::GCN3GPUStaticInst::~GCN3GPUStaticInst
~GCN3GPUStaticInst()
Definition: gpu_static_inst.cc:49
gem5::Gcn3ISA::GCN3GPUStaticInst::GCN3GPUStaticInst
GCN3GPUStaticInst(const std::string &opcode)
Definition: gpu_static_inst.cc:44
gem5::GPUStaticInst::_opcode
const std::string _opcode
Definition: gpu_static_inst.hh:298
gem5::Gcn3ISA::GCN3GPUStaticInst::coalescerTokenCount
int coalescerTokenCount() const override
Return the number of tokens needed by the coalescer.
Definition: gpu_static_inst.hh:77
gem5::Gcn3ISA::GCN3GPUStaticInst::getOperandSize
int getOperandSize(int opIdx) override
Definition: gpu_static_inst.hh:68
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Gcn3ISA::GCN3GPUStaticInst::panicUnimplemented
void panicUnimplemented() const
Definition: gpu_static_inst.cc:54
gem5::Gcn3ISA::isFlatScratchReg
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:210
gem5::Gcn3ISA::ScalarRegU32
uint32_t ScalarRegU32
Definition: gpu_registers.hh:153
gem5::Gcn3ISA::GCN3GPUStaticInst
Definition: gpu_static_inst.hh:47

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