gem5  v22.1.0.0
gpu_static_inst.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
33 #define __ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
34 
40 #include "gpu-compute/wavefront.hh"
41 
42 namespace gem5
43 {
44 
45 namespace Gcn3ISA
46 {
48  {
49  public:
50  GCN3GPUStaticInst(const std::string &opcode);
52 
53  void generateDisassembly() override { disassembly = _opcode; }
54 
55  bool
56  isFlatScratchRegister(int opIdx) override
57  {
58  return isFlatScratchReg(opIdx);
59  }
60 
61  bool
62  isExecMaskRegister(int opIdx) override
63  {
64  return isExecMask(opIdx);
65  }
66 
67  void initOperandInfo() override { return; }
68  int getOperandSize(int opIdx) override { return 0; }
69 
77  int coalescerTokenCount() const override { return 1; }
78  ScalarRegU32 srcLiteral() const override { return _srcLiteral; }
79 
80  protected:
81  void panicUnimplemented() const;
82 
89  }; // class GCN3GPUStaticInst
90 
91 } // namespace Gcn3ISA
92 } // namespace gem5
93 
94 #endif //__ARCH_GCN3_INSTS_GPU_STATIC_INST_HH__
const std::string & opcode() const
const std::string _opcode
ScalarRegU32 srcLiteral() const override
int coalescerTokenCount() const override
Return the number of tokens needed by the coalescer.
bool isExecMaskRegister(int opIdx) override
ScalarRegU32 _srcLiteral
if the instruction has a src literal - an immediate value that is part of the instruction stream - we...
bool isFlatScratchRegister(int opIdx) override
GCN3GPUStaticInst(const std::string &opcode)
int getOperandSize(int opIdx) override
bool isFlatScratchReg(int opIdx)
Definition: registers.cc:213
bool isExecMask(int opIdx)
Definition: registers.cc:201
uint32_t ScalarRegU32
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....

Generated on Wed Dec 21 2022 10:22:16 for gem5 by doxygen 1.9.1