gem5  v21.1.0.2
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gem5::Gcn3ISA Namespace Reference

classes that represnt vector/scalar operands in GCN3 ISA. More...

Classes

struct  BufferRsrcDescriptor
 
class  Decoder
 
class  GCN3GPUStaticInst
 
class  GPUISA
 
struct  InFmt_DS
 
struct  InFmt_DS_1
 
struct  InFmt_EXP
 
struct  InFmt_EXP_1
 
struct  InFmt_FLAT
 
struct  InFmt_FLAT_1
 
struct  InFmt_INST
 
struct  InFmt_MIMG
 
struct  InFmt_MIMG_1
 
struct  InFmt_MTBUF
 
struct  InFmt_MTBUF_1
 
struct  InFmt_MUBUF
 
struct  InFmt_MUBUF_1
 
struct  InFmt_SMEM
 
struct  InFmt_SMEM_1
 
struct  InFmt_SOP1
 
struct  InFmt_SOP2
 
struct  InFmt_SOPC
 
struct  InFmt_SOPK
 
struct  InFmt_SOPP
 
struct  InFmt_VINTRP
 
struct  InFmt_VOP1
 
struct  InFmt_VOP2
 
struct  InFmt_VOP3
 
struct  InFmt_VOP3_1
 
struct  InFmt_VOP3_SDST_ENC
 
struct  InFmt_VOP_DPP
 
struct  InFmt_VOP_SDWA
 
struct  InFmt_VOPC
 
class  Inst_DS
 
class  Inst_DS__DS_ADD_F32
 
class  Inst_DS__DS_ADD_RTN_F32
 
class  Inst_DS__DS_ADD_RTN_U32
 
class  Inst_DS__DS_ADD_RTN_U64
 
class  Inst_DS__DS_ADD_SRC2_F32
 
class  Inst_DS__DS_ADD_SRC2_U32
 
class  Inst_DS__DS_ADD_SRC2_U64
 
class  Inst_DS__DS_ADD_U32
 
class  Inst_DS__DS_ADD_U64
 
class  Inst_DS__DS_AND_B32
 
class  Inst_DS__DS_AND_B64
 
class  Inst_DS__DS_AND_RTN_B32
 
class  Inst_DS__DS_AND_RTN_B64
 
class  Inst_DS__DS_AND_SRC2_B32
 
class  Inst_DS__DS_AND_SRC2_B64
 
class  Inst_DS__DS_APPEND
 
class  Inst_DS__DS_BPERMUTE_B32
 
class  Inst_DS__DS_CMPST_B32
 
class  Inst_DS__DS_CMPST_B64
 
class  Inst_DS__DS_CMPST_F32
 
class  Inst_DS__DS_CMPST_F64
 
class  Inst_DS__DS_CMPST_RTN_B32
 
class  Inst_DS__DS_CMPST_RTN_B64
 
class  Inst_DS__DS_CMPST_RTN_F32
 
class  Inst_DS__DS_CMPST_RTN_F64
 
class  Inst_DS__DS_CONDXCHG32_RTN_B64
 
class  Inst_DS__DS_CONSUME
 
class  Inst_DS__DS_DEC_RTN_U32
 
class  Inst_DS__DS_DEC_RTN_U64
 
class  Inst_DS__DS_DEC_SRC2_U32
 
class  Inst_DS__DS_DEC_SRC2_U64
 
class  Inst_DS__DS_DEC_U32
 
class  Inst_DS__DS_DEC_U64
 
class  Inst_DS__DS_GWS_BARRIER
 
class  Inst_DS__DS_GWS_INIT
 
class  Inst_DS__DS_GWS_SEMA_BR
 
class  Inst_DS__DS_GWS_SEMA_P
 
class  Inst_DS__DS_GWS_SEMA_RELEASE_ALL
 
class  Inst_DS__DS_GWS_SEMA_V
 
class  Inst_DS__DS_INC_RTN_U32
 
class  Inst_DS__DS_INC_RTN_U64
 
class  Inst_DS__DS_INC_SRC2_U32
 
class  Inst_DS__DS_INC_SRC2_U64
 
class  Inst_DS__DS_INC_U32
 
class  Inst_DS__DS_INC_U64
 
class  Inst_DS__DS_MAX_F32
 
class  Inst_DS__DS_MAX_F64
 
class  Inst_DS__DS_MAX_I32
 
class  Inst_DS__DS_MAX_I64
 
class  Inst_DS__DS_MAX_RTN_F32
 
class  Inst_DS__DS_MAX_RTN_F64
 
class  Inst_DS__DS_MAX_RTN_I32
 
class  Inst_DS__DS_MAX_RTN_I64
 
class  Inst_DS__DS_MAX_RTN_U32
 
class  Inst_DS__DS_MAX_RTN_U64
 
class  Inst_DS__DS_MAX_SRC2_F32
 
class  Inst_DS__DS_MAX_SRC2_F64
 
class  Inst_DS__DS_MAX_SRC2_I32
 
class  Inst_DS__DS_MAX_SRC2_I64
 
class  Inst_DS__DS_MAX_SRC2_U32
 
class  Inst_DS__DS_MAX_SRC2_U64
 
class  Inst_DS__DS_MAX_U32
 
class  Inst_DS__DS_MAX_U64
 
class  Inst_DS__DS_MIN_F32
 
class  Inst_DS__DS_MIN_F64
 
class  Inst_DS__DS_MIN_I32
 
class  Inst_DS__DS_MIN_I64
 
class  Inst_DS__DS_MIN_RTN_F32
 
class  Inst_DS__DS_MIN_RTN_F64
 
class  Inst_DS__DS_MIN_RTN_I32
 
class  Inst_DS__DS_MIN_RTN_I64
 
class  Inst_DS__DS_MIN_RTN_U32
 
class  Inst_DS__DS_MIN_RTN_U64
 
class  Inst_DS__DS_MIN_SRC2_F32
 
class  Inst_DS__DS_MIN_SRC2_F64
 
class  Inst_DS__DS_MIN_SRC2_I32
 
class  Inst_DS__DS_MIN_SRC2_I64
 
class  Inst_DS__DS_MIN_SRC2_U32
 
class  Inst_DS__DS_MIN_SRC2_U64
 
class  Inst_DS__DS_MIN_U32
 
class  Inst_DS__DS_MIN_U64
 
class  Inst_DS__DS_MSKOR_B32
 
class  Inst_DS__DS_MSKOR_B64
 
class  Inst_DS__DS_MSKOR_RTN_B32
 
class  Inst_DS__DS_MSKOR_RTN_B64
 
class  Inst_DS__DS_NOP
 
class  Inst_DS__DS_OR_B32
 
class  Inst_DS__DS_OR_B64
 
class  Inst_DS__DS_OR_RTN_B32
 
class  Inst_DS__DS_OR_RTN_B64
 
class  Inst_DS__DS_OR_SRC2_B32
 
class  Inst_DS__DS_OR_SRC2_B64
 
class  Inst_DS__DS_ORDERED_COUNT
 
class  Inst_DS__DS_PERMUTE_B32
 
class  Inst_DS__DS_READ2_B32
 
class  Inst_DS__DS_READ2_B64
 
class  Inst_DS__DS_READ2ST64_B32
 
class  Inst_DS__DS_READ2ST64_B64
 
class  Inst_DS__DS_READ_B128
 
class  Inst_DS__DS_READ_B32
 
class  Inst_DS__DS_READ_B64
 
class  Inst_DS__DS_READ_B96
 
class  Inst_DS__DS_READ_I16
 
class  Inst_DS__DS_READ_I8
 
class  Inst_DS__DS_READ_U16
 
class  Inst_DS__DS_READ_U8
 
class  Inst_DS__DS_RSUB_RTN_U32
 
class  Inst_DS__DS_RSUB_RTN_U64
 
class  Inst_DS__DS_RSUB_SRC2_U32
 
class  Inst_DS__DS_RSUB_SRC2_U64
 
class  Inst_DS__DS_RSUB_U32
 
class  Inst_DS__DS_RSUB_U64
 
class  Inst_DS__DS_SUB_RTN_U32
 
class  Inst_DS__DS_SUB_RTN_U64
 
class  Inst_DS__DS_SUB_SRC2_U32
 
class  Inst_DS__DS_SUB_SRC2_U64
 
class  Inst_DS__DS_SUB_U32
 
class  Inst_DS__DS_SUB_U64
 
class  Inst_DS__DS_SWIZZLE_B32
 
class  Inst_DS__DS_WRAP_RTN_B32
 
class  Inst_DS__DS_WRITE2_B32
 
class  Inst_DS__DS_WRITE2_B64
 
class  Inst_DS__DS_WRITE2ST64_B32
 
class  Inst_DS__DS_WRITE2ST64_B64
 
class  Inst_DS__DS_WRITE_B128
 
class  Inst_DS__DS_WRITE_B16
 
class  Inst_DS__DS_WRITE_B32
 
class  Inst_DS__DS_WRITE_B64
 
class  Inst_DS__DS_WRITE_B8
 
class  Inst_DS__DS_WRITE_B96
 
class  Inst_DS__DS_WRITE_SRC2_B32
 
class  Inst_DS__DS_WRITE_SRC2_B64
 
class  Inst_DS__DS_WRXCHG2_RTN_B32
 
class  Inst_DS__DS_WRXCHG2_RTN_B64
 
class  Inst_DS__DS_WRXCHG2ST64_RTN_B32
 
class  Inst_DS__DS_WRXCHG2ST64_RTN_B64
 
class  Inst_DS__DS_WRXCHG_RTN_B32
 
class  Inst_DS__DS_WRXCHG_RTN_B64
 
class  Inst_DS__DS_XOR_B32
 
class  Inst_DS__DS_XOR_B64
 
class  Inst_DS__DS_XOR_RTN_B32
 
class  Inst_DS__DS_XOR_RTN_B64
 
class  Inst_DS__DS_XOR_SRC2_B32
 
class  Inst_DS__DS_XOR_SRC2_B64
 
class  Inst_EXP
 
class  Inst_EXP__EXP
 
class  Inst_FLAT
 
class  Inst_FLAT__FLAT_ATOMIC_ADD
 
class  Inst_FLAT__FLAT_ATOMIC_ADD_X2
 
class  Inst_FLAT__FLAT_ATOMIC_AND
 
class  Inst_FLAT__FLAT_ATOMIC_AND_X2
 
class  Inst_FLAT__FLAT_ATOMIC_CMPSWAP
 
class  Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
 
class  Inst_FLAT__FLAT_ATOMIC_DEC
 
class  Inst_FLAT__FLAT_ATOMIC_DEC_X2
 
class  Inst_FLAT__FLAT_ATOMIC_INC
 
class  Inst_FLAT__FLAT_ATOMIC_INC_X2
 
class  Inst_FLAT__FLAT_ATOMIC_OR
 
class  Inst_FLAT__FLAT_ATOMIC_OR_X2
 
class  Inst_FLAT__FLAT_ATOMIC_SMAX
 
class  Inst_FLAT__FLAT_ATOMIC_SMAX_X2
 
class  Inst_FLAT__FLAT_ATOMIC_SMIN
 
class  Inst_FLAT__FLAT_ATOMIC_SMIN_X2
 
class  Inst_FLAT__FLAT_ATOMIC_SUB
 
class  Inst_FLAT__FLAT_ATOMIC_SUB_X2
 
class  Inst_FLAT__FLAT_ATOMIC_SWAP
 
class  Inst_FLAT__FLAT_ATOMIC_SWAP_X2
 
class  Inst_FLAT__FLAT_ATOMIC_UMAX
 
class  Inst_FLAT__FLAT_ATOMIC_UMAX_X2
 
class  Inst_FLAT__FLAT_ATOMIC_UMIN
 
class  Inst_FLAT__FLAT_ATOMIC_UMIN_X2
 
class  Inst_FLAT__FLAT_ATOMIC_XOR
 
class  Inst_FLAT__FLAT_ATOMIC_XOR_X2
 
class  Inst_FLAT__FLAT_LOAD_DWORD
 
class  Inst_FLAT__FLAT_LOAD_DWORDX2
 
class  Inst_FLAT__FLAT_LOAD_DWORDX3
 
class  Inst_FLAT__FLAT_LOAD_DWORDX4
 
class  Inst_FLAT__FLAT_LOAD_SBYTE
 
class  Inst_FLAT__FLAT_LOAD_SSHORT
 
class  Inst_FLAT__FLAT_LOAD_UBYTE
 
class  Inst_FLAT__FLAT_LOAD_USHORT
 
class  Inst_FLAT__FLAT_STORE_BYTE
 
class  Inst_FLAT__FLAT_STORE_DWORD
 
class  Inst_FLAT__FLAT_STORE_DWORDX2
 
class  Inst_FLAT__FLAT_STORE_DWORDX3
 
class  Inst_FLAT__FLAT_STORE_DWORDX4
 
class  Inst_FLAT__FLAT_STORE_SHORT
 
class  Inst_MIMG
 
class  Inst_MIMG__IMAGE_ATOMIC_ADD
 
class  Inst_MIMG__IMAGE_ATOMIC_AND
 
class  Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
 
class  Inst_MIMG__IMAGE_ATOMIC_DEC
 
class  Inst_MIMG__IMAGE_ATOMIC_INC
 
class  Inst_MIMG__IMAGE_ATOMIC_OR
 
class  Inst_MIMG__IMAGE_ATOMIC_SMAX
 
class  Inst_MIMG__IMAGE_ATOMIC_SMIN
 
class  Inst_MIMG__IMAGE_ATOMIC_SUB
 
class  Inst_MIMG__IMAGE_ATOMIC_SWAP
 
class  Inst_MIMG__IMAGE_ATOMIC_UMAX
 
class  Inst_MIMG__IMAGE_ATOMIC_UMIN
 
class  Inst_MIMG__IMAGE_ATOMIC_XOR
 
class  Inst_MIMG__IMAGE_GATHER4
 
class  Inst_MIMG__IMAGE_GATHER4_B
 
class  Inst_MIMG__IMAGE_GATHER4_B_CL
 
class  Inst_MIMG__IMAGE_GATHER4_B_CL_O
 
class  Inst_MIMG__IMAGE_GATHER4_B_O
 
class  Inst_MIMG__IMAGE_GATHER4_C
 
class  Inst_MIMG__IMAGE_GATHER4_C_B
 
class  Inst_MIMG__IMAGE_GATHER4_C_B_CL
 
class  Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
 
class  Inst_MIMG__IMAGE_GATHER4_C_B_O
 
class  Inst_MIMG__IMAGE_GATHER4_C_CL
 
class  Inst_MIMG__IMAGE_GATHER4_C_CL_O
 
class  Inst_MIMG__IMAGE_GATHER4_C_L
 
class  Inst_MIMG__IMAGE_GATHER4_C_L_O
 
class  Inst_MIMG__IMAGE_GATHER4_C_LZ
 
class  Inst_MIMG__IMAGE_GATHER4_C_LZ_O
 
class  Inst_MIMG__IMAGE_GATHER4_C_O
 
class  Inst_MIMG__IMAGE_GATHER4_CL
 
class  Inst_MIMG__IMAGE_GATHER4_CL_O
 
class  Inst_MIMG__IMAGE_GATHER4_L
 
class  Inst_MIMG__IMAGE_GATHER4_L_O
 
class  Inst_MIMG__IMAGE_GATHER4_LZ
 
class  Inst_MIMG__IMAGE_GATHER4_LZ_O
 
class  Inst_MIMG__IMAGE_GATHER4_O
 
class  Inst_MIMG__IMAGE_GET_LOD
 
class  Inst_MIMG__IMAGE_GET_RESINFO
 
class  Inst_MIMG__IMAGE_LOAD
 
class  Inst_MIMG__IMAGE_LOAD_MIP
 
class  Inst_MIMG__IMAGE_LOAD_MIP_PCK
 
class  Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
 
class  Inst_MIMG__IMAGE_LOAD_PCK
 
class  Inst_MIMG__IMAGE_LOAD_PCK_SGN
 
class  Inst_MIMG__IMAGE_SAMPLE
 
class  Inst_MIMG__IMAGE_SAMPLE_B
 
class  Inst_MIMG__IMAGE_SAMPLE_B_CL
 
class  Inst_MIMG__IMAGE_SAMPLE_B_CL_O
 
class  Inst_MIMG__IMAGE_SAMPLE_B_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C
 
class  Inst_MIMG__IMAGE_SAMPLE_C_B
 
class  Inst_MIMG__IMAGE_SAMPLE_C_B_CL
 
class  Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C_B_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C_CD
 
class  Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
 
class  Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C_CD_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C_CL
 
class  Inst_MIMG__IMAGE_SAMPLE_C_CL_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C_D
 
class  Inst_MIMG__IMAGE_SAMPLE_C_D_CL
 
class  Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C_D_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C_L
 
class  Inst_MIMG__IMAGE_SAMPLE_C_L_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C_LZ
 
class  Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
 
class  Inst_MIMG__IMAGE_SAMPLE_C_O
 
class  Inst_MIMG__IMAGE_SAMPLE_CD
 
class  Inst_MIMG__IMAGE_SAMPLE_CD_CL
 
class  Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
 
class  Inst_MIMG__IMAGE_SAMPLE_CD_O
 
class  Inst_MIMG__IMAGE_SAMPLE_CL
 
class  Inst_MIMG__IMAGE_SAMPLE_CL_O
 
class  Inst_MIMG__IMAGE_SAMPLE_D
 
class  Inst_MIMG__IMAGE_SAMPLE_D_CL
 
class  Inst_MIMG__IMAGE_SAMPLE_D_CL_O
 
class  Inst_MIMG__IMAGE_SAMPLE_D_O
 
class  Inst_MIMG__IMAGE_SAMPLE_L
 
class  Inst_MIMG__IMAGE_SAMPLE_L_O
 
class  Inst_MIMG__IMAGE_SAMPLE_LZ
 
class  Inst_MIMG__IMAGE_SAMPLE_LZ_O
 
class  Inst_MIMG__IMAGE_SAMPLE_O
 
class  Inst_MIMG__IMAGE_STORE
 
class  Inst_MIMG__IMAGE_STORE_MIP
 
class  Inst_MIMG__IMAGE_STORE_MIP_PCK
 
class  Inst_MIMG__IMAGE_STORE_PCK
 
class  Inst_MTBUF
 
class  Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
 
class  Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
 
class  Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
 
class  Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
 
class  Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
 
class  Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
 
class  Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
 
class  Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
 
class  Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
 
class  Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
 
class  Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
 
class  Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
 
class  Inst_MTBUF__TBUFFER_STORE_FORMAT_X
 
class  Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
 
class  Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
 
class  Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
 
class  Inst_MUBUF
 
class  Inst_MUBUF__BUFFER_ATOMIC_ADD
 
class  Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_AND
 
class  Inst_MUBUF__BUFFER_ATOMIC_AND_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
 
class  Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_DEC
 
class  Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_INC
 
class  Inst_MUBUF__BUFFER_ATOMIC_INC_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_OR
 
class  Inst_MUBUF__BUFFER_ATOMIC_OR_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_SMAX
 
class  Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_SMIN
 
class  Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_SUB
 
class  Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_SWAP
 
class  Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_UMAX
 
class  Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_UMIN
 
class  Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
 
class  Inst_MUBUF__BUFFER_ATOMIC_XOR
 
class  Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
 
class  Inst_MUBUF__BUFFER_LOAD_DWORD
 
class  Inst_MUBUF__BUFFER_LOAD_DWORDX2
 
class  Inst_MUBUF__BUFFER_LOAD_DWORDX3
 
class  Inst_MUBUF__BUFFER_LOAD_DWORDX4
 
class  Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
 
class  Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
 
class  Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
 
class  Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
 
class  Inst_MUBUF__BUFFER_LOAD_FORMAT_X
 
class  Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
 
class  Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
 
class  Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
 
class  Inst_MUBUF__BUFFER_LOAD_SBYTE
 
class  Inst_MUBUF__BUFFER_LOAD_SSHORT
 
class  Inst_MUBUF__BUFFER_LOAD_UBYTE
 
class  Inst_MUBUF__BUFFER_LOAD_USHORT
 
class  Inst_MUBUF__BUFFER_STORE_BYTE
 
class  Inst_MUBUF__BUFFER_STORE_DWORD
 
class  Inst_MUBUF__BUFFER_STORE_DWORDX2
 
class  Inst_MUBUF__BUFFER_STORE_DWORDX3
 
class  Inst_MUBUF__BUFFER_STORE_DWORDX4
 
class  Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
 
class  Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
 
class  Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
 
class  Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
 
class  Inst_MUBUF__BUFFER_STORE_FORMAT_X
 
class  Inst_MUBUF__BUFFER_STORE_FORMAT_XY
 
class  Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
 
class  Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
 
class  Inst_MUBUF__BUFFER_STORE_LDS_DWORD
 
class  Inst_MUBUF__BUFFER_STORE_SHORT
 
class  Inst_MUBUF__BUFFER_WBINVL1
 
class  Inst_MUBUF__BUFFER_WBINVL1_VOL
 
class  Inst_SMEM
 
class  Inst_SMEM__S_ATC_PROBE
 
class  Inst_SMEM__S_ATC_PROBE_BUFFER
 
class  Inst_SMEM__S_BUFFER_LOAD_DWORD
 
class  Inst_SMEM__S_BUFFER_LOAD_DWORDX16
 
class  Inst_SMEM__S_BUFFER_LOAD_DWORDX2
 
class  Inst_SMEM__S_BUFFER_LOAD_DWORDX4
 
class  Inst_SMEM__S_BUFFER_LOAD_DWORDX8
 
class  Inst_SMEM__S_BUFFER_STORE_DWORD
 
class  Inst_SMEM__S_BUFFER_STORE_DWORDX2
 
class  Inst_SMEM__S_BUFFER_STORE_DWORDX4
 
class  Inst_SMEM__S_DCACHE_INV
 
class  Inst_SMEM__S_DCACHE_INV_VOL
 
class  Inst_SMEM__S_DCACHE_WB
 
class  Inst_SMEM__S_DCACHE_WB_VOL
 
class  Inst_SMEM__S_LOAD_DWORD
 
class  Inst_SMEM__S_LOAD_DWORDX16
 
class  Inst_SMEM__S_LOAD_DWORDX2
 
class  Inst_SMEM__S_LOAD_DWORDX4
 
class  Inst_SMEM__S_LOAD_DWORDX8
 
class  Inst_SMEM__S_MEMREALTIME
 
class  Inst_SMEM__S_MEMTIME
 
class  Inst_SMEM__S_STORE_DWORD
 
class  Inst_SMEM__S_STORE_DWORDX2
 
class  Inst_SMEM__S_STORE_DWORDX4
 
class  Inst_SOP1
 
class  Inst_SOP1__S_ABS_I32
 
class  Inst_SOP1__S_AND_SAVEEXEC_B64
 
class  Inst_SOP1__S_ANDN2_SAVEEXEC_B64
 
class  Inst_SOP1__S_BCNT0_I32_B32
 
class  Inst_SOP1__S_BCNT0_I32_B64
 
class  Inst_SOP1__S_BCNT1_I32_B32
 
class  Inst_SOP1__S_BCNT1_I32_B64
 
class  Inst_SOP1__S_BITSET0_B32
 
class  Inst_SOP1__S_BITSET0_B64
 
class  Inst_SOP1__S_BITSET1_B32
 
class  Inst_SOP1__S_BITSET1_B64
 
class  Inst_SOP1__S_BREV_B32
 
class  Inst_SOP1__S_BREV_B64
 
class  Inst_SOP1__S_CBRANCH_JOIN
 
class  Inst_SOP1__S_CMOV_B32
 
class  Inst_SOP1__S_CMOV_B64
 
class  Inst_SOP1__S_FF0_I32_B32
 
class  Inst_SOP1__S_FF0_I32_B64
 
class  Inst_SOP1__S_FF1_I32_B32
 
class  Inst_SOP1__S_FF1_I32_B64
 
class  Inst_SOP1__S_FLBIT_I32
 
class  Inst_SOP1__S_FLBIT_I32_B32
 
class  Inst_SOP1__S_FLBIT_I32_B64
 
class  Inst_SOP1__S_FLBIT_I32_I64
 
class  Inst_SOP1__S_GETPC_B64
 
class  Inst_SOP1__S_MOV_B32
 
class  Inst_SOP1__S_MOV_B64
 
class  Inst_SOP1__S_MOV_FED_B32
 
class  Inst_SOP1__S_MOVRELD_B32
 
class  Inst_SOP1__S_MOVRELD_B64
 
class  Inst_SOP1__S_MOVRELS_B32
 
class  Inst_SOP1__S_MOVRELS_B64
 
class  Inst_SOP1__S_NAND_SAVEEXEC_B64
 
class  Inst_SOP1__S_NOR_SAVEEXEC_B64
 
class  Inst_SOP1__S_NOT_B32
 
class  Inst_SOP1__S_NOT_B64
 
class  Inst_SOP1__S_OR_SAVEEXEC_B64
 
class  Inst_SOP1__S_ORN2_SAVEEXEC_B64
 
class  Inst_SOP1__S_QUADMASK_B32
 
class  Inst_SOP1__S_QUADMASK_B64
 
class  Inst_SOP1__S_RFE_B64
 
class  Inst_SOP1__S_SET_GPR_IDX_IDX
 
class  Inst_SOP1__S_SETPC_B64
 
class  Inst_SOP1__S_SEXT_I32_I16
 
class  Inst_SOP1__S_SEXT_I32_I8
 
class  Inst_SOP1__S_SWAPPC_B64
 
class  Inst_SOP1__S_WQM_B32
 
class  Inst_SOP1__S_WQM_B64
 
class  Inst_SOP1__S_XNOR_SAVEEXEC_B64
 
class  Inst_SOP1__S_XOR_SAVEEXEC_B64
 
class  Inst_SOP2
 
class  Inst_SOP2__S_ABSDIFF_I32
 
class  Inst_SOP2__S_ADD_I32
 
class  Inst_SOP2__S_ADD_U32
 
class  Inst_SOP2__S_ADDC_U32
 
class  Inst_SOP2__S_AND_B32
 
class  Inst_SOP2__S_AND_B64
 
class  Inst_SOP2__S_ANDN2_B32
 
class  Inst_SOP2__S_ANDN2_B64
 
class  Inst_SOP2__S_ASHR_I32
 
class  Inst_SOP2__S_ASHR_I64
 
class  Inst_SOP2__S_BFE_I32
 
class  Inst_SOP2__S_BFE_I64
 
class  Inst_SOP2__S_BFE_U32
 
class  Inst_SOP2__S_BFE_U64
 
class  Inst_SOP2__S_BFM_B32
 
class  Inst_SOP2__S_BFM_B64
 
class  Inst_SOP2__S_CBRANCH_G_FORK
 
class  Inst_SOP2__S_CSELECT_B32
 
class  Inst_SOP2__S_CSELECT_B64
 
class  Inst_SOP2__S_LSHL_B32
 
class  Inst_SOP2__S_LSHL_B64
 
class  Inst_SOP2__S_LSHR_B32
 
class  Inst_SOP2__S_LSHR_B64
 
class  Inst_SOP2__S_MAX_I32
 
class  Inst_SOP2__S_MAX_U32
 
class  Inst_SOP2__S_MIN_I32
 
class  Inst_SOP2__S_MIN_U32
 
class  Inst_SOP2__S_MUL_I32
 
class  Inst_SOP2__S_NAND_B32
 
class  Inst_SOP2__S_NAND_B64
 
class  Inst_SOP2__S_NOR_B32
 
class  Inst_SOP2__S_NOR_B64
 
class  Inst_SOP2__S_OR_B32
 
class  Inst_SOP2__S_OR_B64
 
class  Inst_SOP2__S_ORN2_B32
 
class  Inst_SOP2__S_ORN2_B64
 
class  Inst_SOP2__S_RFE_RESTORE_B64
 
class  Inst_SOP2__S_SUB_I32
 
class  Inst_SOP2__S_SUB_U32
 
class  Inst_SOP2__S_SUBB_U32
 
class  Inst_SOP2__S_XNOR_B32
 
class  Inst_SOP2__S_XNOR_B64
 
class  Inst_SOP2__S_XOR_B32
 
class  Inst_SOP2__S_XOR_B64
 
class  Inst_SOPC
 
class  Inst_SOPC__S_BITCMP0_B32
 
class  Inst_SOPC__S_BITCMP0_B64
 
class  Inst_SOPC__S_BITCMP1_B32
 
class  Inst_SOPC__S_BITCMP1_B64
 
class  Inst_SOPC__S_CMP_EQ_I32
 
class  Inst_SOPC__S_CMP_EQ_U32
 
class  Inst_SOPC__S_CMP_EQ_U64
 
class  Inst_SOPC__S_CMP_GE_I32
 
class  Inst_SOPC__S_CMP_GE_U32
 
class  Inst_SOPC__S_CMP_GT_I32
 
class  Inst_SOPC__S_CMP_GT_U32
 
class  Inst_SOPC__S_CMP_LE_I32
 
class  Inst_SOPC__S_CMP_LE_U32
 
class  Inst_SOPC__S_CMP_LG_I32
 
class  Inst_SOPC__S_CMP_LG_U32
 
class  Inst_SOPC__S_CMP_LG_U64
 
class  Inst_SOPC__S_CMP_LT_I32
 
class  Inst_SOPC__S_CMP_LT_U32
 
class  Inst_SOPC__S_SET_GPR_IDX_ON
 
class  Inst_SOPC__S_SETVSKIP
 
class  Inst_SOPK
 
class  Inst_SOPK__S_ADDK_I32
 
class  Inst_SOPK__S_CBRANCH_I_FORK
 
class  Inst_SOPK__S_CMOVK_I32
 
class  Inst_SOPK__S_CMPK_EQ_I32
 
class  Inst_SOPK__S_CMPK_EQ_U32
 
class  Inst_SOPK__S_CMPK_GE_I32
 
class  Inst_SOPK__S_CMPK_GE_U32
 
class  Inst_SOPK__S_CMPK_GT_I32
 
class  Inst_SOPK__S_CMPK_GT_U32
 
class  Inst_SOPK__S_CMPK_LE_I32
 
class  Inst_SOPK__S_CMPK_LE_U32
 
class  Inst_SOPK__S_CMPK_LG_I32
 
class  Inst_SOPK__S_CMPK_LG_U32
 
class  Inst_SOPK__S_CMPK_LT_I32
 
class  Inst_SOPK__S_CMPK_LT_U32
 
class  Inst_SOPK__S_GETREG_B32
 
class  Inst_SOPK__S_MOVK_I32
 
class  Inst_SOPK__S_MULK_I32
 
class  Inst_SOPK__S_SETREG_B32
 
class  Inst_SOPK__S_SETREG_IMM32_B32
 
class  Inst_SOPP
 
class  Inst_SOPP__S_BARRIER
 
class  Inst_SOPP__S_BRANCH
 
class  Inst_SOPP__S_CBRANCH_CDBGSYS
 
class  Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
 
class  Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
 
class  Inst_SOPP__S_CBRANCH_CDBGUSER
 
class  Inst_SOPP__S_CBRANCH_EXECNZ
 
class  Inst_SOPP__S_CBRANCH_EXECZ
 
class  Inst_SOPP__S_CBRANCH_SCC0
 
class  Inst_SOPP__S_CBRANCH_SCC1
 
class  Inst_SOPP__S_CBRANCH_VCCNZ
 
class  Inst_SOPP__S_CBRANCH_VCCZ
 
class  Inst_SOPP__S_DECPERFLEVEL
 
class  Inst_SOPP__S_ENDPGM
 
class  Inst_SOPP__S_ENDPGM_SAVED
 
class  Inst_SOPP__S_ICACHE_INV
 
class  Inst_SOPP__S_INCPERFLEVEL
 
class  Inst_SOPP__S_NOP
 
class  Inst_SOPP__S_SENDMSG
 
class  Inst_SOPP__S_SENDMSGHALT
 
class  Inst_SOPP__S_SET_GPR_IDX_MODE
 
class  Inst_SOPP__S_SET_GPR_IDX_OFF
 
class  Inst_SOPP__S_SETHALT
 
class  Inst_SOPP__S_SETKILL
 
class  Inst_SOPP__S_SETPRIO
 
class  Inst_SOPP__S_SLEEP
 
class  Inst_SOPP__S_TRAP
 
class  Inst_SOPP__S_TTRACEDATA
 
class  Inst_SOPP__S_WAITCNT
 
class  Inst_SOPP__S_WAKEUP
 
class  Inst_VINTRP
 
class  Inst_VINTRP__V_INTERP_MOV_F32
 
class  Inst_VINTRP__V_INTERP_P1_F32
 
class  Inst_VINTRP__V_INTERP_P2_F32
 
class  Inst_VOP1
 
class  Inst_VOP1__V_BFREV_B32
 
class  Inst_VOP1__V_CEIL_F16
 
class  Inst_VOP1__V_CEIL_F32
 
class  Inst_VOP1__V_CEIL_F64
 
class  Inst_VOP1__V_CLREXCP
 
class  Inst_VOP1__V_COS_F16
 
class  Inst_VOP1__V_COS_F32
 
class  Inst_VOP1__V_CVT_F16_F32
 
class  Inst_VOP1__V_CVT_F16_I16
 
class  Inst_VOP1__V_CVT_F16_U16
 
class  Inst_VOP1__V_CVT_F32_F16
 
class  Inst_VOP1__V_CVT_F32_F64
 
class  Inst_VOP1__V_CVT_F32_I32
 
class  Inst_VOP1__V_CVT_F32_U32
 
class  Inst_VOP1__V_CVT_F32_UBYTE0
 
class  Inst_VOP1__V_CVT_F32_UBYTE1
 
class  Inst_VOP1__V_CVT_F32_UBYTE2
 
class  Inst_VOP1__V_CVT_F32_UBYTE3
 
class  Inst_VOP1__V_CVT_F64_F32
 
class  Inst_VOP1__V_CVT_F64_I32
 
class  Inst_VOP1__V_CVT_F64_U32
 
class  Inst_VOP1__V_CVT_FLR_I32_F32
 
class  Inst_VOP1__V_CVT_I16_F16
 
class  Inst_VOP1__V_CVT_I32_F32
 
class  Inst_VOP1__V_CVT_I32_F64
 
class  Inst_VOP1__V_CVT_OFF_F32_I4
 
class  Inst_VOP1__V_CVT_RPI_I32_F32
 
class  Inst_VOP1__V_CVT_U16_F16
 
class  Inst_VOP1__V_CVT_U32_F32
 
class  Inst_VOP1__V_CVT_U32_F64
 
class  Inst_VOP1__V_EXP_F16
 
class  Inst_VOP1__V_EXP_F32
 
class  Inst_VOP1__V_EXP_LEGACY_F32
 
class  Inst_VOP1__V_FFBH_I32
 
class  Inst_VOP1__V_FFBH_U32
 
class  Inst_VOP1__V_FFBL_B32
 
class  Inst_VOP1__V_FLOOR_F16
 
class  Inst_VOP1__V_FLOOR_F32
 
class  Inst_VOP1__V_FLOOR_F64
 
class  Inst_VOP1__V_FRACT_F16
 
class  Inst_VOP1__V_FRACT_F32
 
class  Inst_VOP1__V_FRACT_F64
 
class  Inst_VOP1__V_FREXP_EXP_I16_F16
 
class  Inst_VOP1__V_FREXP_EXP_I32_F32
 
class  Inst_VOP1__V_FREXP_EXP_I32_F64
 
class  Inst_VOP1__V_FREXP_MANT_F16
 
class  Inst_VOP1__V_FREXP_MANT_F32
 
class  Inst_VOP1__V_FREXP_MANT_F64
 
class  Inst_VOP1__V_LOG_F16
 
class  Inst_VOP1__V_LOG_F32
 
class  Inst_VOP1__V_LOG_LEGACY_F32
 
class  Inst_VOP1__V_MOV_B32
 
class  Inst_VOP1__V_MOV_FED_B32
 
class  Inst_VOP1__V_NOP
 
class  Inst_VOP1__V_NOT_B32
 
class  Inst_VOP1__V_RCP_F16
 
class  Inst_VOP1__V_RCP_F32
 
class  Inst_VOP1__V_RCP_F64
 
class  Inst_VOP1__V_RCP_IFLAG_F32
 
class  Inst_VOP1__V_READFIRSTLANE_B32
 
class  Inst_VOP1__V_RNDNE_F16
 
class  Inst_VOP1__V_RNDNE_F32
 
class  Inst_VOP1__V_RNDNE_F64
 
class  Inst_VOP1__V_RSQ_F16
 
class  Inst_VOP1__V_RSQ_F32
 
class  Inst_VOP1__V_RSQ_F64
 
class  Inst_VOP1__V_SIN_F16
 
class  Inst_VOP1__V_SIN_F32
 
class  Inst_VOP1__V_SQRT_F16
 
class  Inst_VOP1__V_SQRT_F32
 
class  Inst_VOP1__V_SQRT_F64
 
class  Inst_VOP1__V_TRUNC_F16
 
class  Inst_VOP1__V_TRUNC_F32
 
class  Inst_VOP1__V_TRUNC_F64
 
class  Inst_VOP2
 
class  Inst_VOP2__V_ADD_F16
 
class  Inst_VOP2__V_ADD_F32
 
class  Inst_VOP2__V_ADD_U16
 
class  Inst_VOP2__V_ADD_U32
 
class  Inst_VOP2__V_ADDC_U32
 
class  Inst_VOP2__V_AND_B32
 
class  Inst_VOP2__V_ASHRREV_I16
 
class  Inst_VOP2__V_ASHRREV_I32
 
class  Inst_VOP2__V_CNDMASK_B32
 
class  Inst_VOP2__V_LDEXP_F16
 
class  Inst_VOP2__V_LSHLREV_B16
 
class  Inst_VOP2__V_LSHLREV_B32
 
class  Inst_VOP2__V_LSHRREV_B16
 
class  Inst_VOP2__V_LSHRREV_B32
 
class  Inst_VOP2__V_MAC_F16
 
class  Inst_VOP2__V_MAC_F32
 
class  Inst_VOP2__V_MADAK_F16
 
class  Inst_VOP2__V_MADAK_F32
 
class  Inst_VOP2__V_MADMK_F16
 
class  Inst_VOP2__V_MADMK_F32
 
class  Inst_VOP2__V_MAX_F16
 
class  Inst_VOP2__V_MAX_F32
 
class  Inst_VOP2__V_MAX_I16
 
class  Inst_VOP2__V_MAX_I32
 
class  Inst_VOP2__V_MAX_U16
 
class  Inst_VOP2__V_MAX_U32
 
class  Inst_VOP2__V_MIN_F16
 
class  Inst_VOP2__V_MIN_F32
 
class  Inst_VOP2__V_MIN_I16
 
class  Inst_VOP2__V_MIN_I32
 
class  Inst_VOP2__V_MIN_U16
 
class  Inst_VOP2__V_MIN_U32
 
class  Inst_VOP2__V_MUL_F16
 
class  Inst_VOP2__V_MUL_F32
 
class  Inst_VOP2__V_MUL_HI_I32_I24
 
class  Inst_VOP2__V_MUL_HI_U32_U24
 
class  Inst_VOP2__V_MUL_I32_I24
 
class  Inst_VOP2__V_MUL_LEGACY_F32
 
class  Inst_VOP2__V_MUL_LO_U16
 
class  Inst_VOP2__V_MUL_U32_U24
 
class  Inst_VOP2__V_OR_B32
 
class  Inst_VOP2__V_SUB_F16
 
class  Inst_VOP2__V_SUB_F32
 
class  Inst_VOP2__V_SUB_U16
 
class  Inst_VOP2__V_SUB_U32
 
class  Inst_VOP2__V_SUBB_U32
 
class  Inst_VOP2__V_SUBBREV_U32
 
class  Inst_VOP2__V_SUBREV_F16
 
class  Inst_VOP2__V_SUBREV_F32
 
class  Inst_VOP2__V_SUBREV_U16
 
class  Inst_VOP2__V_SUBREV_U32
 
class  Inst_VOP2__V_XOR_B32
 
class  Inst_VOP3
 
class  Inst_VOP3__V_ADD_F16
 
class  Inst_VOP3__V_ADD_F32
 
class  Inst_VOP3__V_ADD_F64
 
class  Inst_VOP3__V_ADD_U16
 
class  Inst_VOP3__V_ADD_U32
 
class  Inst_VOP3__V_ADDC_U32
 
class  Inst_VOP3__V_ALIGNBIT_B32
 
class  Inst_VOP3__V_ALIGNBYTE_B32
 
class  Inst_VOP3__V_AND_B32
 
class  Inst_VOP3__V_ASHRREV_I16
 
class  Inst_VOP3__V_ASHRREV_I32
 
class  Inst_VOP3__V_ASHRREV_I64
 
class  Inst_VOP3__V_BCNT_U32_B32
 
class  Inst_VOP3__V_BFE_I32
 
class  Inst_VOP3__V_BFE_U32
 
class  Inst_VOP3__V_BFI_B32
 
class  Inst_VOP3__V_BFM_B32
 
class  Inst_VOP3__V_BFREV_B32
 
class  Inst_VOP3__V_CEIL_F16
 
class  Inst_VOP3__V_CEIL_F32
 
class  Inst_VOP3__V_CEIL_F64
 
class  Inst_VOP3__V_CLREXCP
 
class  Inst_VOP3__V_CMP_CLASS_F16
 
class  Inst_VOP3__V_CMP_CLASS_F32
 
class  Inst_VOP3__V_CMP_CLASS_F64
 
class  Inst_VOP3__V_CMP_EQ_F16
 
class  Inst_VOP3__V_CMP_EQ_F32
 
class  Inst_VOP3__V_CMP_EQ_F64
 
class  Inst_VOP3__V_CMP_EQ_I16
 
class  Inst_VOP3__V_CMP_EQ_I32
 
class  Inst_VOP3__V_CMP_EQ_I64
 
class  Inst_VOP3__V_CMP_EQ_U16
 
class  Inst_VOP3__V_CMP_EQ_U32
 
class  Inst_VOP3__V_CMP_EQ_U64
 
class  Inst_VOP3__V_CMP_F_F16
 
class  Inst_VOP3__V_CMP_F_F32
 
class  Inst_VOP3__V_CMP_F_F64
 
class  Inst_VOP3__V_CMP_F_I16
 
class  Inst_VOP3__V_CMP_F_I32
 
class  Inst_VOP3__V_CMP_F_I64
 
class  Inst_VOP3__V_CMP_F_U16
 
class  Inst_VOP3__V_CMP_F_U32
 
class  Inst_VOP3__V_CMP_F_U64
 
class  Inst_VOP3__V_CMP_GE_F16
 
class  Inst_VOP3__V_CMP_GE_F32
 
class  Inst_VOP3__V_CMP_GE_F64
 
class  Inst_VOP3__V_CMP_GE_I16
 
class  Inst_VOP3__V_CMP_GE_I32
 
class  Inst_VOP3__V_CMP_GE_I64
 
class  Inst_VOP3__V_CMP_GE_U16
 
class  Inst_VOP3__V_CMP_GE_U32
 
class  Inst_VOP3__V_CMP_GE_U64
 
class  Inst_VOP3__V_CMP_GT_F16
 
class  Inst_VOP3__V_CMP_GT_F32
 
class  Inst_VOP3__V_CMP_GT_F64
 
class  Inst_VOP3__V_CMP_GT_I16
 
class  Inst_VOP3__V_CMP_GT_I32
 
class  Inst_VOP3__V_CMP_GT_I64
 
class  Inst_VOP3__V_CMP_GT_U16
 
class  Inst_VOP3__V_CMP_GT_U32
 
class  Inst_VOP3__V_CMP_GT_U64
 
class  Inst_VOP3__V_CMP_LE_F16
 
class  Inst_VOP3__V_CMP_LE_F32
 
class  Inst_VOP3__V_CMP_LE_F64
 
class  Inst_VOP3__V_CMP_LE_I16
 
class  Inst_VOP3__V_CMP_LE_I32
 
class  Inst_VOP3__V_CMP_LE_I64
 
class  Inst_VOP3__V_CMP_LE_U16
 
class  Inst_VOP3__V_CMP_LE_U32
 
class  Inst_VOP3__V_CMP_LE_U64
 
class  Inst_VOP3__V_CMP_LG_F16
 
class  Inst_VOP3__V_CMP_LG_F32
 
class  Inst_VOP3__V_CMP_LG_F64
 
class  Inst_VOP3__V_CMP_LT_F16
 
class  Inst_VOP3__V_CMP_LT_F32
 
class  Inst_VOP3__V_CMP_LT_F64
 
class  Inst_VOP3__V_CMP_LT_I16
 
class  Inst_VOP3__V_CMP_LT_I32
 
class  Inst_VOP3__V_CMP_LT_I64
 
class  Inst_VOP3__V_CMP_LT_U16
 
class  Inst_VOP3__V_CMP_LT_U32
 
class  Inst_VOP3__V_CMP_LT_U64
 
class  Inst_VOP3__V_CMP_NE_I16
 
class  Inst_VOP3__V_CMP_NE_I32
 
class  Inst_VOP3__V_CMP_NE_I64
 
class  Inst_VOP3__V_CMP_NE_U16
 
class  Inst_VOP3__V_CMP_NE_U32
 
class  Inst_VOP3__V_CMP_NE_U64
 
class  Inst_VOP3__V_CMP_NEQ_F16
 
class  Inst_VOP3__V_CMP_NEQ_F32
 
class  Inst_VOP3__V_CMP_NEQ_F64
 
class  Inst_VOP3__V_CMP_NGE_F16
 
class  Inst_VOP3__V_CMP_NGE_F32
 
class  Inst_VOP3__V_CMP_NGE_F64
 
class  Inst_VOP3__V_CMP_NGT_F16
 
class  Inst_VOP3__V_CMP_NGT_F32
 
class  Inst_VOP3__V_CMP_NGT_F64
 
class  Inst_VOP3__V_CMP_NLE_F16
 
class  Inst_VOP3__V_CMP_NLE_F32
 
class  Inst_VOP3__V_CMP_NLE_F64
 
class  Inst_VOP3__V_CMP_NLG_F16
 
class  Inst_VOP3__V_CMP_NLG_F32
 
class  Inst_VOP3__V_CMP_NLG_F64
 
class  Inst_VOP3__V_CMP_NLT_F16
 
class  Inst_VOP3__V_CMP_NLT_F32
 
class  Inst_VOP3__V_CMP_NLT_F64
 
class  Inst_VOP3__V_CMP_O_F16
 
class  Inst_VOP3__V_CMP_O_F32
 
class  Inst_VOP3__V_CMP_O_F64
 
class  Inst_VOP3__V_CMP_T_I16
 
class  Inst_VOP3__V_CMP_T_I32
 
class  Inst_VOP3__V_CMP_T_I64
 
class  Inst_VOP3__V_CMP_T_U16
 
class  Inst_VOP3__V_CMP_T_U32
 
class  Inst_VOP3__V_CMP_T_U64
 
class  Inst_VOP3__V_CMP_TRU_F16
 
class  Inst_VOP3__V_CMP_TRU_F32
 
class  Inst_VOP3__V_CMP_TRU_F64
 
class  Inst_VOP3__V_CMP_U_F16
 
class  Inst_VOP3__V_CMP_U_F32
 
class  Inst_VOP3__V_CMP_U_F64
 
class  Inst_VOP3__V_CMPX_CLASS_F16
 
class  Inst_VOP3__V_CMPX_CLASS_F32
 
class  Inst_VOP3__V_CMPX_CLASS_F64
 
class  Inst_VOP3__V_CMPX_EQ_F16
 
class  Inst_VOP3__V_CMPX_EQ_F32
 
class  Inst_VOP3__V_CMPX_EQ_F64
 
class  Inst_VOP3__V_CMPX_EQ_I16
 
class  Inst_VOP3__V_CMPX_EQ_I32
 
class  Inst_VOP3__V_CMPX_EQ_I64
 
class  Inst_VOP3__V_CMPX_EQ_U16
 
class  Inst_VOP3__V_CMPX_EQ_U32
 
class  Inst_VOP3__V_CMPX_EQ_U64
 
class  Inst_VOP3__V_CMPX_F_F16
 
class  Inst_VOP3__V_CMPX_F_F32
 
class  Inst_VOP3__V_CMPX_F_F64
 
class  Inst_VOP3__V_CMPX_F_I16
 
class  Inst_VOP3__V_CMPX_F_I32
 
class  Inst_VOP3__V_CMPX_F_I64
 
class  Inst_VOP3__V_CMPX_F_U16
 
class  Inst_VOP3__V_CMPX_F_U32
 
class  Inst_VOP3__V_CMPX_F_U64
 
class  Inst_VOP3__V_CMPX_GE_F16
 
class  Inst_VOP3__V_CMPX_GE_F32
 
class  Inst_VOP3__V_CMPX_GE_F64
 
class  Inst_VOP3__V_CMPX_GE_I16
 
class  Inst_VOP3__V_CMPX_GE_I32
 
class  Inst_VOP3__V_CMPX_GE_I64
 
class  Inst_VOP3__V_CMPX_GE_U16
 
class  Inst_VOP3__V_CMPX_GE_U32
 
class  Inst_VOP3__V_CMPX_GE_U64
 
class  Inst_VOP3__V_CMPX_GT_F16
 
class  Inst_VOP3__V_CMPX_GT_F32
 
class  Inst_VOP3__V_CMPX_GT_F64
 
class  Inst_VOP3__V_CMPX_GT_I16
 
class  Inst_VOP3__V_CMPX_GT_I32
 
class  Inst_VOP3__V_CMPX_GT_I64
 
class  Inst_VOP3__V_CMPX_GT_U16
 
class  Inst_VOP3__V_CMPX_GT_U32
 
class  Inst_VOP3__V_CMPX_GT_U64
 
class  Inst_VOP3__V_CMPX_LE_F16
 
class  Inst_VOP3__V_CMPX_LE_F32
 
class  Inst_VOP3__V_CMPX_LE_F64
 
class  Inst_VOP3__V_CMPX_LE_I16
 
class  Inst_VOP3__V_CMPX_LE_I32
 
class  Inst_VOP3__V_CMPX_LE_I64
 
class  Inst_VOP3__V_CMPX_LE_U16
 
class  Inst_VOP3__V_CMPX_LE_U32
 
class  Inst_VOP3__V_CMPX_LE_U64
 
class  Inst_VOP3__V_CMPX_LG_F16
 
class  Inst_VOP3__V_CMPX_LG_F32
 
class  Inst_VOP3__V_CMPX_LG_F64
 
class  Inst_VOP3__V_CMPX_LT_F16
 
class  Inst_VOP3__V_CMPX_LT_F32
 
class  Inst_VOP3__V_CMPX_LT_F64
 
class  Inst_VOP3__V_CMPX_LT_I16
 
class  Inst_VOP3__V_CMPX_LT_I32
 
class  Inst_VOP3__V_CMPX_LT_I64
 
class  Inst_VOP3__V_CMPX_LT_U16
 
class  Inst_VOP3__V_CMPX_LT_U32
 
class  Inst_VOP3__V_CMPX_LT_U64
 
class  Inst_VOP3__V_CMPX_NE_I16
 
class  Inst_VOP3__V_CMPX_NE_I32
 
class  Inst_VOP3__V_CMPX_NE_I64
 
class  Inst_VOP3__V_CMPX_NE_U16
 
class  Inst_VOP3__V_CMPX_NE_U32
 
class  Inst_VOP3__V_CMPX_NE_U64
 
class  Inst_VOP3__V_CMPX_NEQ_F16
 
class  Inst_VOP3__V_CMPX_NEQ_F32
 
class  Inst_VOP3__V_CMPX_NEQ_F64
 
class  Inst_VOP3__V_CMPX_NGE_F16
 
class  Inst_VOP3__V_CMPX_NGE_F32
 
class  Inst_VOP3__V_CMPX_NGE_F64
 
class  Inst_VOP3__V_CMPX_NGT_F16
 
class  Inst_VOP3__V_CMPX_NGT_F32
 
class  Inst_VOP3__V_CMPX_NGT_F64
 
class  Inst_VOP3__V_CMPX_NLE_F16
 
class  Inst_VOP3__V_CMPX_NLE_F32
 
class  Inst_VOP3__V_CMPX_NLE_F64
 
class  Inst_VOP3__V_CMPX_NLG_F16
 
class  Inst_VOP3__V_CMPX_NLG_F32
 
class  Inst_VOP3__V_CMPX_NLG_F64
 
class  Inst_VOP3__V_CMPX_NLT_F16
 
class  Inst_VOP3__V_CMPX_NLT_F32
 
class  Inst_VOP3__V_CMPX_NLT_F64
 
class  Inst_VOP3__V_CMPX_O_F16
 
class  Inst_VOP3__V_CMPX_O_F32
 
class  Inst_VOP3__V_CMPX_O_F64
 
class  Inst_VOP3__V_CMPX_T_I16
 
class  Inst_VOP3__V_CMPX_T_I32
 
class  Inst_VOP3__V_CMPX_T_I64
 
class  Inst_VOP3__V_CMPX_T_U16
 
class  Inst_VOP3__V_CMPX_T_U32
 
class  Inst_VOP3__V_CMPX_T_U64
 
class  Inst_VOP3__V_CMPX_TRU_F16
 
class  Inst_VOP3__V_CMPX_TRU_F32
 
class  Inst_VOP3__V_CMPX_TRU_F64
 
class  Inst_VOP3__V_CMPX_U_F16
 
class  Inst_VOP3__V_CMPX_U_F32
 
class  Inst_VOP3__V_CMPX_U_F64
 
class  Inst_VOP3__V_CNDMASK_B32
 
class  Inst_VOP3__V_COS_F16
 
class  Inst_VOP3__V_COS_F32
 
class  Inst_VOP3__V_CUBEID_F32
 
class  Inst_VOP3__V_CUBEMA_F32
 
class  Inst_VOP3__V_CUBESC_F32
 
class  Inst_VOP3__V_CUBETC_F32
 
class  Inst_VOP3__V_CVT_F16_F32
 
class  Inst_VOP3__V_CVT_F16_I16
 
class  Inst_VOP3__V_CVT_F16_U16
 
class  Inst_VOP3__V_CVT_F32_F16
 
class  Inst_VOP3__V_CVT_F32_F64
 
class  Inst_VOP3__V_CVT_F32_I32
 
class  Inst_VOP3__V_CVT_F32_U32
 
class  Inst_VOP3__V_CVT_F32_UBYTE0
 
class  Inst_VOP3__V_CVT_F32_UBYTE1
 
class  Inst_VOP3__V_CVT_F32_UBYTE2
 
class  Inst_VOP3__V_CVT_F32_UBYTE3
 
class  Inst_VOP3__V_CVT_F64_F32
 
class  Inst_VOP3__V_CVT_F64_I32
 
class  Inst_VOP3__V_CVT_F64_U32
 
class  Inst_VOP3__V_CVT_FLR_I32_F32
 
class  Inst_VOP3__V_CVT_I16_F16
 
class  Inst_VOP3__V_CVT_I32_F32
 
class  Inst_VOP3__V_CVT_I32_F64
 
class  Inst_VOP3__V_CVT_OFF_F32_I4
 
class  Inst_VOP3__V_CVT_PK_I16_I32
 
class  Inst_VOP3__V_CVT_PK_U16_U32
 
class  Inst_VOP3__V_CVT_PK_U8_F32
 
class  Inst_VOP3__V_CVT_PKACCUM_U8_F32
 
class  Inst_VOP3__V_CVT_PKNORM_I16_F32
 
class  Inst_VOP3__V_CVT_PKNORM_U16_F32
 
class  Inst_VOP3__V_CVT_PKRTZ_F16_F32
 
class  Inst_VOP3__V_CVT_RPI_I32_F32
 
class  Inst_VOP3__V_CVT_U16_F16
 
class  Inst_VOP3__V_CVT_U32_F32
 
class  Inst_VOP3__V_CVT_U32_F64
 
class  Inst_VOP3__V_DIV_FIXUP_F16
 
class  Inst_VOP3__V_DIV_FIXUP_F32
 
class  Inst_VOP3__V_DIV_FIXUP_F64
 
class  Inst_VOP3__V_DIV_FMAS_F32
 
class  Inst_VOP3__V_DIV_FMAS_F64
 
class  Inst_VOP3__V_DIV_SCALE_F32
 
class  Inst_VOP3__V_DIV_SCALE_F64
 
class  Inst_VOP3__V_EXP_F16
 
class  Inst_VOP3__V_EXP_F32
 
class  Inst_VOP3__V_EXP_LEGACY_F32
 
class  Inst_VOP3__V_FFBH_I32
 
class  Inst_VOP3__V_FFBH_U32
 
class  Inst_VOP3__V_FFBL_B32
 
class  Inst_VOP3__V_FLOOR_F16
 
class  Inst_VOP3__V_FLOOR_F32
 
class  Inst_VOP3__V_FLOOR_F64
 
class  Inst_VOP3__V_FMA_F16
 
class  Inst_VOP3__V_FMA_F32
 
class  Inst_VOP3__V_FMA_F64
 
class  Inst_VOP3__V_FRACT_F16
 
class  Inst_VOP3__V_FRACT_F32
 
class  Inst_VOP3__V_FRACT_F64
 
class  Inst_VOP3__V_FREXP_EXP_I16_F16
 
class  Inst_VOP3__V_FREXP_EXP_I32_F32
 
class  Inst_VOP3__V_FREXP_EXP_I32_F64
 
class  Inst_VOP3__V_FREXP_MANT_F16
 
class  Inst_VOP3__V_FREXP_MANT_F32
 
class  Inst_VOP3__V_FREXP_MANT_F64
 
class  Inst_VOP3__V_INTERP_MOV_F32
 
class  Inst_VOP3__V_INTERP_P1_F32
 
class  Inst_VOP3__V_INTERP_P1LL_F16
 
class  Inst_VOP3__V_INTERP_P1LV_F16
 
class  Inst_VOP3__V_INTERP_P2_F16
 
class  Inst_VOP3__V_INTERP_P2_F32
 
class  Inst_VOP3__V_LDEXP_F16
 
class  Inst_VOP3__V_LDEXP_F32
 
class  Inst_VOP3__V_LDEXP_F64
 
class  Inst_VOP3__V_LERP_U8
 
class  Inst_VOP3__V_LOG_F16
 
class  Inst_VOP3__V_LOG_F32
 
class  Inst_VOP3__V_LOG_LEGACY_F32
 
class  Inst_VOP3__V_LSHLREV_B16
 
class  Inst_VOP3__V_LSHLREV_B32
 
class  Inst_VOP3__V_LSHLREV_B64
 
class  Inst_VOP3__V_LSHRREV_B16
 
class  Inst_VOP3__V_LSHRREV_B32
 
class  Inst_VOP3__V_LSHRREV_B64
 
class  Inst_VOP3__V_MAC_F16
 
class  Inst_VOP3__V_MAC_F32
 
class  Inst_VOP3__V_MAD_F16
 
class  Inst_VOP3__V_MAD_F32
 
class  Inst_VOP3__V_MAD_I16
 
class  Inst_VOP3__V_MAD_I32_I24
 
class  Inst_VOP3__V_MAD_I64_I32
 
class  Inst_VOP3__V_MAD_LEGACY_F32
 
class  Inst_VOP3__V_MAD_U16
 
class  Inst_VOP3__V_MAD_U32_U24
 
class  Inst_VOP3__V_MAD_U64_U32
 
class  Inst_VOP3__V_MAX3_F32
 
class  Inst_VOP3__V_MAX3_I32
 
class  Inst_VOP3__V_MAX3_U32
 
class  Inst_VOP3__V_MAX_F16
 
class  Inst_VOP3__V_MAX_F32
 
class  Inst_VOP3__V_MAX_F64
 
class  Inst_VOP3__V_MAX_I16
 
class  Inst_VOP3__V_MAX_I32
 
class  Inst_VOP3__V_MAX_U16
 
class  Inst_VOP3__V_MAX_U32
 
class  Inst_VOP3__V_MBCNT_HI_U32_B32
 
class  Inst_VOP3__V_MBCNT_LO_U32_B32
 
class  Inst_VOP3__V_MED3_F32
 
class  Inst_VOP3__V_MED3_I32
 
class  Inst_VOP3__V_MED3_U32
 
class  Inst_VOP3__V_MIN3_F32
 
class  Inst_VOP3__V_MIN3_I32
 
class  Inst_VOP3__V_MIN3_U32
 
class  Inst_VOP3__V_MIN_F16
 
class  Inst_VOP3__V_MIN_F32
 
class  Inst_VOP3__V_MIN_F64
 
class  Inst_VOP3__V_MIN_I16
 
class  Inst_VOP3__V_MIN_I32
 
class  Inst_VOP3__V_MIN_U16
 
class  Inst_VOP3__V_MIN_U32
 
class  Inst_VOP3__V_MOV_B32
 
class  Inst_VOP3__V_MOV_FED_B32
 
class  Inst_VOP3__V_MQSAD_PK_U16_U8
 
class  Inst_VOP3__V_MQSAD_U32_U8
 
class  Inst_VOP3__V_MSAD_U8
 
class  Inst_VOP3__V_MUL_F16
 
class  Inst_VOP3__V_MUL_F32
 
class  Inst_VOP3__V_MUL_F64
 
class  Inst_VOP3__V_MUL_HI_I32
 
class  Inst_VOP3__V_MUL_HI_I32_I24
 
class  Inst_VOP3__V_MUL_HI_U32
 
class  Inst_VOP3__V_MUL_HI_U32_U24
 
class  Inst_VOP3__V_MUL_I32_I24
 
class  Inst_VOP3__V_MUL_LEGACY_F32
 
class  Inst_VOP3__V_MUL_LO_U16
 
class  Inst_VOP3__V_MUL_LO_U32
 
class  Inst_VOP3__V_MUL_U32_U24
 
class  Inst_VOP3__V_NOP
 
class  Inst_VOP3__V_NOT_B32
 
class  Inst_VOP3__V_OR_B32
 
class  Inst_VOP3__V_PERM_B32
 
class  Inst_VOP3__V_QSAD_PK_U16_U8
 
class  Inst_VOP3__V_RCP_F16
 
class  Inst_VOP3__V_RCP_F32
 
class  Inst_VOP3__V_RCP_F64
 
class  Inst_VOP3__V_RCP_IFLAG_F32
 
class  Inst_VOP3__V_READLANE_B32
 
class  Inst_VOP3__V_RNDNE_F16
 
class  Inst_VOP3__V_RNDNE_F32
 
class  Inst_VOP3__V_RNDNE_F64
 
class  Inst_VOP3__V_RSQ_F16
 
class  Inst_VOP3__V_RSQ_F32
 
class  Inst_VOP3__V_RSQ_F64
 
class  Inst_VOP3__V_SAD_HI_U8
 
class  Inst_VOP3__V_SAD_U16
 
class  Inst_VOP3__V_SAD_U32
 
class  Inst_VOP3__V_SAD_U8
 
class  Inst_VOP3__V_SIN_F16
 
class  Inst_VOP3__V_SIN_F32
 
class  Inst_VOP3__V_SQRT_F16
 
class  Inst_VOP3__V_SQRT_F32
 
class  Inst_VOP3__V_SQRT_F64
 
class  Inst_VOP3__V_SUB_F16
 
class  Inst_VOP3__V_SUB_F32
 
class  Inst_VOP3__V_SUB_U16
 
class  Inst_VOP3__V_SUB_U32
 
class  Inst_VOP3__V_SUBB_U32
 
class  Inst_VOP3__V_SUBBREV_U32
 
class  Inst_VOP3__V_SUBREV_F16
 
class  Inst_VOP3__V_SUBREV_F32
 
class  Inst_VOP3__V_SUBREV_U16
 
class  Inst_VOP3__V_SUBREV_U32
 
class  Inst_VOP3__V_TRIG_PREOP_F64
 
class  Inst_VOP3__V_TRUNC_F16
 
class  Inst_VOP3__V_TRUNC_F32
 
class  Inst_VOP3__V_TRUNC_F64
 
class  Inst_VOP3__V_WRITELANE_B32
 
class  Inst_VOP3__V_XOR_B32
 
class  Inst_VOP3_SDST_ENC
 
class  Inst_VOPC
 
class  Inst_VOPC__V_CMP_CLASS_F16
 
class  Inst_VOPC__V_CMP_CLASS_F32
 
class  Inst_VOPC__V_CMP_CLASS_F64
 
class  Inst_VOPC__V_CMP_EQ_F16
 
class  Inst_VOPC__V_CMP_EQ_F32
 
class  Inst_VOPC__V_CMP_EQ_F64
 
class  Inst_VOPC__V_CMP_EQ_I16
 
class  Inst_VOPC__V_CMP_EQ_I32
 
class  Inst_VOPC__V_CMP_EQ_I64
 
class  Inst_VOPC__V_CMP_EQ_U16
 
class  Inst_VOPC__V_CMP_EQ_U32
 
class  Inst_VOPC__V_CMP_EQ_U64
 
class  Inst_VOPC__V_CMP_F_F16
 
class  Inst_VOPC__V_CMP_F_F32
 
class  Inst_VOPC__V_CMP_F_F64
 
class  Inst_VOPC__V_CMP_F_I16
 
class  Inst_VOPC__V_CMP_F_I32
 
class  Inst_VOPC__V_CMP_F_I64
 
class  Inst_VOPC__V_CMP_F_U16
 
class  Inst_VOPC__V_CMP_F_U32
 
class  Inst_VOPC__V_CMP_F_U64
 
class  Inst_VOPC__V_CMP_GE_F16
 
class  Inst_VOPC__V_CMP_GE_F32
 
class  Inst_VOPC__V_CMP_GE_F64
 
class  Inst_VOPC__V_CMP_GE_I16
 
class  Inst_VOPC__V_CMP_GE_I32
 
class  Inst_VOPC__V_CMP_GE_I64
 
class  Inst_VOPC__V_CMP_GE_U16
 
class  Inst_VOPC__V_CMP_GE_U32
 
class  Inst_VOPC__V_CMP_GE_U64
 
class  Inst_VOPC__V_CMP_GT_F16
 
class  Inst_VOPC__V_CMP_GT_F32
 
class  Inst_VOPC__V_CMP_GT_F64
 
class  Inst_VOPC__V_CMP_GT_I16
 
class  Inst_VOPC__V_CMP_GT_I32
 
class  Inst_VOPC__V_CMP_GT_I64
 
class  Inst_VOPC__V_CMP_GT_U16
 
class  Inst_VOPC__V_CMP_GT_U32
 
class  Inst_VOPC__V_CMP_GT_U64
 
class  Inst_VOPC__V_CMP_LE_F16
 
class  Inst_VOPC__V_CMP_LE_F32
 
class  Inst_VOPC__V_CMP_LE_F64
 
class  Inst_VOPC__V_CMP_LE_I16
 
class  Inst_VOPC__V_CMP_LE_I32
 
class  Inst_VOPC__V_CMP_LE_I64
 
class  Inst_VOPC__V_CMP_LE_U16
 
class  Inst_VOPC__V_CMP_LE_U32
 
class  Inst_VOPC__V_CMP_LE_U64
 
class  Inst_VOPC__V_CMP_LG_F16
 
class  Inst_VOPC__V_CMP_LG_F32
 
class  Inst_VOPC__V_CMP_LG_F64
 
class  Inst_VOPC__V_CMP_LT_F16
 
class  Inst_VOPC__V_CMP_LT_F32
 
class  Inst_VOPC__V_CMP_LT_F64
 
class  Inst_VOPC__V_CMP_LT_I16
 
class  Inst_VOPC__V_CMP_LT_I32
 
class  Inst_VOPC__V_CMP_LT_I64
 
class  Inst_VOPC__V_CMP_LT_U16
 
class  Inst_VOPC__V_CMP_LT_U32
 
class  Inst_VOPC__V_CMP_LT_U64
 
class  Inst_VOPC__V_CMP_NE_I16
 
class  Inst_VOPC__V_CMP_NE_I32
 
class  Inst_VOPC__V_CMP_NE_I64
 
class  Inst_VOPC__V_CMP_NE_U16
 
class  Inst_VOPC__V_CMP_NE_U32
 
class  Inst_VOPC__V_CMP_NE_U64
 
class  Inst_VOPC__V_CMP_NEQ_F16
 
class  Inst_VOPC__V_CMP_NEQ_F32
 
class  Inst_VOPC__V_CMP_NEQ_F64
 
class  Inst_VOPC__V_CMP_NGE_F16
 
class  Inst_VOPC__V_CMP_NGE_F32
 
class  Inst_VOPC__V_CMP_NGE_F64
 
class  Inst_VOPC__V_CMP_NGT_F16
 
class  Inst_VOPC__V_CMP_NGT_F32
 
class  Inst_VOPC__V_CMP_NGT_F64
 
class  Inst_VOPC__V_CMP_NLE_F16
 
class  Inst_VOPC__V_CMP_NLE_F32
 
class  Inst_VOPC__V_CMP_NLE_F64
 
class  Inst_VOPC__V_CMP_NLG_F16
 
class  Inst_VOPC__V_CMP_NLG_F32
 
class  Inst_VOPC__V_CMP_NLG_F64
 
class  Inst_VOPC__V_CMP_NLT_F16
 
class  Inst_VOPC__V_CMP_NLT_F32
 
class  Inst_VOPC__V_CMP_NLT_F64
 
class  Inst_VOPC__V_CMP_O_F16
 
class  Inst_VOPC__V_CMP_O_F32
 
class  Inst_VOPC__V_CMP_O_F64
 
class  Inst_VOPC__V_CMP_T_I16
 
class  Inst_VOPC__V_CMP_T_I32
 
class  Inst_VOPC__V_CMP_T_I64
 
class  Inst_VOPC__V_CMP_T_U16
 
class  Inst_VOPC__V_CMP_T_U32
 
class  Inst_VOPC__V_CMP_T_U64
 
class  Inst_VOPC__V_CMP_TRU_F16
 
class  Inst_VOPC__V_CMP_TRU_F32
 
class  Inst_VOPC__V_CMP_TRU_F64
 
class  Inst_VOPC__V_CMP_U_F16
 
class  Inst_VOPC__V_CMP_U_F32
 
class  Inst_VOPC__V_CMP_U_F64
 
class  Inst_VOPC__V_CMPX_CLASS_F16
 
class  Inst_VOPC__V_CMPX_CLASS_F32
 
class  Inst_VOPC__V_CMPX_CLASS_F64
 
class  Inst_VOPC__V_CMPX_EQ_F16
 
class  Inst_VOPC__V_CMPX_EQ_F32
 
class  Inst_VOPC__V_CMPX_EQ_F64
 
class  Inst_VOPC__V_CMPX_EQ_I16
 
class  Inst_VOPC__V_CMPX_EQ_I32
 
class  Inst_VOPC__V_CMPX_EQ_I64
 
class  Inst_VOPC__V_CMPX_EQ_U16
 
class  Inst_VOPC__V_CMPX_EQ_U32
 
class  Inst_VOPC__V_CMPX_EQ_U64
 
class  Inst_VOPC__V_CMPX_F_F16
 
class  Inst_VOPC__V_CMPX_F_F32
 
class  Inst_VOPC__V_CMPX_F_F64
 
class  Inst_VOPC__V_CMPX_F_I16
 
class  Inst_VOPC__V_CMPX_F_I32
 
class  Inst_VOPC__V_CMPX_F_I64
 
class  Inst_VOPC__V_CMPX_F_U16
 
class  Inst_VOPC__V_CMPX_F_U32
 
class  Inst_VOPC__V_CMPX_F_U64
 
class  Inst_VOPC__V_CMPX_GE_F16
 
class  Inst_VOPC__V_CMPX_GE_F32
 
class  Inst_VOPC__V_CMPX_GE_F64
 
class  Inst_VOPC__V_CMPX_GE_I16
 
class  Inst_VOPC__V_CMPX_GE_I32
 
class  Inst_VOPC__V_CMPX_GE_I64
 
class  Inst_VOPC__V_CMPX_GE_U16
 
class  Inst_VOPC__V_CMPX_GE_U32
 
class  Inst_VOPC__V_CMPX_GE_U64
 
class  Inst_VOPC__V_CMPX_GT_F16
 
class  Inst_VOPC__V_CMPX_GT_F32
 
class  Inst_VOPC__V_CMPX_GT_F64
 
class  Inst_VOPC__V_CMPX_GT_I16
 
class  Inst_VOPC__V_CMPX_GT_I32
 
class  Inst_VOPC__V_CMPX_GT_I64
 
class  Inst_VOPC__V_CMPX_GT_U16
 
class  Inst_VOPC__V_CMPX_GT_U32
 
class  Inst_VOPC__V_CMPX_GT_U64
 
class  Inst_VOPC__V_CMPX_LE_F16
 
class  Inst_VOPC__V_CMPX_LE_F32
 
class  Inst_VOPC__V_CMPX_LE_F64
 
class  Inst_VOPC__V_CMPX_LE_I16
 
class  Inst_VOPC__V_CMPX_LE_I32
 
class  Inst_VOPC__V_CMPX_LE_I64
 
class  Inst_VOPC__V_CMPX_LE_U16
 
class  Inst_VOPC__V_CMPX_LE_U32
 
class  Inst_VOPC__V_CMPX_LE_U64
 
class  Inst_VOPC__V_CMPX_LG_F16
 
class  Inst_VOPC__V_CMPX_LG_F32
 
class  Inst_VOPC__V_CMPX_LG_F64
 
class  Inst_VOPC__V_CMPX_LT_F16
 
class  Inst_VOPC__V_CMPX_LT_F32
 
class  Inst_VOPC__V_CMPX_LT_F64
 
class  Inst_VOPC__V_CMPX_LT_I16
 
class  Inst_VOPC__V_CMPX_LT_I32
 
class  Inst_VOPC__V_CMPX_LT_I64
 
class  Inst_VOPC__V_CMPX_LT_U16
 
class  Inst_VOPC__V_CMPX_LT_U32
 
class  Inst_VOPC__V_CMPX_LT_U64
 
class  Inst_VOPC__V_CMPX_NE_I16
 
class  Inst_VOPC__V_CMPX_NE_I32
 
class  Inst_VOPC__V_CMPX_NE_I64
 
class  Inst_VOPC__V_CMPX_NE_U16
 
class  Inst_VOPC__V_CMPX_NE_U32
 
class  Inst_VOPC__V_CMPX_NE_U64
 
class  Inst_VOPC__V_CMPX_NEQ_F16
 
class  Inst_VOPC__V_CMPX_NEQ_F32
 
class  Inst_VOPC__V_CMPX_NEQ_F64
 
class  Inst_VOPC__V_CMPX_NGE_F16
 
class  Inst_VOPC__V_CMPX_NGE_F32
 
class  Inst_VOPC__V_CMPX_NGE_F64
 
class  Inst_VOPC__V_CMPX_NGT_F16
 
class  Inst_VOPC__V_CMPX_NGT_F32
 
class  Inst_VOPC__V_CMPX_NGT_F64
 
class  Inst_VOPC__V_CMPX_NLE_F16
 
class  Inst_VOPC__V_CMPX_NLE_F32
 
class  Inst_VOPC__V_CMPX_NLE_F64
 
class  Inst_VOPC__V_CMPX_NLG_F16
 
class  Inst_VOPC__V_CMPX_NLG_F32
 
class  Inst_VOPC__V_CMPX_NLG_F64
 
class  Inst_VOPC__V_CMPX_NLT_F16
 
class  Inst_VOPC__V_CMPX_NLT_F32
 
class  Inst_VOPC__V_CMPX_NLT_F64
 
class  Inst_VOPC__V_CMPX_O_F16
 
class  Inst_VOPC__V_CMPX_O_F32
 
class  Inst_VOPC__V_CMPX_O_F64
 
class  Inst_VOPC__V_CMPX_T_I16
 
class  Inst_VOPC__V_CMPX_T_I32
 
class  Inst_VOPC__V_CMPX_T_I64
 
class  Inst_VOPC__V_CMPX_T_U16
 
class  Inst_VOPC__V_CMPX_T_U32
 
class  Inst_VOPC__V_CMPX_T_U64
 
class  Inst_VOPC__V_CMPX_TRU_F16
 
class  Inst_VOPC__V_CMPX_TRU_F32
 
class  Inst_VOPC__V_CMPX_TRU_F64
 
class  Inst_VOPC__V_CMPX_U_F16
 
class  Inst_VOPC__V_CMPX_U_F32
 
class  Inst_VOPC__V_CMPX_U_F64
 
union  InstFormat
 
class  Operand
 
struct  OpTraits
 convenience traits so we can automatically infer the correct FP type without looking at the number of dwords (i.e., to determine if we need a float or a double when creating FP constants). More...
 
struct  OpTraits< ScalarRegF64 >
 
struct  OpTraits< ScalarRegU64 >
 
class  ScalarOperand
 
struct  StatusReg
 
class  VecOperand
 

Typedefs

using IsaDecodeMethod = GPUStaticInst *(Decoder::*)(MachInst)
 
typedef uint8_t ScalarRegU8
 
typedef int8_t ScalarRegI8
 
typedef uint16_t ScalarRegU16
 
typedef int16_t ScalarRegI16
 
typedef uint32_t ScalarRegU32
 
typedef int32_t ScalarRegI32
 
typedef float ScalarRegF32
 
typedef uint64_t ScalarRegU64
 
typedef int64_t ScalarRegI64
 
typedef double ScalarRegF64
 
typedef uint8_t VecElemU8
 
typedef int8_t VecElemI8
 
typedef uint16_t VecElemU16
 
typedef int16_t VecElemI16
 
typedef uint32_t VecElemU32
 
typedef int32_t VecElemI32
 
typedef float VecElemF32
 
typedef uint64_t VecElemU64
 
typedef int64_t VecElemI64
 
typedef double VecElemF64
 
using VecRegContainerU32 = VecRegContainer< sizeof(VecElemU32) *NumVecElemPerVecReg >
 
typedef uint64_t RawMachInst
 used to represnt a GPU inst in its raw format. More...
 
typedef InstFormatMachInst
 used to represent the encoding of a GCN3 inst. More...
 
using ScalarOperandU8 = ScalarOperand< ScalarRegU8, false, 1 >
 
using ScalarOperandI8 = ScalarOperand< ScalarRegI8, false, 1 >
 
using ScalarOperandU16 = ScalarOperand< ScalarRegU16, false, 1 >
 
using ScalarOperandI16 = ScalarOperand< ScalarRegI16, false, 1 >
 
using ScalarOperandU32 = ScalarOperand< ScalarRegU32, false >
 
using ScalarOperandI32 = ScalarOperand< ScalarRegI32, false >
 
using ScalarOperandF32 = ScalarOperand< ScalarRegF32, false >
 
using ScalarOperandU64 = ScalarOperand< ScalarRegU64, false >
 
using ScalarOperandI64 = ScalarOperand< ScalarRegI64, false >
 
using ScalarOperandF64 = ScalarOperand< ScalarRegF64, false >
 
using ScalarOperandU128 = ScalarOperand< ScalarRegU32, false, 4 >
 
using ScalarOperandU256 = ScalarOperand< ScalarRegU32, false, 8 >
 
using ScalarOperandU512 = ScalarOperand< ScalarRegU32, false, 16 >
 
using ConstScalarOperandU8 = ScalarOperand< ScalarRegU8, true, 1 >
 
using ConstScalarOperandI8 = ScalarOperand< ScalarRegI8, true, 1 >
 
using ConstScalarOperandU16 = ScalarOperand< ScalarRegU16, true, 1 >
 
using ConstScalarOperandI16 = ScalarOperand< ScalarRegI16, true, 1 >
 
using ConstScalarOperandU32 = ScalarOperand< ScalarRegU32, true >
 
using ConstScalarOperandI32 = ScalarOperand< ScalarRegI32, true >
 
using ConstScalarOperandF32 = ScalarOperand< ScalarRegF32, true >
 
using ConstScalarOperandU64 = ScalarOperand< ScalarRegU64, true >
 
using ConstScalarOperandI64 = ScalarOperand< ScalarRegI64, true >
 
using ConstScalarOperandF64 = ScalarOperand< ScalarRegF64, true >
 
using ConstScalarOperandU128 = ScalarOperand< ScalarRegU32, true, 4 >
 
using ConstScalarOperandU256 = ScalarOperand< ScalarRegU32, true, 8 >
 
using ConstScalarOperandU512 = ScalarOperand< ScalarRegU32, true, 16 >
 
using VecOperandU8 = VecOperand< VecElemU8, false, 1 >
 
using VecOperandI8 = VecOperand< VecElemI8, false, 1 >
 
using VecOperandU16 = VecOperand< VecElemU16, false, 1 >
 
using VecOperandI16 = VecOperand< VecElemI16, false, 1 >
 
using VecOperandU32 = VecOperand< VecElemU32, false >
 
using VecOperandI32 = VecOperand< VecElemI32, false >
 
using VecOperandF32 = VecOperand< VecElemF32, false >
 
using VecOperandU64 = VecOperand< VecElemU64, false >
 
using VecOperandF64 = VecOperand< VecElemF64, false >
 
using VecOperandI64 = VecOperand< VecElemI64, false >
 
using VecOperandU96 = VecOperand< VecElemU32, false, 3 >
 
using VecOperandU128 = VecOperand< VecElemU32, false, 4 >
 
using VecOperandU256 = VecOperand< VecElemU32, false, 8 >
 
using VecOperandU512 = VecOperand< VecElemU32, false, 16 >
 
using ConstVecOperandU8 = VecOperand< VecElemU8, true, 1 >
 
using ConstVecOperandI8 = VecOperand< VecElemI8, true, 1 >
 
using ConstVecOperandU16 = VecOperand< VecElemU16, true, 1 >
 
using ConstVecOperandI16 = VecOperand< VecElemI16, true, 1 >
 
using ConstVecOperandU32 = VecOperand< VecElemU32, true >
 
using ConstVecOperandI32 = VecOperand< VecElemI32, true >
 
using ConstVecOperandF32 = VecOperand< VecElemF32, true >
 
using ConstVecOperandU64 = VecOperand< VecElemU64, true >
 
using ConstVecOperandI64 = VecOperand< VecElemI64, true >
 
using ConstVecOperandF64 = VecOperand< VecElemF64, true >
 
using ConstVecOperandU96 = VecOperand< VecElemU32, true, 3 >
 
using ConstVecOperandU128 = VecOperand< VecElemU32, true, 4 >
 
using ConstVecOperandU256 = VecOperand< VecElemU32, true, 8 >
 
using ConstVecOperandU512 = VecOperand< VecElemU32, true, 16 >
 

Enumerations

enum  OpSelector : int {
  REG_SGPR_MIN = 0, REG_SGPR_MAX = 101, REG_FLAT_SCRATCH_LO = 102, REG_FLAT_SCRATCH_HI = 103,
  REG_XNACK_MASK_LO = 104, REG_XNACK_MASK_HI = 105, REG_VCC_LO = 106, REG_VCC_HI = 107,
  REG_TBA_LO = 108, REG_TBA_HI = 109, REG_TMA_LO = 110, REG_TMA_HI = 111,
  REG_TTMP_0 = 112, REG_TTMP_1 = 113, REG_TTMP_2 = 114, REG_TTMP_3 = 115,
  REG_TTMP_4 = 116, REG_TTMP_5 = 117, REG_TTMP_6 = 118, REG_TTMP_7 = 119,
  REG_TTMP_8 = 120, REG_TTMP_9 = 121, REG_TTMP_10 = 122, REG_TTMP_11 = 123,
  REG_M0 = 124, REG_RESERVED_1 = 125, REG_EXEC_LO = 126, REG_EXEC_HI = 127,
  REG_ZERO = 128, REG_INT_CONST_POS_MIN = 129, REG_INT_CONST_POS_MAX = 192, REG_INT_CONST_NEG_MIN = 193,
  REG_INT_CONST_NEG_MAX = 208, REG_RESERVED_2 = 209, REG_RESERVED_3 = 210, REG_RESERVED_4 = 211,
  REG_RESERVED_5 = 212, REG_RESERVED_6 = 213, REG_RESERVED_7 = 214, REG_RESERVED_8 = 215,
  REG_RESERVED_9 = 216, REG_RESERVED_10 = 217, REG_RESERVED_11 = 218, REG_RESERVED_12 = 219,
  REG_RESERVED_13 = 220, REG_RESERVED_14 = 221, REG_RESERVED_15 = 222, REG_RESERVED_16 = 223,
  REG_RESERVED_17 = 224, REG_RESERVED_18 = 225, REG_RESERVED_19 = 226, REG_RESERVED_20 = 227,
  REG_RESERVED_21 = 228, REG_RESERVED_22 = 229, REG_RESERVED_23 = 230, REG_RESERVED_24 = 231,
  REG_RESERVED_25 = 232, REG_RESERVED_26 = 233, REG_RESERVED_27 = 234, REG_RESERVED_28 = 235,
  REG_RESERVED_29 = 236, REG_RESERVED_30 = 237, REG_RESERVED_31 = 238, REG_RESERVED_32 = 239,
  REG_POS_HALF = 240, REG_NEG_HALF = 241, REG_POS_ONE = 242, REG_NEG_ONE = 243,
  REG_POS_TWO = 244, REG_NEG_TWO = 245, REG_POS_FOUR = 246, REG_NEG_FOUR = 247,
  REG_PI = 248, REG_SRC_SWDA = 249, REG_SRC_DPP = 250, REG_VCCZ = 251,
  REG_EXECZ = 252, REG_SCC = 253, REG_LDS_DIRECT = 254, REG_SRC_LITERAL = 255,
  REG_VGPR_MIN = 256, REG_VGPR_MAX = 511, REG_SGPR_MIN = 0, REG_SGPR_MAX = 101,
  REG_FLAT_SCRATCH_LO = 102, REG_FLAT_SCRATCH_HI = 103, REG_XNACK_MASK_LO = 104, REG_XNACK_MASK_HI = 105,
  REG_VCC_LO = 106, REG_VCC_HI = 107, REG_TBA_LO = 108, REG_TBA_HI = 109,
  REG_TMA_LO = 110, REG_TMA_HI = 111, REG_TTMP_0 = 112, REG_TTMP_1 = 113,
  REG_TTMP_2 = 114, REG_TTMP_3 = 115, REG_TTMP_4 = 116, REG_TTMP_5 = 117,
  REG_TTMP_6 = 118, REG_TTMP_7 = 119, REG_TTMP_8 = 120, REG_TTMP_9 = 121,
  REG_TTMP_10 = 122, REG_TTMP_11 = 123, REG_M0 = 124, REG_RESERVED_1 = 125,
  REG_EXEC_LO = 126, REG_EXEC_HI = 127, REG_ZERO = 128, REG_INT_CONST_POS_MIN = 129,
  REG_INT_CONST_POS_MAX = 192, REG_INT_CONST_NEG_MIN = 193, REG_INT_CONST_NEG_MAX = 208, REG_RESERVED_2 = 209,
  REG_RESERVED_3 = 210, REG_RESERVED_4 = 211, REG_RESERVED_5 = 212, REG_RESERVED_6 = 213,
  REG_RESERVED_7 = 214, REG_RESERVED_8 = 215, REG_RESERVED_9 = 216, REG_RESERVED_10 = 217,
  REG_RESERVED_11 = 218, REG_RESERVED_12 = 219, REG_RESERVED_13 = 220, REG_RESERVED_14 = 221,
  REG_RESERVED_15 = 222, REG_RESERVED_16 = 223, REG_RESERVED_17 = 224, REG_RESERVED_18 = 225,
  REG_RESERVED_19 = 226, REG_RESERVED_20 = 227, REG_RESERVED_21 = 228, REG_RESERVED_22 = 229,
  REG_RESERVED_23 = 230, REG_RESERVED_24 = 231, REG_RESERVED_25 = 232, REG_RESERVED_26 = 233,
  REG_RESERVED_27 = 234, REG_RESERVED_28 = 235, REG_RESERVED_29 = 236, REG_RESERVED_30 = 237,
  REG_RESERVED_31 = 238, REG_RESERVED_32 = 239, REG_POS_HALF = 240, REG_NEG_HALF = 241,
  REG_POS_ONE = 242, REG_NEG_ONE = 243, REG_POS_TWO = 244, REG_NEG_TWO = 245,
  REG_POS_FOUR = 246, REG_NEG_FOUR = 247, REG_PI = 248, REG_SRC_SWDA = 249,
  REG_SRC_DPP = 250, REG_VCCZ = 251, REG_EXECZ = 252, REG_SCC = 253,
  REG_LDS_DIRECT = 254, REG_SRC_LITERAL = 255, REG_VGPR_MIN = 256, REG_VGPR_MAX = 511
}
 
enum  OpSelector : int {
  REG_SGPR_MIN = 0, REG_SGPR_MAX = 101, REG_FLAT_SCRATCH_LO = 102, REG_FLAT_SCRATCH_HI = 103,
  REG_XNACK_MASK_LO = 104, REG_XNACK_MASK_HI = 105, REG_VCC_LO = 106, REG_VCC_HI = 107,
  REG_TBA_LO = 108, REG_TBA_HI = 109, REG_TMA_LO = 110, REG_TMA_HI = 111,
  REG_TTMP_0 = 112, REG_TTMP_1 = 113, REG_TTMP_2 = 114, REG_TTMP_3 = 115,
  REG_TTMP_4 = 116, REG_TTMP_5 = 117, REG_TTMP_6 = 118, REG_TTMP_7 = 119,
  REG_TTMP_8 = 120, REG_TTMP_9 = 121, REG_TTMP_10 = 122, REG_TTMP_11 = 123,
  REG_M0 = 124, REG_RESERVED_1 = 125, REG_EXEC_LO = 126, REG_EXEC_HI = 127,
  REG_ZERO = 128, REG_INT_CONST_POS_MIN = 129, REG_INT_CONST_POS_MAX = 192, REG_INT_CONST_NEG_MIN = 193,
  REG_INT_CONST_NEG_MAX = 208, REG_RESERVED_2 = 209, REG_RESERVED_3 = 210, REG_RESERVED_4 = 211,
  REG_RESERVED_5 = 212, REG_RESERVED_6 = 213, REG_RESERVED_7 = 214, REG_RESERVED_8 = 215,
  REG_RESERVED_9 = 216, REG_RESERVED_10 = 217, REG_RESERVED_11 = 218, REG_RESERVED_12 = 219,
  REG_RESERVED_13 = 220, REG_RESERVED_14 = 221, REG_RESERVED_15 = 222, REG_RESERVED_16 = 223,
  REG_RESERVED_17 = 224, REG_RESERVED_18 = 225, REG_RESERVED_19 = 226, REG_RESERVED_20 = 227,
  REG_RESERVED_21 = 228, REG_RESERVED_22 = 229, REG_RESERVED_23 = 230, REG_RESERVED_24 = 231,
  REG_RESERVED_25 = 232, REG_RESERVED_26 = 233, REG_RESERVED_27 = 234, REG_RESERVED_28 = 235,
  REG_RESERVED_29 = 236, REG_RESERVED_30 = 237, REG_RESERVED_31 = 238, REG_RESERVED_32 = 239,
  REG_POS_HALF = 240, REG_NEG_HALF = 241, REG_POS_ONE = 242, REG_NEG_ONE = 243,
  REG_POS_TWO = 244, REG_NEG_TWO = 245, REG_POS_FOUR = 246, REG_NEG_FOUR = 247,
  REG_PI = 248, REG_SRC_SWDA = 249, REG_SRC_DPP = 250, REG_VCCZ = 251,
  REG_EXECZ = 252, REG_SCC = 253, REG_LDS_DIRECT = 254, REG_SRC_LITERAL = 255,
  REG_VGPR_MIN = 256, REG_VGPR_MAX = 511, REG_SGPR_MIN = 0, REG_SGPR_MAX = 101,
  REG_FLAT_SCRATCH_LO = 102, REG_FLAT_SCRATCH_HI = 103, REG_XNACK_MASK_LO = 104, REG_XNACK_MASK_HI = 105,
  REG_VCC_LO = 106, REG_VCC_HI = 107, REG_TBA_LO = 108, REG_TBA_HI = 109,
  REG_TMA_LO = 110, REG_TMA_HI = 111, REG_TTMP_0 = 112, REG_TTMP_1 = 113,
  REG_TTMP_2 = 114, REG_TTMP_3 = 115, REG_TTMP_4 = 116, REG_TTMP_5 = 117,
  REG_TTMP_6 = 118, REG_TTMP_7 = 119, REG_TTMP_8 = 120, REG_TTMP_9 = 121,
  REG_TTMP_10 = 122, REG_TTMP_11 = 123, REG_M0 = 124, REG_RESERVED_1 = 125,
  REG_EXEC_LO = 126, REG_EXEC_HI = 127, REG_ZERO = 128, REG_INT_CONST_POS_MIN = 129,
  REG_INT_CONST_POS_MAX = 192, REG_INT_CONST_NEG_MIN = 193, REG_INT_CONST_NEG_MAX = 208, REG_RESERVED_2 = 209,
  REG_RESERVED_3 = 210, REG_RESERVED_4 = 211, REG_RESERVED_5 = 212, REG_RESERVED_6 = 213,
  REG_RESERVED_7 = 214, REG_RESERVED_8 = 215, REG_RESERVED_9 = 216, REG_RESERVED_10 = 217,
  REG_RESERVED_11 = 218, REG_RESERVED_12 = 219, REG_RESERVED_13 = 220, REG_RESERVED_14 = 221,
  REG_RESERVED_15 = 222, REG_RESERVED_16 = 223, REG_RESERVED_17 = 224, REG_RESERVED_18 = 225,
  REG_RESERVED_19 = 226, REG_RESERVED_20 = 227, REG_RESERVED_21 = 228, REG_RESERVED_22 = 229,
  REG_RESERVED_23 = 230, REG_RESERVED_24 = 231, REG_RESERVED_25 = 232, REG_RESERVED_26 = 233,
  REG_RESERVED_27 = 234, REG_RESERVED_28 = 235, REG_RESERVED_29 = 236, REG_RESERVED_30 = 237,
  REG_RESERVED_31 = 238, REG_RESERVED_32 = 239, REG_POS_HALF = 240, REG_NEG_HALF = 241,
  REG_POS_ONE = 242, REG_NEG_ONE = 243, REG_POS_TWO = 244, REG_NEG_TWO = 245,
  REG_POS_FOUR = 246, REG_NEG_FOUR = 247, REG_PI = 248, REG_SRC_SWDA = 249,
  REG_SRC_DPP = 250, REG_VCCZ = 251, REG_EXECZ = 252, REG_SCC = 253,
  REG_LDS_DIRECT = 254, REG_SRC_LITERAL = 255, REG_VGPR_MIN = 256, REG_VGPR_MAX = 511
}
 

Functions

constexpr size_t MaxOperandDwords (16)
 
const int NumVecElemPerVecReg (64)
 
std::string opSelectorToRegSym (int opIdx, int numRegs=0)
 
int opSelectorToRegIdx (int opIdx, int numScalarRegs)
 
bool isPosConstVal (int opIdx)
 
bool isNegConstVal (int opIdx)
 
bool isConstVal (int opIdx)
 
bool isLiteral (int opIdx)
 
bool isScalarReg (int opIdx)
 
bool isVectorReg (int opIdx)
 
bool isFlatScratchReg (int opIdx)
 
bool isExecMask (int opIdx)
 
bool isVccReg (int opIdx)
 
template<typename T >
wholeQuadMode (T val)
 
template<typename T >
quadMask (T val)
 
template<typename T >
ScalarRegI32 countZeroBits (T val)
 
template<typename T >
ScalarRegI32 findFirstZero (T val)
 
template<typename T >
ScalarRegI32 findFirstOne (T val)
 
template<typename T >
ScalarRegI32 findFirstOneMsb (T val)
 
template<typename T >
ScalarRegI32 countZeroBitsMsb (T val)
 
ScalarRegI32 firstOppositeSignBit (ScalarRegI32 val)
 
ScalarRegI32 firstOppositeSignBit (ScalarRegI64 val)
 
template<typename T >
median (T val_0, T val_1, T val_2)
 
template<typename T >
roundNearestEven (T val)
 
VecElemU32 muladd (VecElemU64 &dst, VecElemU32 val_0, VecElemU32 val_1, VecElemU64 val_2)
 
VecElemU32 muladd (VecElemI64 &dst, VecElemI32 val_0, VecElemI32 val_1, VecElemI64 val_2)
 
int dppInstImpl (SqDPPVals dppCtrl, int currLane, int rowNum, int rowOffset, bool &outOfBounds)
 dppInstImpl is a helper function that performs the inputted operation on the inputted vector register lane. More...
 
template<typename T >
void processDPP (GPUDynInstPtr gpuDynInst, InFmt_VOP_DPP dppInst, T &src0)
 processDPP is a helper function for implementing Data Parallel Primitive instructions. More...
 
template<typename T >
void processDPP (GPUDynInstPtr gpuDynInst, InFmt_VOP_DPP dppInst, T &src0, T &src1)
 processDPP is a helper function for implementing Data Parallel Primitive instructions. More...
 
template<typename T >
sdwaInstSrcImpl_helper (T currOperVal, const T origOperVal, const SDWASelVals sel, const bool signExt)
 sdwaInstSrcImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending. More...
 
template<typename T >
void sdwaInstSrcImpl (T &currOper, T &origCurrOper, const SDWASelVals sel, const bool signExt)
 sdwaInstSrcImpl is a helper function that selects the appropriate bits/bytes for each lane of the inputted source operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value. More...
 
template<typename T >
sdwaInstDstImpl_helper (T currDstVal, const T origDstVal, const bool clamp, const SDWASelVals sel, const SDWADstVals unusedBits_format)
 sdwaInstDstImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending. More...
 
template<typename T >
void sdwaInstDstImpl (T &dstOper, T &origDstOper, const bool clamp, const SDWASelVals sel, const SDWADstVals unusedBits_format)
 sdwaInstDestImpl is a helper function that selects the appropriate bits/bytes for the inputted dest operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value. More...
 
template<typename T >
void processSDWA_src_helper (T &currSrc, T &origCurrSrc, const SDWASelVals src_sel, const bool src_signExt, const bool src_abs, const bool src_neg)
 processSDWA_srcHelper is a helper function for implementing sub d-word addressing instructions for the src operands. More...
 
template<typename T >
void processSDWA_src (InFmt_VOP_SDWA sdwaInst, T &src0, T &origSrc0)
 processSDWA_src is a helper function for implementing sub d-word addressing instructions for the src operands. More...
 
template<typename T >
void processSDWA_src (InFmt_VOP_SDWA sdwaInst, T &src0, T &origSrc0, T &src1, T &origSrc1)
 processSDWA_src is a helper function for implementing sub d-word addressing instructions. More...
 
template<typename T >
void processSDWA_dst (InFmt_VOP_SDWA sdwaInst, T &dst, T &origDst)
 processSDWA_dst is a helper function for implementing sub d-word addressing instructions for the dst operand. More...
 

Variables

const int NumPosConstRegs
 
const int NumNegConstRegs
 
const int BITS_PER_BYTE = 8
 
const int BITS_PER_WORD = 16
 
const int MSB_PER_BYTE = (BITS_PER_BYTE - 1)
 
const int MSB_PER_WORD = (BITS_PER_WORD - 1)
 
const int DWordSize = sizeof(VecElemU32)
 
const int RegSizeDWords = sizeof(VecElemU32) / DWordSize
 Size of a single-precision register in DWords. More...
 
const int DWORDSize = sizeof(VecElemU32)
 
const int RegSizeDWORDs = sizeof(VecElemU32) / DWORDSize
 Size of a single-precision register in DWORDs. More...
 

Detailed Description

classes that represnt vector/scalar operands in GCN3 ISA.

these classes wrap the generic vector register type (i.e., src/arch/generic/vec_reg.hh) and allow them to be manipulated in ways that are unique to GCN3 insts.

Typedef Documentation

◆ ConstScalarOperandF32

Definition at line 710 of file operand.hh.

◆ ConstScalarOperandF64

Definition at line 713 of file operand.hh.

◆ ConstScalarOperandI16

Definition at line 707 of file operand.hh.

◆ ConstScalarOperandI32

Definition at line 709 of file operand.hh.

◆ ConstScalarOperandI64

Definition at line 712 of file operand.hh.

◆ ConstScalarOperandI8

Definition at line 705 of file operand.hh.

◆ ConstScalarOperandU128

Definition at line 714 of file operand.hh.

◆ ConstScalarOperandU16

Definition at line 706 of file operand.hh.

◆ ConstScalarOperandU256

Definition at line 715 of file operand.hh.

◆ ConstScalarOperandU32

Definition at line 708 of file operand.hh.

◆ ConstScalarOperandU512

Definition at line 716 of file operand.hh.

◆ ConstScalarOperandU64

Definition at line 711 of file operand.hh.

◆ ConstScalarOperandU8

Definition at line 704 of file operand.hh.

◆ ConstVecOperandF32

Definition at line 739 of file operand.hh.

◆ ConstVecOperandF64

Definition at line 742 of file operand.hh.

◆ ConstVecOperandI16

Definition at line 736 of file operand.hh.

◆ ConstVecOperandI32

Definition at line 738 of file operand.hh.

◆ ConstVecOperandI64

Definition at line 741 of file operand.hh.

◆ ConstVecOperandI8

Definition at line 734 of file operand.hh.

◆ ConstVecOperandU128

Definition at line 744 of file operand.hh.

◆ ConstVecOperandU16

Definition at line 735 of file operand.hh.

◆ ConstVecOperandU256

Definition at line 745 of file operand.hh.

◆ ConstVecOperandU32

Definition at line 737 of file operand.hh.

◆ ConstVecOperandU512

Definition at line 746 of file operand.hh.

◆ ConstVecOperandU64

Definition at line 740 of file operand.hh.

◆ ConstVecOperandU8

Definition at line 733 of file operand.hh.

◆ ConstVecOperandU96

Definition at line 743 of file operand.hh.

◆ IsaDecodeMethod

using gem5::Gcn3ISA::IsaDecodeMethod = typedef GPUStaticInst*(Decoder::*)(MachInst)

Definition at line 52 of file gpu_decoder.hh.

◆ MachInst

used to represent the encoding of a GCN3 inst.

each portion of a GCN3 inst must be 1 DWORD (32b), so we use a pointer to InstFormat type (which is 32b). for the case in which we need multiple DWORDS to represnt a single inst, this pointer essentialy acts as an array of the DWORDs needed to represent the entire inst encoding.

Definition at line 63 of file gpu_types.hh.

◆ RawMachInst

typedef uint64_t gem5::Gcn3ISA::RawMachInst

used to represnt a GPU inst in its raw format.

GCN3 instructions may be 32b or 64b, therefore we represent a raw inst with 64b to ensure that all of its inst data, including potential immediate values, may be represented in the worst case.

Definition at line 44 of file gpu_types.hh.

◆ ScalarOperandF32

Definition at line 696 of file operand.hh.

◆ ScalarOperandF64

Definition at line 699 of file operand.hh.

◆ ScalarOperandI16

Definition at line 693 of file operand.hh.

◆ ScalarOperandI32

Definition at line 695 of file operand.hh.

◆ ScalarOperandI64

Definition at line 698 of file operand.hh.

◆ ScalarOperandI8

Definition at line 691 of file operand.hh.

◆ ScalarOperandU128

Definition at line 700 of file operand.hh.

◆ ScalarOperandU16

Definition at line 692 of file operand.hh.

◆ ScalarOperandU256

Definition at line 701 of file operand.hh.

◆ ScalarOperandU32

Definition at line 694 of file operand.hh.

◆ ScalarOperandU512

Definition at line 702 of file operand.hh.

◆ ScalarOperandU64

Definition at line 697 of file operand.hh.

◆ ScalarOperandU8

Definition at line 690 of file operand.hh.

◆ ScalarRegF32

Definition at line 157 of file gpu_registers.hh.

◆ ScalarRegF64

Definition at line 160 of file gpu_registers.hh.

◆ ScalarRegI16

typedef int16_t gem5::Gcn3ISA::ScalarRegI16

Definition at line 154 of file gpu_registers.hh.

◆ ScalarRegI32

typedef int32_t gem5::Gcn3ISA::ScalarRegI32

Definition at line 156 of file gpu_registers.hh.

◆ ScalarRegI64

typedef int64_t gem5::Gcn3ISA::ScalarRegI64

Definition at line 159 of file gpu_registers.hh.

◆ ScalarRegI8

Definition at line 152 of file gpu_registers.hh.

◆ ScalarRegU16

typedef uint16_t gem5::Gcn3ISA::ScalarRegU16

Definition at line 153 of file gpu_registers.hh.

◆ ScalarRegU32

typedef uint32_t gem5::Gcn3ISA::ScalarRegU32

Definition at line 155 of file gpu_registers.hh.

◆ ScalarRegU64

typedef uint64_t gem5::Gcn3ISA::ScalarRegU64

Definition at line 158 of file gpu_registers.hh.

◆ ScalarRegU8

typedef uint8_t gem5::Gcn3ISA::ScalarRegU8

Definition at line 151 of file gpu_registers.hh.

◆ VecElemF32

Definition at line 169 of file gpu_registers.hh.

◆ VecElemF64

typedef double gem5::Gcn3ISA::VecElemF64

Definition at line 172 of file gpu_registers.hh.

◆ VecElemI16

typedef int16_t gem5::Gcn3ISA::VecElemI16

Definition at line 166 of file gpu_registers.hh.

◆ VecElemI32

typedef int32_t gem5::Gcn3ISA::VecElemI32

Definition at line 168 of file gpu_registers.hh.

◆ VecElemI64

typedef int64_t gem5::Gcn3ISA::VecElemI64

Definition at line 171 of file gpu_registers.hh.

◆ VecElemI8

typedef int8_t gem5::Gcn3ISA::VecElemI8

Definition at line 164 of file gpu_registers.hh.

◆ VecElemU16

typedef uint16_t gem5::Gcn3ISA::VecElemU16

Definition at line 165 of file gpu_registers.hh.

◆ VecElemU32

typedef uint32_t gem5::Gcn3ISA::VecElemU32

Definition at line 167 of file gpu_registers.hh.

◆ VecElemU64

typedef uint64_t gem5::Gcn3ISA::VecElemU64

Definition at line 170 of file gpu_registers.hh.

◆ VecElemU8

typedef uint8_t gem5::Gcn3ISA::VecElemU8

Definition at line 163 of file gpu_registers.hh.

◆ VecOperandF32

Definition at line 724 of file operand.hh.

◆ VecOperandF64

Definition at line 726 of file operand.hh.

◆ VecOperandI16

Definition at line 721 of file operand.hh.

◆ VecOperandI32

Definition at line 723 of file operand.hh.

◆ VecOperandI64

Definition at line 727 of file operand.hh.

◆ VecOperandI8

using gem5::Gcn3ISA::VecOperandI8 = typedef VecOperand<VecElemI8, false, 1>

Definition at line 719 of file operand.hh.

◆ VecOperandU128

Definition at line 729 of file operand.hh.

◆ VecOperandU16

Definition at line 720 of file operand.hh.

◆ VecOperandU256

Definition at line 730 of file operand.hh.

◆ VecOperandU32

Definition at line 722 of file operand.hh.

◆ VecOperandU512

Definition at line 731 of file operand.hh.

◆ VecOperandU64

Definition at line 725 of file operand.hh.

◆ VecOperandU8

using gem5::Gcn3ISA::VecOperandU8 = typedef VecOperand<VecElemU8, false, 1>

Definition at line 718 of file operand.hh.

◆ VecOperandU96

Definition at line 728 of file operand.hh.

◆ VecRegContainerU32

Definition at line 181 of file gpu_registers.hh.

Enumeration Type Documentation

◆ OpSelector [1/2]

Enumerator
REG_SGPR_MIN 
REG_SGPR_MAX 
REG_FLAT_SCRATCH_LO 
REG_FLAT_SCRATCH_HI 
REG_XNACK_MASK_LO 
REG_XNACK_MASK_HI 
REG_VCC_LO 
REG_VCC_HI 
REG_TBA_LO 
REG_TBA_HI 
REG_TMA_LO 
REG_TMA_HI 
REG_TTMP_0 
REG_TTMP_1 
REG_TTMP_2 
REG_TTMP_3 
REG_TTMP_4 
REG_TTMP_5 
REG_TTMP_6 
REG_TTMP_7 
REG_TTMP_8 
REG_TTMP_9 
REG_TTMP_10 
REG_TTMP_11 
REG_M0 
REG_RESERVED_1 
REG_EXEC_LO 
REG_EXEC_HI 
REG_ZERO 
REG_INT_CONST_POS_MIN 
REG_INT_CONST_POS_MAX 
REG_INT_CONST_NEG_MIN 
REG_INT_CONST_NEG_MAX 
REG_RESERVED_2 
REG_RESERVED_3 
REG_RESERVED_4 
REG_RESERVED_5 
REG_RESERVED_6 
REG_RESERVED_7 
REG_RESERVED_8 
REG_RESERVED_9 
REG_RESERVED_10 
REG_RESERVED_11 
REG_RESERVED_12 
REG_RESERVED_13 
REG_RESERVED_14 
REG_RESERVED_15 
REG_RESERVED_16 
REG_RESERVED_17 
REG_RESERVED_18 
REG_RESERVED_19 
REG_RESERVED_20 
REG_RESERVED_21 
REG_RESERVED_22 
REG_RESERVED_23 
REG_RESERVED_24 
REG_RESERVED_25 
REG_RESERVED_26 
REG_RESERVED_27 
REG_RESERVED_28 
REG_RESERVED_29 
REG_RESERVED_30 
REG_RESERVED_31 
REG_RESERVED_32 
REG_POS_HALF 
REG_NEG_HALF 
REG_POS_ONE 
REG_NEG_ONE 
REG_POS_TWO 
REG_NEG_TWO 
REG_POS_FOUR 
REG_NEG_FOUR 
REG_PI 
REG_SRC_SWDA 
REG_SRC_DPP 
REG_VCCZ 
REG_EXECZ 
REG_SCC 
REG_LDS_DIRECT 
REG_SRC_LITERAL 
REG_VGPR_MIN 
REG_VGPR_MAX 
REG_SGPR_MIN 
REG_SGPR_MAX 
REG_FLAT_SCRATCH_LO 
REG_FLAT_SCRATCH_HI 
REG_XNACK_MASK_LO 
REG_XNACK_MASK_HI 
REG_VCC_LO 
REG_VCC_HI 
REG_TBA_LO 
REG_TBA_HI 
REG_TMA_LO 
REG_TMA_HI 
REG_TTMP_0 
REG_TTMP_1 
REG_TTMP_2 
REG_TTMP_3 
REG_TTMP_4 
REG_TTMP_5 
REG_TTMP_6 
REG_TTMP_7 
REG_TTMP_8 
REG_TTMP_9 
REG_TTMP_10 
REG_TTMP_11 
REG_M0 
REG_RESERVED_1 
REG_EXEC_LO 
REG_EXEC_HI 
REG_ZERO 
REG_INT_CONST_POS_MIN 
REG_INT_CONST_POS_MAX 
REG_INT_CONST_NEG_MIN 
REG_INT_CONST_NEG_MAX 
REG_RESERVED_2 
REG_RESERVED_3 
REG_RESERVED_4 
REG_RESERVED_5 
REG_RESERVED_6 
REG_RESERVED_7 
REG_RESERVED_8 
REG_RESERVED_9 
REG_RESERVED_10 
REG_RESERVED_11 
REG_RESERVED_12 
REG_RESERVED_13 
REG_RESERVED_14 
REG_RESERVED_15 
REG_RESERVED_16 
REG_RESERVED_17 
REG_RESERVED_18 
REG_RESERVED_19 
REG_RESERVED_20 
REG_RESERVED_21 
REG_RESERVED_22 
REG_RESERVED_23 
REG_RESERVED_24 
REG_RESERVED_25 
REG_RESERVED_26 
REG_RESERVED_27 
REG_RESERVED_28 
REG_RESERVED_29 
REG_RESERVED_30 
REG_RESERVED_31 
REG_RESERVED_32 
REG_POS_HALF 
REG_NEG_HALF 
REG_POS_ONE 
REG_NEG_ONE 
REG_POS_TWO 
REG_NEG_TWO 
REG_POS_FOUR 
REG_NEG_FOUR 
REG_PI 
REG_SRC_SWDA 
REG_SRC_DPP 
REG_VCCZ 
REG_EXECZ 
REG_SCC 
REG_LDS_DIRECT 
REG_SRC_LITERAL 
REG_VGPR_MIN 
REG_VGPR_MAX 

Definition at line 50 of file gpu_registers.hh.

◆ OpSelector [2/2]

Enumerator
REG_SGPR_MIN 
REG_SGPR_MAX 
REG_FLAT_SCRATCH_LO 
REG_FLAT_SCRATCH_HI 
REG_XNACK_MASK_LO 
REG_XNACK_MASK_HI 
REG_VCC_LO 
REG_VCC_HI 
REG_TBA_LO 
REG_TBA_HI 
REG_TMA_LO 
REG_TMA_HI 
REG_TTMP_0 
REG_TTMP_1 
REG_TTMP_2 
REG_TTMP_3 
REG_TTMP_4 
REG_TTMP_5 
REG_TTMP_6 
REG_TTMP_7 
REG_TTMP_8 
REG_TTMP_9 
REG_TTMP_10 
REG_TTMP_11 
REG_M0 
REG_RESERVED_1 
REG_EXEC_LO 
REG_EXEC_HI 
REG_ZERO 
REG_INT_CONST_POS_MIN 
REG_INT_CONST_POS_MAX 
REG_INT_CONST_NEG_MIN 
REG_INT_CONST_NEG_MAX 
REG_RESERVED_2 
REG_RESERVED_3 
REG_RESERVED_4 
REG_RESERVED_5 
REG_RESERVED_6 
REG_RESERVED_7 
REG_RESERVED_8 
REG_RESERVED_9 
REG_RESERVED_10 
REG_RESERVED_11 
REG_RESERVED_12 
REG_RESERVED_13 
REG_RESERVED_14 
REG_RESERVED_15 
REG_RESERVED_16 
REG_RESERVED_17 
REG_RESERVED_18 
REG_RESERVED_19 
REG_RESERVED_20 
REG_RESERVED_21 
REG_RESERVED_22 
REG_RESERVED_23 
REG_RESERVED_24 
REG_RESERVED_25 
REG_RESERVED_26 
REG_RESERVED_27 
REG_RESERVED_28 
REG_RESERVED_29 
REG_RESERVED_30 
REG_RESERVED_31 
REG_RESERVED_32 
REG_POS_HALF 
REG_NEG_HALF 
REG_POS_ONE 
REG_NEG_ONE 
REG_POS_TWO 
REG_NEG_TWO 
REG_POS_FOUR 
REG_NEG_FOUR 
REG_PI 
REG_SRC_SWDA 
REG_SRC_DPP 
REG_VCCZ 
REG_EXECZ 
REG_SCC 
REG_LDS_DIRECT 
REG_SRC_LITERAL 
REG_VGPR_MIN 
REG_VGPR_MAX 
REG_SGPR_MIN 
REG_SGPR_MAX 
REG_FLAT_SCRATCH_LO 
REG_FLAT_SCRATCH_HI 
REG_XNACK_MASK_LO 
REG_XNACK_MASK_HI 
REG_VCC_LO 
REG_VCC_HI 
REG_TBA_LO 
REG_TBA_HI 
REG_TMA_LO 
REG_TMA_HI 
REG_TTMP_0 
REG_TTMP_1 
REG_TTMP_2 
REG_TTMP_3 
REG_TTMP_4 
REG_TTMP_5 
REG_TTMP_6 
REG_TTMP_7 
REG_TTMP_8 
REG_TTMP_9 
REG_TTMP_10 
REG_TTMP_11 
REG_M0 
REG_RESERVED_1 
REG_EXEC_LO 
REG_EXEC_HI 
REG_ZERO 
REG_INT_CONST_POS_MIN 
REG_INT_CONST_POS_MAX 
REG_INT_CONST_NEG_MIN 
REG_INT_CONST_NEG_MAX 
REG_RESERVED_2 
REG_RESERVED_3 
REG_RESERVED_4 
REG_RESERVED_5 
REG_RESERVED_6 
REG_RESERVED_7 
REG_RESERVED_8 
REG_RESERVED_9 
REG_RESERVED_10 
REG_RESERVED_11 
REG_RESERVED_12 
REG_RESERVED_13 
REG_RESERVED_14 
REG_RESERVED_15 
REG_RESERVED_16 
REG_RESERVED_17 
REG_RESERVED_18 
REG_RESERVED_19 
REG_RESERVED_20 
REG_RESERVED_21 
REG_RESERVED_22 
REG_RESERVED_23 
REG_RESERVED_24 
REG_RESERVED_25 
REG_RESERVED_26 
REG_RESERVED_27 
REG_RESERVED_28 
REG_RESERVED_29 
REG_RESERVED_30 
REG_RESERVED_31 
REG_RESERVED_32 
REG_POS_HALF 
REG_NEG_HALF 
REG_POS_ONE 
REG_NEG_ONE 
REG_POS_TWO 
REG_NEG_TWO 
REG_POS_FOUR 
REG_NEG_FOUR 
REG_PI 
REG_SRC_SWDA 
REG_SRC_DPP 
REG_VCCZ 
REG_EXECZ 
REG_SCC 
REG_LDS_DIRECT 
REG_SRC_LITERAL 
REG_VGPR_MIN 
REG_VGPR_MAX 

Definition at line 50 of file registers.hh.

Function Documentation

◆ countZeroBits()

template<typename T >
ScalarRegI32 gem5::Gcn3ISA::countZeroBits ( val)
inline

◆ countZeroBitsMsb()

template<typename T >
ScalarRegI32 gem5::Gcn3ISA::countZeroBitsMsb ( val)
inline

◆ dppInstImpl()

int gem5::Gcn3ISA::dppInstImpl ( SqDPPVals  dppCtrl,
int  currLane,
int  rowNum,
int  rowOffset,
bool &  outOfBounds 
)

dppInstImpl is a helper function that performs the inputted operation on the inputted vector register lane.

The returned output lane represents the input lane given the destination lane and DPP_CTRL word.

Currently the values are: 0x0 - 0xFF: full permute of four threads 0x100: reserved 0x101 - 0x10F: row shift right by 1-15 threads 0x111 - 0x11F: row shift right by 1-15 threads 0x121 - 0x12F: row shift right by 1-15 threads 0x130: wavefront left shift by 1 thread 0x134: wavefront left rotate by 1 thread 0x138: wavefront right shift by 1 thread 0x13C: wavefront right rotate by 1 thread 0x140: mirror threads within row 0x141: mirror threads within 1/2 row (8 threads) 0x142: broadcast 15th thread of each row to next row 0x143: broadcast thread 31 to rows 2 and 3

Definition at line 320 of file inst_util.hh.

References gem5::X86ISA::count, NumVecElemPerVecReg(), panic, gem5::ROW_SIZE, gem5::SQ_DPP_QUAD_PERM_MAX, gem5::SQ_DPP_RESERVED, gem5::SQ_DPP_ROW_BCAST15, gem5::SQ_DPP_ROW_BCAST31, gem5::SQ_DPP_ROW_HALF_MIRROR, gem5::SQ_DPP_ROW_MIRROR, gem5::SQ_DPP_ROW_RR1, gem5::SQ_DPP_ROW_RR15, gem5::SQ_DPP_ROW_SL1, gem5::SQ_DPP_ROW_SL15, gem5::SQ_DPP_ROW_SR1, gem5::SQ_DPP_ROW_SR15, gem5::SQ_DPP_WF_RL1, gem5::SQ_DPP_WF_RR1, gem5::SQ_DPP_WF_SL1, and gem5::SQ_DPP_WF_SR1.

Referenced by processDPP().

◆ findFirstOne()

template<typename T >
ScalarRegI32 gem5::Gcn3ISA::findFirstOne ( val)
inline

◆ findFirstOneMsb()

template<typename T >
ScalarRegI32 gem5::Gcn3ISA::findFirstOneMsb ( val)
inline

◆ findFirstZero()

template<typename T >
ScalarRegI32 gem5::Gcn3ISA::findFirstZero ( val)
inline

◆ firstOppositeSignBit() [1/2]

ScalarRegI32 gem5::Gcn3ISA::firstOppositeSignBit ( ScalarRegI32  val)
inline

◆ firstOppositeSignBit() [2/2]

ScalarRegI32 gem5::Gcn3ISA::firstOppositeSignBit ( ScalarRegI64  val)
inline

Definition at line 211 of file inst_util.hh.

References gem5::X86ISA::count, gem5::ArmISA::i, and gem5::X86ISA::val.

◆ isConstVal()

bool gem5::Gcn3ISA::isConstVal ( int  opIdx)

◆ isExecMask()

bool gem5::Gcn3ISA::isExecMask ( int  opIdx)

◆ isFlatScratchReg()

bool gem5::Gcn3ISA::isFlatScratchReg ( int  opIdx)

◆ isLiteral()

bool gem5::Gcn3ISA::isLiteral ( int  opIdx)

Definition at line 194 of file registers.cc.

References REG_SRC_LITERAL.

Referenced by gem5::OperandInfo::OperandInfo().

◆ isNegConstVal()

bool gem5::Gcn3ISA::isNegConstVal ( int  opIdx)

Definition at line 178 of file registers.cc.

References REG_INT_CONST_NEG_MAX, and REG_INT_CONST_NEG_MIN.

Referenced by isConstVal(), and gem5::Gcn3ISA::GPUISA::readConstVal().

◆ isPosConstVal()

bool gem5::Gcn3ISA::isPosConstVal ( int  opIdx)

◆ isScalarReg()

bool gem5::Gcn3ISA::isScalarReg ( int  opIdx)

◆ isVccReg()

bool gem5::Gcn3ISA::isVccReg ( int  opIdx)

Definition at line 206 of file registers.cc.

References REG_VCC_HI, and REG_VCC_LO.

Referenced by gem5::OperandInfo::OperandInfo().

◆ isVectorReg()

bool gem5::Gcn3ISA::isVectorReg ( int  opIdx)

◆ MaxOperandDwords()

constexpr size_t gem5::Gcn3ISA::MaxOperandDwords ( 16  )
constexpr

◆ median()

template<typename T >
T gem5::Gcn3ISA::median ( val_0,
val_1,
val_2 
)
inline

◆ muladd() [1/2]

VecElemU32 gem5::Gcn3ISA::muladd ( VecElemI64 dst,
VecElemI32  val_0,
VecElemI32  val_1,
VecElemI64  val_2 
)
inline

Definition at line 287 of file inst_util.hh.

◆ muladd() [2/2]

VecElemU32 gem5::Gcn3ISA::muladd ( VecElemU64 dst,
VecElemU32  val_0,
VecElemU32  val_1,
VecElemU64  val_2 
)
inline

◆ NumVecElemPerVecReg()

const int gem5::Gcn3ISA::NumVecElemPerVecReg ( 64  )

Referenced by gem5::Gcn3ISA::Inst_DS::calcAddr(), gem5::Gcn3ISA::Inst_MUBUF::calcAddr(), gem5::Gcn3ISA::Inst_FLAT::calcAddr(), gem5::Gcn3ISA::Inst_DS__DS_READ_B32::completeAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ2_B32::completeAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ2ST64_B32::completeAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_U8::completeAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_U16::completeAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_B64::completeAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ2_B64::completeAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ2ST64_B64::completeAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_B96::completeAcc(), gem5::Gcn3ISA::Inst_DS__DS_READ_B128::completeAcc(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_UBYTE::completeAcc(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_USHORT::completeAcc(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORD::completeAcc(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2::completeAcc(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3::completeAcc(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_UBYTE::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_SBYTE::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_USHORT::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORD::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX2::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX3::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX4::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SWAP::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC_X2::completeAcc(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2::completeAcc(), dppInstImpl(), gem5::Gcn3ISA::Inst_VOP2__V_CNDMASK_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_SUB_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_SUBREV_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MUL_LEGACY_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MUL_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MUL_I32_I24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MUL_HI_I32_I24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MUL_HI_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MIN_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MAX_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MIN_I32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MAX_I32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MIN_U32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MAX_U32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHRREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ASHRREV_I32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_AND_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_XOR_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MAC_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MADMK_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MADAK_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_SUB_U32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_SUBREV_U32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADDC_U32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_SUBB_U32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_SUBBREV_U32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ADD_U16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_SUB_U16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_SUBREV_U16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MUL_LO_U16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHRREV_B16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_ASHRREV_I16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MAX_U16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MAX_I16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MIN_U16::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MIN_I16::execute(), gem5::Gcn3ISA::Inst_VOP1__V_MOV_B32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_I32_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F64_I32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_I32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_U32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_U32_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_I32_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_RPI_I32_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_FLR_I32_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F64_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE0::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE1::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE2::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F32_UBYTE3::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_U32_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CVT_F64_U32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_TRUNC_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CEIL_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_RNDNE_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FLOOR_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FRACT_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_TRUNC_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_CEIL_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_RNDNE_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FLOOR_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_EXP_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_LOG_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_RCP_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_RCP_IFLAG_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_RSQ_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_RCP_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_RSQ_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_SQRT_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_SQRT_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_SIN_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_COS_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_NOT_B32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_BFREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FFBH_U32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FFBL_B32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FFBH_I32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FREXP_EXP_I32_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FREXP_MANT_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FRACT_F64::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FREXP_EXP_I32_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_FREXP_MANT_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_EXP_LEGACY_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_LOG_LEGACY_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_CLASS_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_CLASS_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_CLASS_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_CLASS_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LG_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_O_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_U_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGE_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLG_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGT_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLE_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NEQ_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLT_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_TRU_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LG_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_O_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_U_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGE_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLG_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGT_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLE_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NEQ_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLT_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_TRU_F32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LG_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_O_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_U_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGE_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLG_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NGT_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLE_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NEQ_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NLT_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_TRU_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LG_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_O_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_U_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGE_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLG_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NGT_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLE_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NEQ_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NLT_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_TRU_F64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_I16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_U16::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_I32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_U32::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_F_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LT_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_EQ_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_LE_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GT_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_NE_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_GE_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMP_T_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_I64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_F_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LT_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_EQ_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_LE_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GT_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_NE_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_GE_U64::execute(), gem5::Gcn3ISA::Inst_VOPC__V_CMPX_T_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_CLASS_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_CLASS_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_CLASS_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_CLASS_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_TRU_F16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_F16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_TRU_F16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LG_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_O_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_U_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLG_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NEQ_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_TRU_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LG_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_O_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_U_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLG_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NEQ_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_TRU_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LG_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_O_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_U_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLG_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NGT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NEQ_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NLT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_TRU_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LG_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_O_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_U_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLG_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NGT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NEQ_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NLT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_TRU_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_F_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LT_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_EQ_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_LE_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GT_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_NE_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_GE_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMP_T_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_F_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LT_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_EQ_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_LE_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GT_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_NE_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_GE_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CMPX_T_U64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CNDMASK_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ADD_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SUB_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SUBREV_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_LEGACY_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_I32_I24::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_HI_I32_I24::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_HI_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MIN_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAX_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MIN_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAX_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MIN_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAX_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LSHRREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ASHRREV_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_AND_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_OR_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_XOR_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAC_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ADD_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SUB_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SUBREV_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ADDC_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SUBB_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SUBBREV_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ADD_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SUB_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SUBREV_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_LO_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LSHLREV_B16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LSHRREV_B16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ASHRREV_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAX_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAX_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MIN_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MIN_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MOV_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_I32_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F64_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_U32_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_I32_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_RPI_I32_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_FLR_I32_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F64_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE0::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE1::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE2::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F32_UBYTE3::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_U32_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_F64_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_TRUNC_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CEIL_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_RNDNE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FLOOR_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FRACT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_TRUNC_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CEIL_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_RNDNE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FLOOR_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_EXP_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LOG_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_RCP_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_RCP_IFLAG_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_RSQ_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_RCP_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_RSQ_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SQRT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SQRT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SIN_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_COS_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_NOT_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_BFREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FFBH_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FFBL_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FFBH_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FREXP_EXP_I32_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FREXP_MANT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FRACT_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FREXP_EXP_I32_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FREXP_MANT_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_EXP_LEGACY_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LOG_LEGACY_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAD_LEGACY_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAD_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAD_I32_I24::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAD_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP3__V_BFE_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_BFE_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_BFI_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FMA_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_FMA_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LERP_U8::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ALIGNBIT_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ALIGNBYTE_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MIN3_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MIN3_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MIN3_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAX3_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAX3_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAX3_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MED3_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MED3_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MED3_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SAD_U8::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SAD_HI_U8::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SAD_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_SAD_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_CVT_PK_U8_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_DIV_FIXUP_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_DIV_FIXUP_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_DIV_SCALE_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_DIV_SCALE_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_DIV_FMAS_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_DIV_FMAS_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAD_U64_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAD_I64_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAD_U16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAD_I16::execute(), gem5::Gcn3ISA::Inst_VOP3__V_PERM_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ADD_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MIN_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MAX_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LDEXP_F64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_LO_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_HI_U32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MUL_HI_I32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LDEXP_F32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_BCNT_U32_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MBCNT_LO_U32_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_MBCNT_HI_U32_B32::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LSHLREV_B64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_LSHRREV_B64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_ASHRREV_I64::execute(), gem5::Gcn3ISA::Inst_VOP3__V_BFM_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE2_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE2ST64_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B8::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B16::execute(), gem5::Gcn3ISA::Inst_DS__DS_SWIZZLE_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_PERMUTE_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_BPERMUTE_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B64::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE2_B64::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B96::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B128::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_BYTE::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_SHORT::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORD::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX2::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX3::execute(), gem5::Gcn3ISA::Inst_MUBUF__BUFFER_STORE_DWORDX4::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_BYTE::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_SHORT::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORD::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX3::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX4::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SWAP::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC_X2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2::execute(), gem5::Gcn3ISA::Inst_FLAT::initAtomicAccess(), gem5::Gcn3ISA::Inst_DS::initDualMemRead(), gem5::Gcn3ISA::Inst_DS::initDualMemWrite(), gem5::Gcn3ISA::Inst_DS::initMemRead(), gem5::Gcn3ISA::Inst_FLAT::initMemRead(), gem5::initMemReqHelper(), gem5::Gcn3ISA::Inst_DS::initMemWrite(), gem5::Gcn3ISA::Inst_FLAT::initMemWrite(), gem5::Gcn3ISA::VecOperand< DataType, Const, NumDwords >::operator[](), processDPP(), gem5::Gcn3ISA::VecOperand< DataType, Const, NumDwords >::read(), sdwaInstDstImpl(), sdwaInstSrcImpl(), and gem5::Gcn3ISA::VecOperand< DataType, Const, NumDwords >::write().

◆ opSelectorToRegIdx()

int gem5::Gcn3ISA::opSelectorToRegIdx ( int  opIdx,
int  numScalarRegs 
)

the VCC register occupies the two highest numbered SRF entries. VCC is typically indexed by specifying VCC_LO (simply called VCC) in the instruction encoding and reading it as a 64b value so we only return the index to the lower half of the VCC register.

VCC_LO = s[NUM_SGPRS - 2] VCC_HI = s[NUM_SGPRS - 1]

the FLAT_SCRATCH register occupies the two SRF entries just below VCC. FLAT_SCRATCH is typically indexed by specifying FLAT_SCRATCH_LO (simply called FLAT_SCRATCH) in the instruction encoding and reading it as a 64b value so we only return the index to the lower half of the FLAT_SCRATCH register.

FLAT_SCRATCH_LO = s[NUM_SGPRS - 4] FLAT_SCRATCH_HI = s[NUM_SGPRS - 3]

the VCC register occupies the two highest numbered SRF entries. VCC is typically indexed by specifying VCC_LO (simply called VCC) in the instruction encoding and reading it as a 64b value so we only return the index to the lower half of the VCC register.

VCC_LO = s[NUM_SGPRS - 2] VCC_HI = s[NUM_SGPRS - 1]

the FLAT_SCRATCH register occupies the two SRF entries just below VCC. FLAT_SCRATCH is typically indexed by specifying FLAT_SCRATCH_LO (simply called FLAT_SCRATCH) in the instruction encoding and reading it as a 64b value so we only return the index to the lower half of the FLAT_SCRATCH register.

FLAT_SCRATCH_LO = s[NUM_SGPRS - 4] FLAT_SCRATCH_HI = s[NUM_SGPRS - 3]

Definition at line 124 of file registers.cc.

References REG_FLAT_SCRATCH_HI, REG_FLAT_SCRATCH_LO, REG_SGPR_MAX, REG_VCC_HI, REG_VCC_LO, REG_VGPR_MAX, and REG_VGPR_MIN.

Referenced by gem5::Gcn3ISA::VecOperand< DataType, Const, NumDwords >::readSrc(), and gem5::OperandInfo::registerIndex().

◆ opSelectorToRegSym()

std::string gem5::Gcn3ISA::opSelectorToRegSym ( int  opIdx,
int  numRegs = 0 
)

◆ processDPP() [1/2]

template<typename T >
void gem5::Gcn3ISA::processDPP ( GPUDynInstPtr  gpuDynInst,
InFmt_VOP_DPP  dppInst,
T &  src0 
)

processDPP is a helper function for implementing Data Parallel Primitive instructions.

This function may be called by many different VOP1 instructions to do operations within a register.

STEP 1a: check if the absolute value (ABS) or negation (NEG) tags are set. If so, do the appropriate action(s) on src0 and/or src1.

NOTE: ABS takes priority over NEG.

STEP 2: check the row and bank mask values. These determine which threads are enabled for the subsequent DPP_CTRL operations.

STEP 4: Handle the potential values of DPP_CTRL: 0x0 - 0xFF: full permute of four threads 0x100: reserved 0x101 - 0x10F: row shift right by 1-15 threads 0x111 - 0x11F: row shift right by 1-15 threads 0x121 - 0x12F: row shift right by 1-15 threads 0x130: wavefront left shift by 1 thread 0x134: wavefront left rotate by 1 thread 0x138: wavefront right shift by 1 thread 0x13C: wavefront right rotate by 1 thread 0x140: mirror threads within row 0x141: mirror threads within 1/2 row (8 threads) 0x142: broadcast 15th thread of each row to next row 0x143: broadcast thread 31 to rows 2 and 3

STEP 4: Implement bound control for disabled threads. If thread is disabled but boundCtrl is set, then we need to set the source data to 0 (i.e., set this lane to 0).

Definition at line 417 of file inst_util.hh.

References gem5::Gcn3ISA::InFmt_VOP_DPP::BANK_MASK, gem5::Gcn3ISA::InFmt_VOP_DPP::BOUND_CTRL, gem5::Gcn3ISA::InFmt_VOP_DPP::DPP_CTRL, dppInstImpl(), gem5::NUM_BANKS, NumVecElemPerVecReg(), gem5::Gcn3ISA::InFmt_VOP_DPP::ROW_MASK, gem5::ROW_SIZE, gem5::Gcn3ISA::InFmt_VOP_DPP::SRC0_ABS, and gem5::Gcn3ISA::InFmt_VOP_DPP::SRC0_NEG.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_ADD_F32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_MAC_F32::execute(), gem5::Gcn3ISA::Inst_VOP1__V_MOV_B32::execute(), and processDPP().

◆ processDPP() [2/2]

template<typename T >
void gem5::Gcn3ISA::processDPP ( GPUDynInstPtr  gpuDynInst,
InFmt_VOP_DPP  dppInst,
T &  src0,
T &  src1 
)

processDPP is a helper function for implementing Data Parallel Primitive instructions.

This function may be called by many different VOP2/VOPC instructions to do operations within a register.

STEP 1b: check if the absolute value (ABS) or negation (NEG) tags are set. If so, do the appropriate action(s) on src0 and/or src1.

NOTE: ABS takes priority over NEG.

Definition at line 526 of file inst_util.hh.

References processDPP(), gem5::Gcn3ISA::InFmt_VOP_DPP::SRC1_ABS, and gem5::Gcn3ISA::InFmt_VOP_DPP::SRC1_NEG.

◆ processSDWA_dst()

template<typename T >
void gem5::Gcn3ISA::processSDWA_dst ( InFmt_VOP_SDWA  sdwaInst,
T &  dst,
T &  origDst 
)

processSDWA_dst is a helper function for implementing sub d-word addressing instructions for the dst operand.

This function may be called by many different VOP1/VOP2/VOPC instructions to do operations within a register. processSDWA_dst is called after the math, while processSDWA_src is called before the math.

STEP 1: select the appropriate bits for dst and pad/sign-extend as appropriate.

Definition at line 881 of file inst_util.hh.

References gem5::Gcn3ISA::InFmt_VOP_SDWA::CLAMP, gem5::Gcn3ISA::InFmt_VOP_SDWA::DST_SEL, gem5::Gcn3ISA::InFmt_VOP_SDWA::DST_UNUSED, and sdwaInstDstImpl().

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), and gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute().

◆ processSDWA_src() [1/2]

template<typename T >
void gem5::Gcn3ISA::processSDWA_src ( InFmt_VOP_SDWA  sdwaInst,
T &  src0,
T &  origSrc0 
)

processSDWA_src is a helper function for implementing sub d-word addressing instructions for the src operands.

This function may be called by many different VOP1 instructions to do operations within a register. processSDWA_dst is called after the math, while processSDWA_src is called before the math.

Definition at line 825 of file inst_util.hh.

References processSDWA_src_helper(), gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_ABS, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_NEG, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_SEL, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_SEXT, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_ABS, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_NEG, and gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_SEXT.

Referenced by gem5::Gcn3ISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::Gcn3ISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::Gcn3ISA::Inst_VOP2__V_OR_B32::execute(), and gem5::Gcn3ISA::Inst_VOP2__V_ADD_U32::execute().

◆ processSDWA_src() [2/2]

template<typename T >
void gem5::Gcn3ISA::processSDWA_src ( InFmt_VOP_SDWA  sdwaInst,
T &  src0,
T &  origSrc0,
T &  src1,
T &  origSrc1 
)

processSDWA_src is a helper function for implementing sub d-word addressing instructions.

This function may be called by many different VOP2/VOPC instructions to do operations within a register. processSDWA_dst is called after the math, while processSDWA_src is called before the math.

Definition at line 853 of file inst_util.hh.

References processSDWA_src_helper(), gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_ABS, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_NEG, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_SEL, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC0_SEXT, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_ABS, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_NEG, gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_SEL, and gem5::Gcn3ISA::InFmt_VOP_SDWA::SRC1_SEXT.

◆ processSDWA_src_helper()

template<typename T >
void gem5::Gcn3ISA::processSDWA_src_helper ( T &  currSrc,
T &  origCurrSrc,
const SDWASelVals  src_sel,
const bool  src_signExt,
const bool  src_abs,
const bool  src_neg 
)

processSDWA_srcHelper is a helper function for implementing sub d-word addressing instructions for the src operands.

This function may be called by many different VOP1/VOP2/VOPC instructions to do operations within a register. This function is also agnostic of which operand it is operating on, so that it can be called for any src operand.

STEP 1: check if the absolute value (ABS) or negation (NEG) tags are set. If so, do the appropriate action(s) on the src operand.

NOTE: According to the CSim implementation, ABS takes priority over NEG.

STEP 2: select the appropriate bits for each lane of source operand.

Definition at line 790 of file inst_util.hh.

References sdwaInstSrcImpl().

Referenced by processSDWA_src().

◆ quadMask()

template<typename T >
T gem5::Gcn3ISA::quadMask ( val)
inline

◆ roundNearestEven()

template<typename T >
T gem5::Gcn3ISA::roundNearestEven ( val)
inline

◆ sdwaInstDstImpl()

template<typename T >
void gem5::Gcn3ISA::sdwaInstDstImpl ( T &  dstOper,
T &  origDstOper,
const bool  clamp,
const SDWASelVals  sel,
const SDWADstVals  unusedBits_format 
)

sdwaInstDestImpl is a helper function that selects the appropriate bits/bytes for the inputted dest operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value.

The desired behavior is:

  1. Select the appropriate bits/bytes based on sel: 0 (SDWA_BYTE_0): select data[7:0] 1 (SDWA_BYTE_1): select data[15:8] 2 (SDWA_BYTE_2): select data[23:16] 3 (SDWA_BYTE_3): select data[31:24] 4 (SDWA_WORD_0): select data[15:0] 5 (SDWA_WORD_1): select data[31:16] 6 (SDWA_DWORD): select data[31:0]
  2. either pad, sign extend, or select all bits based on the value of unusedBits_format: 0 (SDWA_UNUSED_PAD): pad all unused bits with 0 1 (SDWA_UNUSED_SEXT): sign-extend upper bits; pad lower bits w/ 0 2 (SDWA_UNUSED_PRESERVE): select data[31:0]

Definition at line 769 of file inst_util.hh.

References NumVecElemPerVecReg(), sdwaInstDstImpl_helper(), and gem5::ArmISA::sel.

Referenced by processSDWA_dst().

◆ sdwaInstDstImpl_helper()

template<typename T >
T gem5::Gcn3ISA::sdwaInstDstImpl_helper ( currDstVal,
const T  origDstVal,
const bool  clamp,
const SDWASelVals  sel,
const SDWADstVals  unusedBits_format 
)

sdwaInstDstImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending.

It returns the value after these operations are done on it.

Definition at line 668 of file inst_util.hh.

References gem5::bits(), BITS_PER_BYTE, BITS_PER_WORD, gem5::insertBits(), MSB_PER_BYTE, MSB_PER_WORD, panic, gem5::SDWA_DWORD, gem5::SDWA_UNUSED_PRESERVE, gem5::SDWA_UNUSED_SEXT, gem5::SDWA_WORD_0, and gem5::ArmISA::sel.

Referenced by sdwaInstDstImpl().

◆ sdwaInstSrcImpl()

template<typename T >
void gem5::Gcn3ISA::sdwaInstSrcImpl ( T &  currOper,
T &  origCurrOper,
const SDWASelVals  sel,
const bool  signExt 
)

sdwaInstSrcImpl is a helper function that selects the appropriate bits/bytes for each lane of the inputted source operand of an SDWA instruction, does the appropriate masking/padding/sign extending for the non-selected bits/bytes, and updates the operands values with the resultant value.

The desired behavior is:

  1. Select the appropriate bits/bytes based on sel: 0 (SDWA_BYTE_0): select data[7:0] 1 (SDWA_BYTE_1): select data[15:8] 2 (SDWA_BYTE_2): select data[23:16] 3 (SDWA_BYTE_3): select data[31:24] 4 (SDWA_WORD_0): select data[15:0] 5 (SDWA_WORD_1): select data[31:16] 6 (SDWA_DWORD): select data[31:0]
  2. if sign extend is set, then sign extend the value

Definition at line 649 of file inst_util.hh.

References NumVecElemPerVecReg(), sdwaInstSrcImpl_helper(), and gem5::ArmISA::sel.

Referenced by processSDWA_src_helper().

◆ sdwaInstSrcImpl_helper()

template<typename T >
T gem5::Gcn3ISA::sdwaInstSrcImpl_helper ( currOperVal,
const T  origOperVal,
const SDWASelVals  sel,
const bool  signExt 
)

sdwaInstSrcImpl_helper contains the per-lane code for selecting the appropriate bytes/words of the lane and doing the appropriate masking/padding/sign extending.

It returns the value after these operations are done on it.

Definition at line 556 of file inst_util.hh.

References gem5::bits(), BITS_PER_BYTE, BITS_PER_WORD, fatal_if, MSB_PER_BYTE, MSB_PER_WORD, panic, gem5::SDWA_DWORD, gem5::SDWA_WORD_0, and gem5::ArmISA::sel.

Referenced by sdwaInstSrcImpl().

◆ wholeQuadMode()

template<typename T >
T gem5::Gcn3ISA::wholeQuadMode ( val)
inline

Variable Documentation

◆ BITS_PER_BYTE

const int gem5::Gcn3ISA::BITS_PER_BYTE = 8

Definition at line 145 of file gpu_registers.hh.

Referenced by sdwaInstDstImpl_helper(), and sdwaInstSrcImpl_helper().

◆ BITS_PER_WORD

const int gem5::Gcn3ISA::BITS_PER_WORD = 16

Definition at line 146 of file gpu_registers.hh.

Referenced by sdwaInstDstImpl_helper(), and sdwaInstSrcImpl_helper().

◆ DWORDSize

const int gem5::Gcn3ISA::DWORDSize = sizeof(VecElemU32)

Definition at line 174 of file registers.hh.

◆ DWordSize

const int gem5::Gcn3ISA::DWordSize = sizeof(VecElemU32)

Definition at line 174 of file gpu_registers.hh.

◆ MSB_PER_BYTE

const int gem5::Gcn3ISA::MSB_PER_BYTE = (BITS_PER_BYTE - 1)

Definition at line 147 of file gpu_registers.hh.

Referenced by sdwaInstDstImpl_helper(), and sdwaInstSrcImpl_helper().

◆ MSB_PER_WORD

const int gem5::Gcn3ISA::MSB_PER_WORD = (BITS_PER_WORD - 1)

Definition at line 148 of file gpu_registers.hh.

Referenced by sdwaInstDstImpl_helper(), and sdwaInstSrcImpl_helper().

◆ NumNegConstRegs

const int gem5::Gcn3ISA::NumNegConstRegs
Initial value:

Definition at line 143 of file gpu_registers.hh.

◆ NumPosConstRegs

const int gem5::Gcn3ISA::NumPosConstRegs
Initial value:

Definition at line 140 of file gpu_registers.hh.

◆ RegSizeDWORDs

const int gem5::Gcn3ISA::RegSizeDWORDs = sizeof(VecElemU32) / DWORDSize

Size of a single-precision register in DWORDs.

Definition at line 178 of file registers.hh.

◆ RegSizeDWords

const int gem5::Gcn3ISA::RegSizeDWords = sizeof(VecElemU32) / DWordSize

Size of a single-precision register in DWords.

Definition at line 178 of file gpu_registers.hh.

Referenced by gem5::OperandInfo::numRegisters(), and gem5::RegisterOperandInfo::numRegisters().

gem5::VegaISA::REG_INT_CONST_NEG_MIN
@ REG_INT_CONST_NEG_MIN
Definition: gpu_registers.hh:83
gem5::VegaISA::REG_INT_CONST_POS_MIN
@ REG_INT_CONST_POS_MIN
Definition: gpu_registers.hh:81
gem5::VegaISA::REG_INT_CONST_NEG_MAX
@ REG_INT_CONST_NEG_MAX
Definition: gpu_registers.hh:84
gem5::VegaISA::REG_INT_CONST_POS_MAX
@ REG_INT_CONST_POS_MAX
Definition: gpu_registers.hh:82

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