gem5
v24.0.0.0
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arch
arm
fastmodel
iris
isa.cc
Go to the documentation of this file.
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/*
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* Copyright 2020 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/arm/fastmodel/iris/isa.hh
"
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#include "
arch/arm/regs/misc.hh
"
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#include "
base/logging.hh
"
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#include "
cpu/thread_context.hh
"
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#include "
sim/serialize.hh
"
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namespace
gem5
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{
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void
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Iris::ISA::serialize
(
CheckpointOut
&cp)
const
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{
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RegVal
miscRegs[
ArmISA::NUM_PHYS_MISCREGS
];
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for
(
int
i
= 0;
i
<
ArmISA::NUM_PHYS_MISCREGS
;
i
++)
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miscRegs[
i
] =
tc
->
readMiscRegNoEffect
(
i
);
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SERIALIZE_ARRAY
(miscRegs,
ArmISA::NUM_PHYS_MISCREGS
);
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}
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void
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Iris::ISA::copyRegsFrom
(
ThreadContext
*src)
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{
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panic
(
"copyRegsFrom not implemented"
);
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}
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}
// namespace gem5
misc.hh
isa.hh
gem5::BaseISA::tc
ThreadContext * tc
Definition
isa.hh:68
gem5::Iris::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition
isa.cc:48
gem5::Iris::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition
isa.cc:39
gem5::Iris::ThreadContext
Definition
thread_context.hh:55
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition
logging.hh:188
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition
serialize.hh:610
logging.hh
gem5::ArmISA::i
Bitfield< 7 > i
Definition
misc_types.hh:67
gem5::ArmISA::NUM_PHYS_MISCREGS
@ NUM_PHYS_MISCREGS
Definition
misc.hh:1168
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::RegVal
uint64_t RegVal
Definition
types.hh:173
gem5::CheckpointOut
std::ostream CheckpointOut
Definition
serialize.hh:66
serialize.hh
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