gem5  v21.1.0.2
thread_context.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
29 #define __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
30 
31 #include <list>
32 #include <map>
33 #include <memory>
34 
35 #include "arch/arm/regs/vec.hh"
36 #include "cpu/base.hh"
37 #include "cpu/thread_context.hh"
38 #include "iris/IrisInstance.h"
39 #include "iris/detail/IrisErrorCode.h"
40 #include "iris/detail/IrisObjects.h"
41 #include "sim/system.hh"
42 
43 namespace gem5
44 {
45 
46 namespace Iris
47 {
48 
49 // This class is the base for ThreadContexts which read and write state using
50 // the Iris API.
52 {
53  public:
54  typedef std::map<std::string, iris::ResourceInfo> ResourceMap;
55 
57  typedef std::map<int, std::string> IdxNameMap;
58 
59  protected:
61  int _threadId;
66 
67  std::string _irisPath;
68  iris::InstanceId _instId = iris::IRIS_UINT64_MAX;
69 
70  // Temporary holding places for the vector reg accessors to return.
71  // These are not updated live, only when requested.
74 
77 
78  virtual void initFromIrisInstance(const ResourceMap &resources);
79 
80  iris::ResourceId extractResourceId(
81  const ResourceMap &resources, const std::string &name);
83  const ResourceMap &resources, const IdxNameMap &idx_names);
84 
85 
91 
92  iris::ResourceId pcRscId = iris::IRIS_UINT64_MAX;
93  iris::ResourceId icountRscId;
94 
97 
100 
101  std::unique_ptr<PortProxy> virtProxy = nullptr;
102 
103 
104  // A queue to keep track of instruction count based events.
106  // A helper function to maintain the IRIS step count. This makes sure the
107  // step count is correct even after IRIS resets it for us, and also handles
108  // events which are supposed to happen at the current instruction count.
109  void maintainStepping();
110 
111 
112  using BpId = uint64_t;
113  struct BpInfo
114  {
118  std::shared_ptr<EventList> events;
119 
120  BpInfo(Addr _pc) : pc(_pc), events(new EventList) {}
121 
122  bool empty() const { return events->empty(); }
123  bool validIds() const { return !ids.empty(); }
124  void clearIds() { ids.clear(); }
125  };
126 
127  using BpInfoPtr = std::unique_ptr<BpInfo>;
128  using BpInfoMap = std::map<Addr, BpInfoPtr>;
129  using BpInfoIt = BpInfoMap::iterator;
130 
132 
134 
135  void installBp(BpInfoIt it);
136  void uninstallBp(BpInfoIt it);
137  void delBp(BpInfoIt it);
138 
139  virtual const std::vector<iris::MemorySpaceId> &getBpSpaceIds() const = 0;
140 
141 
142  iris::IrisErrorCode instanceRegistryChanged(
143  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
144  uint64_t sInstId, bool syncEc, std::string &error_message_out);
145  iris::IrisErrorCode phaseInitLeave(
146  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
147  uint64_t sInstId, bool syncEc, std::string &error_message_out);
148  iris::IrisErrorCode simulationTimeEvent(
149  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
150  uint64_t sInstId, bool syncEc, std::string &error_message_out);
151  iris::IrisErrorCode breakpointHit(
152  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
153  uint64_t sInstId, bool syncEc, std::string &error_message_out);
154  iris::IrisErrorCode semihostingEvent(
155  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
156  uint64_t sInstId, bool syncEc, std::string &error_message_out);
157 
158  iris::EventStreamId regEventStreamId;
159  iris::EventStreamId initEventStreamId;
160  iris::EventStreamId timeEventStreamId;
161  iris::EventStreamId breakpointEventStreamId;
162  iris::EventStreamId semihostingEventStreamId;
163 
164  mutable iris::IrisInstance client;
165  iris::IrisCppAdapter &call() const { return client.irisCall(); }
166  iris::IrisCppAdapter &noThrow() const { return client.irisCallNoThrow(); }
167 
168  bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space,
169  Addr vaddr, iris::MemorySpaceId v_space);
170 
171  public:
172  ThreadContext(gem5::BaseCPU *cpu, int id, System *system,
173  gem5::BaseMMU *mmu, gem5::BaseISA *isa,
174  iris::IrisConnectionInterface *iris_if,
175  const std::string &iris_path);
176  virtual ~ThreadContext();
177 
178  virtual bool translateAddress(Addr &paddr, Addr vaddr) = 0;
179 
180  bool schedule(PCEvent *e) override;
181  bool remove(PCEvent *e) override;
182 
183  void scheduleInstCountEvent(Event *event, Tick count) override;
184  void descheduleInstCountEvent(Event *event) override;
185  Tick getCurrentInstCount() override;
186 
187  gem5::BaseCPU *getCpuPtr() override { return _cpu; }
188  int cpuId() const override { return _cpu->cpuId(); }
189  uint32_t socketId() const override { return _cpu->socketId(); }
190 
191  int threadId() const override { return _threadId; }
192  void setThreadId(int id) override { _threadId = id; }
193 
194  int contextId() const override { return _contextId; }
195  void setContextId(int id) override { _contextId = id; }
196 
197  BaseMMU *
198  getMMUPtr() override
199  {
200  return _mmu;
201  }
202 
203  CheckerCPU *getCheckerCpuPtr() override { return nullptr; }
205  getDecoderPtr() override
206  {
207  panic("%s not implemented.", __FUNCTION__);
208  }
209 
210  System *getSystemPtr() override { return _cpu->system; }
211 
212  BaseISA *
213  getIsaPtr() override
214  {
215  return _isa;
216  }
217 
218  PortProxy &getVirtProxy() override { return *virtProxy; }
219  void initMemProxies(gem5::ThreadContext *tc) override;
220 
221  void sendFunctional(PacketPtr pkt) override;
222 
223  Process *
224  getProcessPtr() override
225  {
226  panic("%s not implemented.", __FUNCTION__);
227  }
228  void
230  {
231  panic("%s not implemented.", __FUNCTION__);
232  }
233 
234  Status status() const override;
235  void setStatus(Status new_status) override;
236  void activate() override { setStatus(Active); }
237  void suspend() override { setStatus(Suspended); }
238  void halt() override { setStatus(Halted); }
239 
240  void
241  takeOverFrom(gem5::ThreadContext *old_context) override
242  {
243  panic("%s not implemented.", __FUNCTION__);
244  }
245 
246  void regStats(const std::string &name) override {}
247 
248  // Not necessarily the best location for these...
249  // Having an extra function just to read these is obnoxious
250  Tick
251  readLastActivate() override
252  {
253  panic("%s not implemented.", __FUNCTION__);
254  }
256  {
257  panic("%s not implemented.", __FUNCTION__);
258  }
259 
260  void
262  {
263  panic("%s not implemented.", __FUNCTION__);
264  }
265 
266  void
267  clearArchRegs() override
268  {
269  warn("Ignoring clearArchRegs()");
270  }
271 
272  //
273  // New accessors for new decoder.
274  //
275  RegVal readIntReg(RegIndex reg_idx) const override;
276 
277  RegVal
278  readFloatReg(RegIndex reg_idx) const override
279  {
280  panic("%s not implemented.", __FUNCTION__);
281  }
282 
283  const ArmISA::VecRegContainer &readVecReg(const RegId &reg) const override;
285  getWritableVecReg(const RegId &reg) override
286  {
287  panic("%s not implemented.", __FUNCTION__);
288  }
289 
290  const ArmISA::VecElem &
291  readVecElem(const RegId &reg) const override
292  {
293  panic("%s not implemented.", __FUNCTION__);
294  }
295 
297  readVecPredReg(const RegId &reg) const override;
299  getWritableVecPredReg(const RegId &reg) override
300  {
301  panic("%s not implemented.", __FUNCTION__);
302  }
303 
304  RegVal
305  readCCReg(RegIndex reg_idx) const override
306  {
307  return readCCRegFlat(reg_idx);
308  }
309 
310  void setIntReg(RegIndex reg_idx, RegVal val) override;
311 
312  void
313  setFloatReg(RegIndex reg_idx, RegVal val) override
314  {
315  panic("%s not implemented.", __FUNCTION__);
316  }
317 
318  void
319  setVecReg(const RegId &reg, const ArmISA::VecRegContainer &val) override
320  {
321  panic("%s not implemented.", __FUNCTION__);
322  }
323 
324  void
325  setVecElem(const RegId& reg, const ArmISA::VecElem& val) override
326  {
327  panic("%s not implemented.", __FUNCTION__);
328  }
329 
330  void
332  const ArmISA::VecPredRegContainer &val) override
333  {
334  panic("%s not implemented.", __FUNCTION__);
335  }
336 
337  void
338  setCCReg(RegIndex reg_idx, RegVal val) override
339  {
340  setCCRegFlat(reg_idx, val);
341  }
342 
343  void pcStateNoRecord(const ArmISA::PCState &val) override { pcState(val); }
344  MicroPC microPC() const override { return 0; }
345 
346  ArmISA::PCState pcState() const override;
347  void pcState(const ArmISA::PCState &val) override;
348  Addr instAddr() const override;
349  Addr nextInstAddr() const override;
350 
351  RegVal readMiscRegNoEffect(RegIndex misc_reg) const override;
352  RegVal
353  readMiscReg(RegIndex misc_reg) override
354  {
355  return readMiscRegNoEffect(misc_reg);
356  }
357 
358  void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override;
359  void
360  setMiscReg(RegIndex misc_reg, const RegVal val) override
361  {
362  setMiscRegNoEffect(misc_reg, val);
363  }
364 
365  RegId
366  flattenRegId(const RegId& regId) const override
367  {
368  panic("%s not implemented.", __FUNCTION__);
369  }
370 
371  // Also not necessarily the best location for these two. Hopefully will go
372  // away once we decide upon where st cond failures goes.
373  unsigned
374  readStCondFailures() const override
375  {
376  panic("%s not implemented.", __FUNCTION__);
377  }
378 
379  void
380  setStCondFailures(unsigned sc_failures) override
381  {
382  panic("%s not implemented.", __FUNCTION__);
383  }
384 
397  RegVal readIntRegFlat(RegIndex idx) const override;
398  void setIntRegFlat(RegIndex idx, uint64_t val) override;
399 
400  RegVal
401  readFloatRegFlat(RegIndex idx) const override
402  {
403  panic("%s not implemented.", __FUNCTION__);
404  }
405  void
407  {
408  panic("%s not implemented.", __FUNCTION__);
409  }
410 
411  const ArmISA::VecRegContainer &readVecRegFlat(RegIndex idx) const override;
414  {
415  panic("%s not implemented.", __FUNCTION__);
416  }
417  void
419  {
420  panic("%s not implemented.", __FUNCTION__);
421  }
422 
423  const ArmISA::VecElem&
424  readVecElemFlat(RegIndex idx, const ElemIndex& elemIdx) const override
425  {
426  panic("%s not implemented.", __FUNCTION__);
427  }
428  void
429  setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx,
430  const ArmISA::VecElem &val) override
431  {
432  panic("%s not implemented.", __FUNCTION__);
433  }
434 
436  readVecPredRegFlat(RegIndex idx) const override;
439  {
440  panic("%s not implemented.", __FUNCTION__);
441  }
442  void
444  const ArmISA::VecPredRegContainer &val) override
445  {
446  panic("%s not implemented.", __FUNCTION__);
447  }
448 
449  RegVal readCCRegFlat(RegIndex idx) const override;
450  void setCCRegFlat(RegIndex idx, RegVal val) override;
453  // hardware transactional memory
454  void
455  htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
456  {
457  panic("%s not implemented.", __FUNCTION__);
458  }
459 
462  {
463  panic("%s not implemented.", __FUNCTION__);
464  }
465 
466  void
468  {
469  panic("%s not implemented.", __FUNCTION__);
470  }
471 };
472 
473 } // namespace Iris
474 } // namespace gem5
475 
476 #endif // __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
gem5::Iris::ThreadContext::readLastSuspend
Tick readLastSuspend() override
Definition: thread_context.hh:255
gem5::Iris::ThreadContext::IdxNameMap
std::map< int, std::string > IdxNameMap
Definition: thread_context.hh:57
gem5::Iris::ThreadContext::setVecReg
void setVecReg(const RegId &reg, const ArmISA::VecRegContainer &val) override
Definition: thread_context.hh:319
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:108
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::Iris::ThreadContext::getSystemPtr
System * getSystemPtr() override
Definition: thread_context.hh:210
warn
#define warn(...)
Definition: logging.hh:245
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::Iris::ThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
Definition: thread_context.cc:616
system.hh
gem5::Iris::ThreadContext::pcState
ArmISA::PCState pcState() const override
Definition: thread_context.cc:522
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::Iris::ThreadContext::BpInfo::ids
std::vector< BpId > ids
Definition: thread_context.hh:116
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:121
gem5::Iris::ThreadContext::vecRegIds
ResourceIds vecRegIds
Definition: thread_context.hh:95
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::Iris::ThreadContext::readVecPredReg
const ArmISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const override
Definition: thread_context.cc:688
gem5::Iris::ThreadContext::takeOverFrom
void takeOverFrom(gem5::ThreadContext *old_context) override
Definition: thread_context.hh:241
gem5::Iris::ThreadContext::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: thread_context.hh:353
gem5::Iris::ThreadContext::BpInfo::events
std::shared_ptr< EventList > events
Definition: thread_context.hh:118
gem5::Iris::ThreadContext::regEventStreamId
iris::EventStreamId regEventStreamId
Definition: thread_context.hh:158
gem5::Iris::ThreadContext::_isa
gem5::BaseISA * _isa
Definition: thread_context.hh:65
gem5::Iris::ThreadContext::microPC
MicroPC microPC() const override
Definition: thread_context.hh:344
gem5::Iris::ThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.hh:238
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::Iris::ThreadContext::nextInstAddr
Addr nextInstAddr() const override
Definition: thread_context.cc:566
gem5::Iris::ThreadContext::threadId
int threadId() const override
Definition: thread_context.hh:191
gem5::Iris::ThreadContext::call
iris::IrisCppAdapter & call() const
Definition: thread_context.hh:165
gem5::Iris::ThreadContext::getIsaPtr
BaseISA * getIsaPtr() override
Definition: thread_context.hh:213
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::Iris::ThreadContext::setVecRegFlat
void setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val) override
Definition: thread_context.hh:418
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:104
gem5::Iris::ThreadContext::BpInfoMap
std::map< Addr, BpInfoPtr > BpInfoMap
Definition: thread_context.hh:128
gem5::Iris::ThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.hh:455
gem5::BaseCPU::system
System * system
Definition: base.hh:376
gem5::Iris::ThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.cc:600
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
vec.hh
std::vector< iris::ResourceId >
gem5::Iris::ThreadContext::getWritableVecRegFlat
ArmISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
Definition: thread_context.hh:413
gem5::Iris::ThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.hh:236
gem5::ArmISA::ids
Bitfield< 39, 36 > ids
Definition: misc_types.hh:153
gem5::Iris::ThreadContext::breakpointHit
iris::IrisErrorCode breakpointHit(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:268
gem5::Iris::ThreadContext::sendFunctional
void sendFunctional(PacketPtr pkt) override
Definition: thread_context.cc:493
gem5::Iris::ThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.cc:465
gem5::Iris::ThreadContext::installBp
void installBp(BpInfoIt it)
Definition: thread_context.cc:162
gem5::Iris::ThreadContext::_mmu
gem5::BaseMMU * _mmu
Definition: thread_context.hh:64
gem5::Iris::ThreadContext::BpInfo::clearIds
void clearIds()
Definition: thread_context.hh:124
gem5::Iris::ThreadContext::initFromIrisInstance
virtual void initFromIrisInstance(const ResourceMap &resources)
Definition: thread_context.cc:60
gem5::Iris::ThreadContext::getVirtProxy
PortProxy & getVirtProxy() override
Definition: thread_context.hh:218
gem5::Iris::ThreadContext::icountRscId
iris::ResourceId icountRscId
Definition: thread_context.hh:93
gem5::BaseCPU::socketId
uint32_t socketId() const
Reads this CPU's Socket ID.
Definition: base.hh:191
gem5::Iris::ThreadContext::getOrAllocBp
BpInfoIt getOrAllocBp(Addr pc)
Definition: thread_context.cc:149
gem5::Iris::ThreadContext::uninstallBp
void uninstallBp(BpInfoIt it)
Definition: thread_context.cc:174
gem5::Iris::ThreadContext::getCpuPtr
gem5::BaseCPU * getCpuPtr() override
Definition: thread_context.hh:187
gem5::Iris::ThreadContext::maintainStepping
void maintainStepping()
Definition: thread_context.cc:120
gem5::Iris::ThreadContext::enableAfterPseudoEvent
Event * enableAfterPseudoEvent
Definition: thread_context.hh:76
gem5::Iris::ThreadContext::breakpointEventStreamId
iris::EventStreamId breakpointEventStreamId
Definition: thread_context.hh:161
gem5::Iris::ThreadContext::memorySpaces
std::vector< iris::MemorySpaceInfo > memorySpaces
Definition: thread_context.hh:98
gem5::BaseMMU
Definition: mmu.hh:50
gem5::Iris::ThreadContext::_status
Status _status
Definition: thread_context.hh:75
gem5::Iris::ThreadContext::vecPredRegs
std::vector< ArmISA::VecPredRegContainer > vecPredRegs
Definition: thread_context.hh:73
gem5::Iris::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.hh:237
gem5::Iris::ThreadContext::noThrow
iris::IrisCppAdapter & noThrow() const
Definition: thread_context.hh:166
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::Iris::ThreadContext::simulationTimeEvent
iris::IrisErrorCode simulationTimeEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:246
gem5::Iris::ThreadContext::getWritableVecReg
ArmISA::VecRegContainer & getWritableVecReg(const RegId &reg) override
Definition: thread_context.hh:285
gem5::System
Definition: system.hh:77
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)>
gem5::Iris::ThreadContext::readVecElem
const ArmISA::VecElem & readVecElem(const RegId &reg) const override
Definition: thread_context.hh:291
gem5::Iris::ThreadContext::copyArchRegs
void copyArchRegs(gem5::ThreadContext *tc) override
Definition: thread_context.hh:261
gem5::Iris::ThreadContext::setThreadId
void setThreadId(int id) override
Definition: thread_context.hh:192
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Iris::ThreadContext::readCCReg
RegVal readCCReg(RegIndex reg_idx) const override
Definition: thread_context.hh:305
gem5::Iris::ThreadContext::cpuId
int cpuId() const override
Definition: thread_context.hh:188
gem5::Iris::ThreadContext::~ThreadContext
virtual ~ThreadContext()
Definition: thread_context.cc:377
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:112
gem5::Event
Definition: eventq.hh:251
gem5::Iris::ThreadContext::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:338
gem5::Iris::ThreadContext::BpInfoIt
BpInfoMap::iterator BpInfoIt
Definition: thread_context.hh:129
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Iris::ThreadContext::_irisPath
std::string _irisPath
Definition: thread_context.hh:67
gem5::Iris::ThreadContext::getDecoderPtr
ArmISA::Decoder * getDecoderPtr() override
Definition: thread_context.hh:205
gem5::Iris::ThreadContext::pcStateNoRecord
void pcStateNoRecord(const ArmISA::PCState &val) override
Definition: thread_context.hh:343
gem5::Iris::ThreadContext::miscRegIds
ResourceIds miscRegIds
Definition: thread_context.hh:86
gem5::Iris::ThreadContext
Definition: thread_context.hh:51
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Iris::ThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.hh:461
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Iris::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override
Definition: thread_context.cc:580
gem5::PCEvent
Definition: pc_event.hh:45
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::Iris::ThreadContext::virtProxy
std::unique_ptr< PortProxy > virtProxy
Definition: thread_context.hh:101
gem5::Iris::ThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val) override
Definition: thread_context.hh:313
gem5::Iris::ThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) override
Definition: thread_context.hh:467
gem5::Iris::ThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const override
Definition: thread_context.cc:641
gem5::Iris::ThreadContext::ThreadContext
ThreadContext(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
Definition: thread_context.cc:310
gem5::ArmISA::Decoder
Definition: decoder.hh:62
gem5::Iris::ThreadContext::readVecPredRegFlat
const ArmISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
Definition: thread_context.cc:717
gem5::Iris::ThreadContext::BpInfoPtr
std::unique_ptr< BpInfo > BpInfoPtr
Definition: thread_context.hh:127
gem5::Iris::ThreadContext::phaseInitLeave
iris::IrisErrorCode phaseInitLeave(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:216
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::EventQueue
Queue of events sorted in time order.
Definition: eventq.hh:622
gem5::Iris::ThreadContext::getWritableVecPredRegFlat
ArmISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
Definition: thread_context.hh:438
gem5::Iris::ThreadContext::_system
System * _system
Definition: thread_context.hh:63
gem5::Iris::ThreadContext::readVecRegFlat
const ArmISA::VecRegContainer & readVecRegFlat(RegIndex idx) const override
Definition: thread_context.cc:682
gem5::Iris::ThreadContext::clearArchRegs
void clearArchRegs() override
Definition: thread_context.hh:267
gem5::Iris::ThreadContext::translations
std::vector< iris::MemorySupportedAddressTranslationResult > translations
Definition: thread_context.hh:99
gem5::BaseCPU
Definition: base.hh:107
gem5::Iris::ThreadContext::extractResourceMap
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
Definition: thread_context.cc:104
gem5::Iris::ThreadContext::ccRegIds
ResourceIds ccRegIds
Definition: thread_context.hh:90
gem5::Iris::ThreadContext::contextId
int contextId() const override
Definition: thread_context.hh:194
gem5::Iris::ThreadContext::setStCondFailures
void setStCondFailures(unsigned sc_failures) override
Definition: thread_context.hh:380
gem5::Iris::ThreadContext::readStCondFailures
unsigned readStCondFailures() const override
Definition: thread_context.hh:374
gem5::Iris::ThreadContext::flattenedIntIds
ResourceIds flattenedIntIds
Definition: thread_context.hh:89
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uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Iris::ThreadContext::delBp
void delBp(BpInfoIt it)
Definition: thread_context.cc:182
gem5::Iris::ThreadContext::vecRegs
std::vector< ArmISA::VecRegContainer > vecRegs
Definition: thread_context.hh:72
gem5::Iris::ThreadContext::readVecElemFlat
const ArmISA::VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elemIdx) const override
Definition: thread_context.hh:424
gem5::Iris::ThreadContext::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const override
Definition: thread_context.hh:401
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uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
name
const std::string & name()
Definition: trace.cc:49
gem5::Iris::ThreadContext::extractResourceId
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
Definition: thread_context.cc:97
gem5::Iris::ThreadContext::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.hh:406
gem5::Iris::ThreadContext::vecPredRegIds
ResourceIds vecPredRegIds
Definition: thread_context.hh:96
gem5::Iris::ThreadContext::timeEventStreamId
iris::EventStreamId timeEventStreamId
Definition: thread_context.hh:160
gem5::Iris::ThreadContext::semihostingEvent
iris::IrisErrorCode semihostingEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:289
gem5::Iris::ThreadContext::readMiscRegNoEffect
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
Definition: thread_context.cc:572
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:67
gem5::Iris::ThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val) override
Definition: thread_context.cc:651
gem5::Iris::ThreadContext::getWritableVecPredReg
ArmISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg) override
Definition: thread_context.hh:299
gem5::Iris::ThreadContext::scheduleInstCountEvent
void scheduleInstCountEvent(Event *event, Tick count) override
Definition: thread_context.cc:454
gem5::Iris::ThreadContext::bps
BpInfoMap bps
Definition: thread_context.hh:131
gem5::Iris::ThreadContext::flattenRegId
RegId flattenRegId(const RegId &regId) const override
Definition: thread_context.hh:366
gem5::Iris::ThreadContext::instanceRegistryChanged
iris::IrisErrorCode instanceRegistryChanged(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:194
gem5::Iris::ThreadContext::getCurrentInstCount
Tick getCurrentInstCount() override
Definition: thread_context.cc:472
gem5::Iris::ThreadContext::comInstEventQueue
EventQueue comInstEventQueue
Definition: thread_context.hh:105
gem5::Iris::ThreadContext::intReg32Ids
ResourceIds intReg32Ids
Definition: thread_context.hh:87
gem5::Iris::ThreadContext::setContextId
void setContextId(int id) override
Definition: thread_context.hh:195
gem5::Iris::ThreadContext::intReg64Ids
ResourceIds intReg64Ids
Definition: thread_context.hh:88
gem5::Iris::ThreadContext::initMemProxies
void initMemProxies(gem5::ThreadContext *tc) override
Initialise the physical and virtual port proxies and tie them to the data port of the CPU.
Definition: thread_context.cc:481
gem5::Iris::ThreadContext::ResourceMap
std::map< std::string, iris::ResourceInfo > ResourceMap
Definition: thread_context.hh:54
base.hh
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::Iris::ThreadContext::translateAddress
bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)
Definition: thread_context.cc:424
gem5::Iris::ThreadContext::BpInfo::validIds
bool validIds() const
Definition: thread_context.hh:123
gem5::Iris::ThreadContext::getBpSpaceIds
virtual const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const =0
gem5::BaseCPU::cpuId
int cpuId() const
Reads this CPU's ID.
Definition: base.hh:188
gem5::Iris::ThreadContext::setVecElem
void setVecElem(const RegId &reg, const ArmISA::VecElem &val) override
Definition: thread_context.hh:325
gem5::Iris::ThreadContext::BpInfo
Definition: thread_context.hh:113
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::Iris::ThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, const RegVal val) override
Definition: thread_context.hh:360
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::Iris::ThreadContext::semihostingEventStreamId
iris::EventStreamId semihostingEventStreamId
Definition: thread_context.hh:162
gem5::Iris::ThreadContext::_threadId
int _threadId
Definition: thread_context.hh:61
gem5::Iris::ThreadContext::readLastActivate
Tick readLastActivate() override
Definition: thread_context.hh:251
gem5::Iris::ThreadContext::socketId
uint32_t socketId() const override
Definition: thread_context.hh:189
gem5::Iris::ThreadContext::pcRscId
iris::ResourceId pcRscId
Definition: thread_context.hh:92
gem5::Iris::ThreadContext::BpInfo::empty
bool empty() const
Definition: thread_context.hh:122
gem5::Iris::ThreadContext::setStatus
void setStatus(Status new_status) override
Definition: thread_context.cc:507
gem5::Iris::ThreadContext::remove
bool remove(PCEvent *e) override
Definition: thread_context.cc:412
gem5::Iris::ThreadContext::status
Status status() const override
Definition: thread_context.cc:501
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::BaseISA
Definition: isa.hh:54
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
std::list
STL list class.
Definition: stl.hh:51
gem5::Iris::ThreadContext::setVecPredRegFlat
void setVecPredRegFlat(RegIndex idx, const ArmISA::VecPredRegContainer &val) override
Definition: thread_context.hh:443
gem5::Iris::ThreadContext::initEventStreamId
iris::EventStreamId initEventStreamId
Definition: thread_context.hh:159
gem5::Iris::ThreadContext::ResourceIds
std::vector< iris::ResourceId > ResourceIds
Definition: thread_context.hh:56
gem5::Iris::ThreadContext::BpInfo::pc
Addr pc
Definition: thread_context.hh:115
gem5::Iris::ThreadContext::regStats
void regStats(const std::string &name) override
Definition: thread_context.hh:246
gem5::Iris::ThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const override
Definition: thread_context.hh:278
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Iris::ThreadContext::_contextId
ContextID _contextId
Definition: thread_context.hh:62
gem5::Iris::ThreadContext::schedule
bool schedule(PCEvent *e) override
Definition: thread_context.cc:400
gem5::Iris::ThreadContext::BpInfo::BpInfo
BpInfo(Addr _pc)
Definition: thread_context.hh:120
gem5::Iris::ThreadContext::setVecPredReg
void setVecPredReg(const RegId &reg, const ArmISA::VecPredRegContainer &val) override
Definition: thread_context.hh:331
gem5::Iris::ThreadContext::client
iris::IrisInstance client
Definition: thread_context.hh:164
gem5::Iris::ThreadContext::_cpu
gem5::BaseCPU * _cpu
Definition: thread_context.hh:60
gem5::Iris::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const override
Definition: thread_context.cc:587
gem5::Iris::ThreadContext::setProcessPtr
void setProcessPtr(Process *p) override
Definition: thread_context.hh:229
gem5::Iris::ThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, uint64_t val) override
Definition: thread_context.cc:629
gem5::Iris::ThreadContext::getMMUPtr
BaseMMU * getMMUPtr() override
Definition: thread_context.hh:198
thread_context.hh
gem5::Iris::ThreadContext::getProcessPtr
Process * getProcessPtr() override
Definition: thread_context.hh:224
gem5::Iris::ThreadContext::readVecReg
const ArmISA::VecRegContainer & readVecReg(const RegId &reg) const override
Definition: thread_context.cc:660
gem5::Iris::ThreadContext::getCheckerCpuPtr
CheckerCPU * getCheckerCpuPtr() override
Definition: thread_context.hh:203
gem5::Iris::ThreadContext::instAddr
Addr instAddr() const override
Definition: thread_context.cc:560
gem5::Iris::ThreadContext::BpId
uint64_t BpId
Definition: thread_context.hh:112
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::Iris::ThreadContext::setVecElemFlat
void setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, const ArmISA::VecElem &val) override
Definition: thread_context.hh:429
gem5::Iris::ThreadContext::_instId
iris::InstanceId _instId
Definition: thread_context.hh:68

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