gem5  v22.0.0.2
thread_context.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
29 #define __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
30 
31 #include <list>
32 #include <map>
33 #include <memory>
34 #include <unordered_map>
35 
37 #include "arch/arm/regs/vec.hh"
38 #include "cpu/base.hh"
39 #include "cpu/thread_context.hh"
40 #include "iris/IrisInstance.h"
41 #include "iris/detail/IrisErrorCode.h"
42 #include "iris/detail/IrisObjects.h"
43 #include "sim/system.hh"
44 
45 namespace gem5
46 {
47 
48 namespace Iris
49 {
50 
51 // This class is the base for ThreadContexts which read and write state using
52 // the Iris API.
54 {
55  public:
56  typedef std::map<std::string, iris::ResourceInfo> ResourceMap;
57 
59  typedef std::map<int, std::string> IdxNameMap;
60 
61  typedef std::unordered_map<Iris::CanonicalMsn, iris::MemorySpaceId>
63 
64  protected:
65  gem5::BaseCPU *_cpu;
66  int _threadId;
71 
72  std::string _irisPath;
73  iris::InstanceId _instId = iris::IRIS_UINT64_MAX;
74 
75  // Temporary holding places for the vector reg accessors to return.
76  // These are not updated live, only when requested.
79 
82 
83  virtual void initFromIrisInstance(const ResourceMap &resources);
84 
85  iris::ResourceId extractResourceId(
86  const ResourceMap &resources, const std::string &name);
88  const ResourceMap &resources, const IdxNameMap &idx_names);
89  iris::MemorySpaceId getMemorySpaceId(const Iris::CanonicalMsn& msn) const;
90 
91 
97 
98  iris::ResourceId pcRscId = iris::IRIS_UINT64_MAX;
99  iris::ResourceId icountRscId;
100 
103 
107 
108  // A queue to keep track of instruction count based events.
110  // A helper function to maintain the IRIS step count. This makes sure the
111  // step count is correct even after IRIS resets it for us, and also handles
112  // events which are supposed to happen at the current instruction count.
113  void maintainStepping();
114 
115 
116  using BpId = uint64_t;
117  struct BpInfo
118  {
122  std::shared_ptr<EventList> events;
123 
124  BpInfo(Addr _pc) : pc(_pc), events(new EventList) {}
125 
126  bool empty() const { return events->empty(); }
127  bool validIds() const { return !ids.empty(); }
128  void clearIds() { ids.clear(); }
129  };
130 
131  using BpInfoPtr = std::unique_ptr<BpInfo>;
132  using BpInfoMap = std::map<Addr, BpInfoPtr>;
133  using BpInfoIt = BpInfoMap::iterator;
134 
136 
138 
139  void installBp(BpInfoIt it);
140  void uninstallBp(BpInfoIt it);
141  void delBp(BpInfoIt it);
142 
143  virtual const std::vector<iris::MemorySpaceId> &getBpSpaceIds() const = 0;
144 
145 
146  iris::IrisErrorCode instanceRegistryChanged(
147  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
148  uint64_t sInstId, bool syncEc, std::string &error_message_out);
149  iris::IrisErrorCode phaseInitLeave(
150  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
151  uint64_t sInstId, bool syncEc, std::string &error_message_out);
152  iris::IrisErrorCode simulationTimeEvent(
153  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
154  uint64_t sInstId, bool syncEc, std::string &error_message_out);
155  iris::IrisErrorCode breakpointHit(
156  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
157  uint64_t sInstId, bool syncEc, std::string &error_message_out);
158  iris::IrisErrorCode semihostingEvent(
159  uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
160  uint64_t sInstId, bool syncEc, std::string &error_message_out);
161 
162  iris::EventStreamId regEventStreamId;
163  iris::EventStreamId initEventStreamId;
164  iris::EventStreamId timeEventStreamId;
165  iris::EventStreamId breakpointEventStreamId;
166  iris::EventStreamId semihostingEventStreamId;
167 
168  mutable iris::IrisInstance client;
169  iris::IrisCppAdapter &call() const { return client.irisCall(); }
170  iris::IrisCppAdapter &noThrow() const { return client.irisCallNoThrow(); }
171 
173 
174  void readMem(iris::MemorySpaceId space,
175  Addr addr, void *p, size_t size);
176  void writeMem(iris::MemorySpaceId space,
177  Addr addr, const void *p, size_t size);
178  bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space,
179  Addr vaddr, iris::MemorySpaceId v_space);
180 
181  public:
182  ThreadContext(gem5::BaseCPU *cpu, int id, System *system,
183  gem5::BaseMMU *mmu, gem5::BaseISA *isa,
184  iris::IrisConnectionInterface *iris_if,
185  const std::string &iris_path);
186  virtual ~ThreadContext();
187 
188  virtual bool translateAddress(Addr &paddr, Addr vaddr) = 0;
189 
190  bool schedule(PCEvent *e) override;
191  bool remove(PCEvent *e) override;
192 
193  void scheduleInstCountEvent(Event *event, Tick count) override;
194  void descheduleInstCountEvent(Event *event) override;
195  Tick getCurrentInstCount() override;
196 
197  gem5::BaseCPU *getCpuPtr() override { return _cpu; }
198  int cpuId() const override { return _cpu->cpuId(); }
199  uint32_t socketId() const override { return _cpu->socketId(); }
200 
201  int threadId() const override { return _threadId; }
202  void setThreadId(int id) override { _threadId = id; }
203 
204  int contextId() const override { return _contextId; }
205  void setContextId(int id) override { _contextId = id; }
206 
207  BaseMMU *
208  getMMUPtr() override
209  {
210  return _mmu;
211  }
212 
213  CheckerCPU *getCheckerCpuPtr() override { return nullptr; }
214  InstDecoder *
215  getDecoderPtr() override
216  {
217  panic("%s not implemented.", __FUNCTION__);
218  }
219 
220  System *getSystemPtr() override { return _cpu->system; }
221 
222  BaseISA *
223  getIsaPtr() const override
224  {
225  return _isa;
226  }
227 
228  void sendFunctional(PacketPtr pkt) override;
229 
230  Process *
231  getProcessPtr() override
232  {
233  panic("%s not implemented.", __FUNCTION__);
234  }
235  void
237  {
238  panic("%s not implemented.", __FUNCTION__);
239  }
240 
241  Status status() const override;
242  void setStatus(Status new_status) override;
243  void activate() override { setStatus(Active); }
244  void suspend() override { setStatus(Suspended); }
245  void halt() override { setStatus(Halted); }
246 
247  void
248  takeOverFrom(gem5::ThreadContext *old_context) override
249  {
250  panic("%s not implemented.", __FUNCTION__);
251  }
252 
253  void regStats(const std::string &name) override {}
254 
255  // Not necessarily the best location for these...
256  // Having an extra function just to read these is obnoxious
257  Tick
258  readLastActivate() override
259  {
260  panic("%s not implemented.", __FUNCTION__);
261  }
263  {
264  panic("%s not implemented.", __FUNCTION__);
265  }
266 
267  void
269  {
270  panic("%s not implemented.", __FUNCTION__);
271  }
272 
273  void
274  clearArchRegs() override
275  {
276  warn("Ignoring clearArchRegs()");
277  }
278 
279  //
280  // New accessors for new decoder.
281  //
282  RegVal getReg(const RegId &reg) const override;
283  void getReg(const RegId &reg, void *val) const override;
284  void *getWritableReg(const RegId &reg) override;
285 
286  void setReg(const RegId &reg, RegVal val) override;
287  void setReg(const RegId &reg, const void *val) override;
288 
289  virtual RegVal readIntReg(RegIndex reg_idx) const;
290 
291  virtual const ArmISA::VecRegContainer &readVecReg(const RegId &reg) const;
292  virtual ArmISA::VecRegContainer &
294  {
295  panic("%s not implemented.", __FUNCTION__);
296  }
297 
298  virtual RegVal
299  readVecElem(const RegId &reg) const
300  {
301  panic("%s not implemented.", __FUNCTION__);
302  }
303 
304  virtual const ArmISA::VecPredRegContainer &
305  readVecPredReg(const RegId &reg) const;
308  {
309  panic("%s not implemented.", __FUNCTION__);
310  }
311 
312  virtual RegVal
313  readCCReg(RegIndex reg_idx) const
314  {
315  return readCCRegFlat(reg_idx);
316  }
317 
318  virtual void setIntReg(RegIndex reg_idx, RegVal val);
319 
320  virtual void
322  {
323  panic("%s not implemented.", __FUNCTION__);
324  }
325 
326  virtual void
328  {
329  panic("%s not implemented.", __FUNCTION__);
330  }
331 
332  virtual void
335  {
336  panic("%s not implemented.", __FUNCTION__);
337  }
338 
339  virtual void
341  {
342  setCCRegFlat(reg_idx, val);
343  }
344 
345  void pcStateNoRecord(const PCStateBase &val) override { pcState(val); }
346 
347  const PCStateBase &pcState() const override;
348  void pcState(const PCStateBase &val) override;
349 
350  RegVal readMiscRegNoEffect(RegIndex misc_reg) const override;
351  RegVal
352  readMiscReg(RegIndex misc_reg) override
353  {
354  return readMiscRegNoEffect(misc_reg);
355  }
356 
357  void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override;
358  void
359  setMiscReg(RegIndex misc_reg, const RegVal val) override
360  {
361  setMiscRegNoEffect(misc_reg, val);
362  }
363 
364  RegId
365  flattenRegId(const RegId& regId) const override
366  {
367  panic("%s not implemented.", __FUNCTION__);
368  }
369 
370  // Also not necessarily the best location for these two. Hopefully will go
371  // away once we decide upon where st cond failures goes.
372  unsigned
373  readStCondFailures() const override
374  {
375  panic("%s not implemented.", __FUNCTION__);
376  }
377 
378  void
379  setStCondFailures(unsigned sc_failures) override
380  {
381  panic("%s not implemented.", __FUNCTION__);
382  }
383 
396  RegVal getRegFlat(const RegId &reg) const override;
397  void getRegFlat(const RegId &reg, void *val) const override;
398  void *getWritableRegFlat(const RegId &reg) override;
399 
400  void setRegFlat(const RegId &reg, RegVal val) override;
401  void setRegFlat(const RegId &reg, const void *val) override;
402 
403  virtual RegVal readIntRegFlat(RegIndex idx) const;
404  virtual void setIntRegFlat(RegIndex idx, uint64_t val);
405 
406  virtual const ArmISA::VecRegContainer &readVecRegFlat(RegIndex idx) const;
407  virtual ArmISA::VecRegContainer &
409  {
410  panic("%s not implemented.", __FUNCTION__);
411  }
412  virtual void
414  {
415  panic("%s not implemented.", __FUNCTION__);
416  }
417 
418  virtual RegVal
420  {
421  panic("%s not implemented.", __FUNCTION__);
422  }
423  virtual void
425  {
426  panic("%s not implemented.", __FUNCTION__);
427  }
428 
432  {
433  panic("%s not implemented.", __FUNCTION__);
434  }
435  virtual void
438  {
439  panic("%s not implemented.", __FUNCTION__);
440  }
441 
442  virtual RegVal readCCRegFlat(RegIndex idx) const;
443  virtual void setCCRegFlat(RegIndex idx, RegVal val);
446  // hardware transactional memory
447  void
448  htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
449  {
450  panic("%s not implemented.", __FUNCTION__);
451  }
452 
455  {
456  panic("%s not implemented.", __FUNCTION__);
457  }
458 
459  void
461  {
462  panic("%s not implemented.", __FUNCTION__);
463  }
464 };
465 
466 } // namespace Iris
467 } // namespace gem5
468 
469 #endif // __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
gem5::Iris::ThreadContext::readLastSuspend
Tick readLastSuspend() override
Definition: thread_context.hh:262
gem5::Iris::ThreadContext::IdxNameMap
std::map< int, std::string > IdxNameMap
Definition: thread_context.hh:59
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:109
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::Iris::ThreadContext::getSystemPtr
System * getSystemPtr() override
Definition: thread_context.hh:220
warn
#define warn(...)
Definition: logging.hh:246
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
system.hh
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::Iris::ThreadContext::BpInfo::ids
std::vector< BpId > ids
Definition: thread_context.hh:120
gem5::Iris::ThreadContext::readVecRegFlat
virtual const ArmISA::VecRegContainer & readVecRegFlat(RegIndex idx) const
Definition: thread_context.cc:879
memory_spaces.hh
gem5::Iris::ThreadContext::pcStateNoRecord
void pcStateNoRecord(const PCStateBase &val) override
Definition: thread_context.hh:345
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::Iris::ThreadContext::vecRegIds
ResourceIds vecRegIds
Definition: thread_context.hh:101
gem5::Iris::ThreadContext::pc
ArmISA::PCState pc
Definition: thread_context.hh:172
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::Iris::ThreadContext::takeOverFrom
void takeOverFrom(gem5::ThreadContext *old_context) override
Definition: thread_context.hh:248
gem5::Iris::ThreadContext::readMiscReg
RegVal readMiscReg(RegIndex misc_reg) override
Definition: thread_context.hh:352
gem5::Iris::ThreadContext::BpInfo::events
std::shared_ptr< EventList > events
Definition: thread_context.hh:122
gem5::Iris::ThreadContext::regEventStreamId
iris::EventStreamId regEventStreamId
Definition: thread_context.hh:162
gem5::Iris::ThreadContext::readVecPredReg
virtual const ArmISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const
Definition: thread_context.cc:885
gem5::Iris::ThreadContext::_isa
gem5::BaseISA * _isa
Definition: thread_context.hh:70
gem5::Iris::ThreadContext::getWritableRegFlat
void * getWritableRegFlat(const RegId &reg) override
Definition: thread_context.cc:769
gem5::Iris::ThreadContext::setReg
void setReg(const RegId &reg, RegVal val) override
Definition: thread_context.cc:617
gem5::Iris::ThreadContext::setRegFlat
void setRegFlat(const RegId &reg, RegVal val) override
Definition: thread_context.cc:707
gem5::Iris::ThreadContext::pcState
const PCStateBase & pcState() const override
Definition: thread_context.cc:557
gem5::Iris::ThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.hh:245
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::Iris::ThreadContext::setCCRegFlat
virtual void setCCRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.cc:848
gem5::Iris::ThreadContext::threadId
int threadId() const override
Definition: thread_context.hh:201
gem5::Iris::ThreadContext::call
iris::IrisCppAdapter & call() const
Definition: thread_context.hh:169
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:105
gem5::Iris::ThreadContext::BpInfoMap
std::map< Addr, BpInfoPtr > BpInfoMap
Definition: thread_context.hh:132
gem5::Iris::ThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.hh:448
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
vec.hh
std::vector< iris::ResourceId >
gem5::Iris::ThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.hh:243
gem5::ArmISA::ids
Bitfield< 39, 36 > ids
Definition: misc_types.hh:154
gem5::Iris::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.cc:784
gem5::Iris::ThreadContext::breakpointHit
iris::IrisErrorCode breakpointHit(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:284
gem5::Iris::ThreadContext::sendFunctional
void sendFunctional(PacketPtr pkt) override
Definition: thread_context.cc:518
gem5::Iris::ThreadContext::descheduleInstCountEvent
void descheduleInstCountEvent(Event *event) override
Definition: thread_context.cc:502
gem5::Iris::ThreadContext::installBp
void installBp(BpInfoIt it)
Definition: thread_context.cc:178
gem5::Iris::ThreadContext::_mmu
gem5::BaseMMU * _mmu
Definition: thread_context.hh:69
gem5::Iris::ThreadContext::BpInfo::clearIds
void clearIds()
Definition: thread_context.hh:128
gem5::Iris::ThreadContext::initFromIrisInstance
virtual void initFromIrisInstance(const ResourceMap &resources)
Definition: thread_context.cc:65
gem5::Iris::ThreadContext::icountRscId
iris::ResourceId icountRscId
Definition: thread_context.hh:99
gem5::Iris::ThreadContext::getOrAllocBp
BpInfoIt getOrAllocBp(Addr pc)
Definition: thread_context.cc:165
gem5::Iris::ThreadContext::uninstallBp
void uninstallBp(BpInfoIt it)
Definition: thread_context.cc:190
gem5::Iris::ThreadContext::getCpuPtr
gem5::BaseCPU * getCpuPtr() override
Definition: thread_context.hh:197
gem5::Iris::ThreadContext::maintainStepping
void maintainStepping()
Definition: thread_context.cc:136
gem5::Iris::ThreadContext::setVecPredRegFlat
virtual void setVecPredRegFlat(RegIndex idx, const ArmISA::VecPredRegContainer &val)
Definition: thread_context.hh:436
gem5::Iris::ThreadContext::enableAfterPseudoEvent
Event * enableAfterPseudoEvent
Definition: thread_context.hh:81
gem5::Iris::ThreadContext::breakpointEventStreamId
iris::EventStreamId breakpointEventStreamId
Definition: thread_context.hh:165
gem5::Iris::ThreadContext::memorySpaces
std::vector< iris::MemorySpaceInfo > memorySpaces
Definition: thread_context.hh:104
gem5::BaseMMU
Definition: mmu.hh:53
gem5::Iris::ThreadContext::_status
Status _status
Definition: thread_context.hh:80
gem5::Iris::ThreadContext::vecPredRegs
std::vector< ArmISA::VecPredRegContainer > vecPredRegs
Definition: thread_context.hh:78
gem5::Iris::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.hh:244
gem5::Iris::ThreadContext::getWritableVecReg
virtual ArmISA::VecRegContainer & getWritableVecReg(const RegId &reg)
Definition: thread_context.hh:293
gem5::Iris::ThreadContext::memorySpaceIds
MemorySpaceMap memorySpaceIds
Definition: thread_context.hh:106
gem5::Iris::ThreadContext::noThrow
iris::IrisCppAdapter & noThrow() const
Definition: thread_context.hh:170
gem5::Iris::ThreadContext::MemorySpaceMap
std::unordered_map< Iris::CanonicalMsn, iris::MemorySpaceId > MemorySpaceMap
Definition: thread_context.hh:62
gem5::Iris::ThreadContext::setVecRegFlat
virtual void setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val)
Definition: thread_context.hh:413
gem5::Iris::ThreadContext::simulationTimeEvent
iris::IrisErrorCode simulationTimeEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Definition: thread_context.cc:262
gem5::Iris::ThreadContext::readCCRegFlat
virtual RegVal readCCRegFlat(RegIndex idx) const
Definition: thread_context.cc:838
gem5::Iris::ThreadContext::setVecElemFlat
virtual void setVecElemFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:424
gem5::System
Definition: system.hh:75
gem5::VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:123
gem5::Iris::ThreadContext::copyArchRegs
void copyArchRegs(gem5::ThreadContext *tc) override
Definition: thread_context.hh:268
gem5::Iris::ThreadContext::getDecoderPtr
InstDecoder * getDecoderPtr() override
Definition: thread_context.hh:215
gem5::Iris::ThreadContext::setThreadId
void setThreadId(int id) override
Definition: thread_context.hh:202
gem5::Iris::ThreadContext::getReg
RegVal getReg(const RegId &reg) const override
Definition: thread_context.cc:609
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Iris::ThreadContext::cpuId
int cpuId() const override
Definition: thread_context.hh:198
gem5::Iris::ThreadContext::~ThreadContext
virtual ~ThreadContext()
Definition: thread_context.cc:393
gem5::InstDecoder
Definition: decoder.hh:42
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
gem5::Event
Definition: eventq.hh:251
gem5::Iris::ThreadContext::BpInfoIt
BpInfoMap::iterator BpInfoIt
Definition: thread_context.hh:133
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Iris::ThreadContext::_irisPath
std::string _irisPath
Definition: thread_context.hh:72
gem5::Iris::ThreadContext::readMem
void readMem(iris::MemorySpaceId space, Addr addr, void *p, size_t size)
Definition: thread_context.cc:440
gem5::Iris::ThreadContext::miscRegIds
ResourceIds miscRegIds
Definition: thread_context.hh:92
gem5::Iris::ThreadContext
Definition: thread_context.hh:53
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Iris::ThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.hh:454
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Iris::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override
Definition: thread_context.cc:602
gem5::PCEvent
Definition: pc_event.hh:45
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::Iris::ThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) override
Definition: thread_context.hh:460
gem5::Iris::ThreadContext::ThreadContext
ThreadContext(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
Definition: thread_context.cc:326
gem5::Iris::ThreadContext::BpInfoPtr
std::unique_ptr< BpInfo > BpInfoPtr
Definition: thread_context.hh:131
gem5::Iris::ThreadContext::phaseInitLeave
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Definition: thread_context.cc:232
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Definition: eventq.hh:622
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Definition: thread_context.hh:68
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Definition: thread_context.hh:274
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Definition: thread_context.hh:105
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Definition: thread_context.cc:113
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Definition: thread_context.hh:96
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Definition: thread_context.cc:857
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Definition: thread_context.hh:204
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Definition: thread_context.hh:379
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Definition: thread_context.hh:373
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Definition: thread_context.hh:95
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Definition: thread_context.cc:826
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Definition: thread_context.cc:813
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Definition: types.hh:147
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Definition: thread_context.cc:198
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Definition: thread_context.hh:77
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Definition: trace.cc:49
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Definition: thread_context.cc:106
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Definition: thread_context.hh:431
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Definition: thread_context.hh:102
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Definition: thread_context.hh:164
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Definition: thread_context.hh:365
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Definition: thread_context.hh:340
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Definition: thread_context.hh:93
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Definition: thread_context.hh:94
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Definition: thread_context.hh:56
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Definition: thread_context.cc:461
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Definition: thread_context.hh:307
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Definition: thread_context.hh:127
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Definition: thread_context.hh:299
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Definition: thread_context.hh:313
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Definition: thread_context.hh:223
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Definition: thread_context.hh:117
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Definition: types.hh:239
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Definition: thread_context.hh:359
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Definition: thread_context.cc:797
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Definition: misc_types.hh:251
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Definition: thread_context.hh:166
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Definition: thread_context.hh:66
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Definition: thread_context.hh:258
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Definition: thread_context.hh:199
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Definition: thread_context.hh:98
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Definition: thread_context.cc:129
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Definition: thread_context.hh:126
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Definition: thread_context.cc:542
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Definition: thread_context.cc:428
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Definition: thread_context.cc:536
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Definition: pra_constants.hh:278
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Definition: pcstate.hh:57
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Definition: thread_context.hh:327
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Definition: isa.hh:57
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Definition: types.hh:176
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Definition: stl.hh:51
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Definition: thread_context.hh:163
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Definition: thread_context.hh:58
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Definition: thread_context.hh:119
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Definition: thread_context.hh:253
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Definition: thread_context.cc:699
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Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
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Definition: thread_context.hh:67
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Definition: thread_context.cc:416
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Definition: thread_context.hh:124
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Definition: thread_context.hh:168
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Definition: thread_context.hh:65
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Definition: thread_context.hh:236
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Definition: thread_context.hh:408
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Definition: memory_spaces.hh:37
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Definition: thread_context.hh:208
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Definition: thread_context.hh:419
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Definition: thread_context.hh:231
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Definition: thread_context.hh:116
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Definition: thread_context.hh:321
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Definition: reg_class.hh:126
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Definition: thread_context.cc:450
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Definition: logging.hh:178
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Definition: thread_context.hh:73
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Definition: types.hh:84
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Definition: thread_context.hh:333

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