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28 #ifndef __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
29 #define __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
34 #include <unordered_map>
40 #include "iris/IrisInstance.h"
41 #include "iris/detail/IrisErrorCode.h"
42 #include "iris/detail/IrisObjects.h"
56 typedef std::map<std::string, iris::ResourceInfo>
ResourceMap;
61 typedef std::unordered_map<Iris::CanonicalMsn, iris::MemorySpaceId>
73 iris::InstanceId
_instId = iris::IRIS_UINT64_MAX;
98 iris::ResourceId
pcRscId = iris::IRIS_UINT64_MAX;
147 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
148 uint64_t sInstId,
bool syncEc, std::string &error_message_out);
150 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
151 uint64_t sInstId,
bool syncEc, std::string &error_message_out);
153 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
154 uint64_t sInstId,
bool syncEc, std::string &error_message_out);
156 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
157 uint64_t sInstId,
bool syncEc, std::string &error_message_out);
159 uint64_t esId,
const iris::IrisValueMap &fields, uint64_t time,
160 uint64_t sInstId,
bool syncEc, std::string &error_message_out);
169 iris::IrisCppAdapter &
call()
const {
return client.irisCall(); }
174 void readMem(iris::MemorySpaceId space,
176 void writeMem(iris::MemorySpaceId space,
179 Addr vaddr, iris::MemorySpaceId v_space);
184 iris::IrisConnectionInterface *iris_if,
185 const std::string &iris_path);
217 panic(
"%s not implemented.", __FUNCTION__);
233 panic(
"%s not implemented.", __FUNCTION__);
238 panic(
"%s not implemented.", __FUNCTION__);
250 panic(
"%s not implemented.", __FUNCTION__);
260 panic(
"%s not implemented.", __FUNCTION__);
264 panic(
"%s not implemented.", __FUNCTION__);
270 panic(
"%s not implemented.", __FUNCTION__);
276 warn(
"Ignoring clearArchRegs()");
287 panic(
"%s not implemented.", __FUNCTION__);
294 panic(
"%s not implemented.", __FUNCTION__);
300 panic(
"%s not implemented.", __FUNCTION__);
308 panic(
"%s not implemented.", __FUNCTION__);
322 panic(
"%s not implemented.", __FUNCTION__);
328 panic(
"%s not implemented.", __FUNCTION__);
334 panic(
"%s not implemented.", __FUNCTION__);
341 panic(
"%s not implemented.", __FUNCTION__);
372 panic(
"%s not implemented.", __FUNCTION__);
380 panic(
"%s not implemented.", __FUNCTION__);
386 panic(
"%s not implemented.", __FUNCTION__);
407 panic(
"%s not implemented.", __FUNCTION__);
412 panic(
"%s not implemented.", __FUNCTION__);
419 panic(
"%s not implemented.", __FUNCTION__);
424 panic(
"%s not implemented.", __FUNCTION__);
430 panic(
"%s not implemented.", __FUNCTION__);
435 panic(
"%s not implemented.", __FUNCTION__);
443 panic(
"%s not implemented.", __FUNCTION__);
449 panic(
"%s not implemented.", __FUNCTION__);
460 panic(
"%s not implemented.", __FUNCTION__);
466 panic(
"%s not implemented.", __FUNCTION__);
472 panic(
"%s not implemented.", __FUNCTION__);
479 #endif // __ARCH_ARM_FASTMODEL_IRIS_THREAD_CONTEXT_HH__
Tick readLastSuspend() override
std::map< int, std::string > IdxNameMap
void setVecReg(const RegId ®, const ArmISA::VecRegContainer &val) override
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
System * getSystemPtr() override
RegVal readIntRegFlat(RegIndex idx) const override
Flat register interfaces.
VecPredReg::Container VecPredRegContainer
void pcStateNoRecord(const PCStateBase &val) override
@ Halted
Permanently shut down.
const ArmISA::VecPredRegContainer & readVecPredReg(const RegId ®) const override
void takeOverFrom(gem5::ThreadContext *old_context) override
RegVal readMiscReg(RegIndex misc_reg) override
std::shared_ptr< EventList > events
iris::EventStreamId regEventStreamId
const PCStateBase & pcState() const override
void halt() override
Set the status to Halted.
int threadId() const override
iris::IrisCppAdapter & call() const
BaseISA * getIsaPtr() override
void setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val) override
std::map< Addr, BpInfoPtr > BpInfoMap
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
void setIntReg(RegIndex reg_idx, RegVal val) override
ArmISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx) override
void activate() override
Set the status to Active.
iris::IrisErrorCode breakpointHit(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
void sendFunctional(PacketPtr pkt) override
void descheduleInstCountEvent(Event *event) override
void installBp(BpInfoIt it)
virtual void initFromIrisInstance(const ResourceMap &resources)
iris::ResourceId icountRscId
BpInfoIt getOrAllocBp(Addr pc)
void uninstallBp(BpInfoIt it)
gem5::BaseCPU * getCpuPtr() override
Event * enableAfterPseudoEvent
iris::EventStreamId breakpointEventStreamId
std::vector< iris::MemorySpaceInfo > memorySpaces
std::vector< ArmISA::VecPredRegContainer > vecPredRegs
void suspend() override
Set the status to Suspended.
MemorySpaceMap memorySpaceIds
iris::IrisCppAdapter & noThrow() const
std::unordered_map< Iris::CanonicalMsn, iris::MemorySpaceId > MemorySpaceMap
iris::IrisErrorCode simulationTimeEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
ArmISA::VecRegContainer & getWritableVecReg(const RegId ®) override
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
void copyArchRegs(gem5::ThreadContext *tc) override
InstDecoder * getDecoderPtr() override
void setThreadId(int id) override
ThreadContext is the external interface to all thread state for anything outside of the CPU.
RegVal readCCReg(RegIndex reg_idx) const override
int cpuId() const override
@ Suspended
Temporarily inactive.
void setCCReg(RegIndex reg_idx, RegVal val) override
BpInfoMap::iterator BpInfoIt
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
void readMem(iris::MemorySpaceId space, Addr addr, void *p, size_t size)
GenericISA::DelaySlotPCState< 4 > PCState
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
uint64_t Tick
Tick count type.
void setMiscRegNoEffect(RegIndex misc_reg, const RegVal val) override
void setFloatReg(RegIndex reg_idx, RegVal val) override
void setVecElemFlat(RegIndex idx, const ElemIndex &elemIdx, RegVal val) override
void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) override
RegVal readCCRegFlat(RegIndex idx) const override
ThreadContext(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
const ArmISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const override
std::unique_ptr< BpInfo > BpInfoPtr
iris::IrisErrorCode phaseInitLeave(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Queue of events sorted in time order.
ArmISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx) override
const ArmISA::VecRegContainer & readVecRegFlat(RegIndex idx) const override
void clearArchRegs() override
std::vector< iris::MemorySupportedAddressTranslationResult > translations
void extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
int contextId() const override
void setStCondFailures(unsigned sc_failures) override
unsigned readStCondFailures() const override
ResourceIds flattenedIntIds
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
std::vector< ArmISA::VecRegContainer > vecRegs
RegVal readFloatRegFlat(RegIndex idx) const override
uint16_t ElemIndex
Logical vector register elem index type.
const std::string & name()
iris::ResourceId extractResourceId(const ResourceMap &resources, const std::string &name)
void setFloatRegFlat(RegIndex idx, RegVal val) override
ResourceIds vecPredRegIds
iris::EventStreamId timeEventStreamId
iris::IrisErrorCode semihostingEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override
void setCCRegFlat(RegIndex idx, RegVal val) override
ArmISA::VecPredRegContainer & getWritableVecPredReg(const RegId ®) override
void scheduleInstCountEvent(Event *event, Tick count) override
RegId flattenRegId(const RegId ®Id) const override
iris::IrisErrorCode instanceRegistryChanged(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
Tick getCurrentInstCount() override
EventQueue comInstEventQueue
void setContextId(int id) override
std::map< std::string, iris::ResourceInfo > ResourceMap
bool translateAddress(Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)
virtual const std::vector< iris::MemorySpaceId > & getBpSpaceIds() const =0
void setVecElem(const RegId ®, RegVal val) override
int ContextID
Globally unique thread context ID.
void setMiscReg(RegIndex misc_reg, const RegVal val) override
RegVal readVecElemFlat(RegIndex idx, const ElemIndex &elemIdx) const override
iris::EventStreamId semihostingEventStreamId
RegVal readVecElem(const RegId ®) const override
Tick readLastActivate() override
uint32_t socketId() const override
iris::MemorySpaceId getMemorySpaceId(const Iris::CanonicalMsn &msn) const
void setStatus(Status new_status) override
bool remove(PCEvent *e) override
Status status() const override
void setVecPredRegFlat(RegIndex idx, const ArmISA::VecPredRegContainer &val) override
iris::EventStreamId initEventStreamId
std::vector< iris::ResourceId > ResourceIds
void regStats(const std::string &name) override
RegVal readFloatReg(RegIndex reg_idx) const override
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
bool schedule(PCEvent *e) override
void setVecPredReg(const RegId ®, const ArmISA::VecPredRegContainer &val) override
iris::IrisInstance client
RegVal readIntReg(RegIndex reg_idx) const override
void setProcessPtr(Process *p) override
void setIntRegFlat(RegIndex idx, uint64_t val) override
BaseMMU * getMMUPtr() override
Process * getProcessPtr() override
const ArmISA::VecRegContainer & readVecReg(const RegId ®) const override
CheckerCPU * getCheckerCpuPtr() override
Register ID: describe an architectural register with its class and index.
void writeMem(iris::MemorySpaceId space, Addr addr, const void *p, size_t size)
#define panic(...)
This implements a cprintf based panic() function.
Generated on Wed May 4 2022 12:13:46 for gem5 by doxygen 1.8.17