gem5  v21.2.1.1
isa.hh
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39 
40 #ifndef __ARCH_GENERIC_ISA_HH__
41 #define __ARCH_GENERIC_ISA_HH__
42 
43 #include <vector>
44 
45 #include "arch/generic/pcstate.hh"
46 #include "cpu/reg_class.hh"
47 #include "mem/packet.hh"
48 #include "mem/request.hh"
49 #include "sim/sim_object.hh"
50 
51 namespace gem5
52 {
53 
54 class ThreadContext;
55 class ExecContext;
56 
57 class BaseISA : public SimObject
58 {
59  public:
61 
62  protected:
64 
65  ThreadContext *tc = nullptr;
66 
68 
69  public:
70  virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
71  virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) {}
72  virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
73 
74  virtual uint64_t getExecutingAsid() const { return 0; }
75  virtual bool inUserMode() const = 0;
76  virtual void copyRegsFrom(ThreadContext *src) = 0;
77 
78  const RegClasses &regClasses() const { return _regClasses; }
79 
80  // Locked memory handling functions.
81  virtual void handleLockedRead(const RequestPtr &req) {}
82  virtual void
84  {
85  handleLockedRead(req);
86  }
87  virtual bool
88  handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
89  {
90  return true;
91  }
92  virtual bool
94  Addr cacheBlockMask)
95  {
96  return handleLockedWrite(req, cacheBlockMask);
97  }
98 
99  virtual void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) {}
100  virtual void
101  handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)
102  {
103  handleLockedSnoop(pkt, cacheBlockMask);
104  }
105  virtual void handleLockedSnoopHit() {}
106  virtual void
108  {
110  }
111 
112  virtual void globalClearExclusive() {}
113  virtual void
115  {
117  }
118 };
119 
120 } // namespace gem5
121 
122 #endif // __ARCH_GENERIC_ISA_HH__
gem5::BaseISA::handleLockedRead
virtual void handleLockedRead(const RequestPtr &req)
Definition: isa.hh:81
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:65
gem5::BaseISA::copyRegsFrom
virtual void copyRegsFrom(ThreadContext *src)=0
gem5::BaseISA::getExecutingAsid
virtual uint64_t getExecutingAsid() const
Definition: isa.hh:74
gem5::BaseISA::globalClearExclusive
virtual void globalClearExclusive(ExecContext *xc)
Definition: isa.hh:114
gem5::BaseISA::handleLockedWrite
virtual bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
Definition: isa.hh:88
gem5::BaseISA::handleLockedSnoop
virtual void handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)
Definition: isa.hh:101
std::vector< RegClass >
gem5::BaseISA::handleLockedWrite
virtual bool handleLockedWrite(ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask)
Definition: isa.hh:93
gem5::BaseISA::inUserMode
virtual bool inUserMode() const =0
gem5::BaseISA::takeOverFrom
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition: isa.hh:71
request.hh
packet.hh
gem5::BaseISA::RegClasses
std::vector< RegClass > RegClasses
Definition: isa.hh:60
gem5::BaseISA::handleLockedSnoop
virtual void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
Definition: isa.hh:99
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:67
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::BaseISA::newPCState
virtual PCStateBase * newPCState(Addr new_inst_addr=0) const =0
sim_object.hh
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::BaseISA::setThreadContext
virtual void setThreadContext(ThreadContext *_tc)
Definition: isa.hh:72
gem5::BaseISA::regClasses
const RegClasses & regClasses() const
Definition: isa.hh:78
gem5::BaseISA::handleLockedRead
virtual void handleLockedRead(ExecContext *xc, const RequestPtr &req)
Definition: isa.hh:83
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::BaseISA::handleLockedSnoopHit
virtual void handleLockedSnoopHit(ExecContext *xc)
Definition: isa.hh:107
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
pcstate.hh
gem5::SimObject::SimObject
SimObject(const Params &p)
Definition: sim_object.cc:58
gem5::BaseISA::globalClearExclusive
virtual void globalClearExclusive()
Definition: isa.hh:112
reg_class.hh
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::BaseISA
Definition: isa.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::BaseISA::handleLockedSnoopHit
virtual void handleLockedSnoopHit()
Definition: isa.hh:105

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