gem5  v21.1.0.2
isa.hh
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39 
40 #ifndef __ARCH_GENERIC_ISA_HH__
41 #define __ARCH_GENERIC_ISA_HH__
42 
43 #include <vector>
44 
45 #include "cpu/reg_class.hh"
46 #include "enums/VecRegRenameMode.hh"
47 #include "sim/sim_object.hh"
48 
49 namespace gem5
50 {
51 
52 class ThreadContext;
53 
54 class BaseISA : public SimObject
55 {
56  public:
58 
59  protected:
61 
62  ThreadContext *tc = nullptr;
63 
65 
66  public:
67  virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) {}
68  virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
69 
70  virtual uint64_t getExecutingAsid() const { return 0; }
71  virtual bool inUserMode() const = 0;
72  virtual void copyRegsFrom(ThreadContext *src) = 0;
73 
74  virtual enums::VecRegRenameMode
76  {
77  return enums::Full;
78  }
79 
80  virtual enums::VecRegRenameMode
82  {
83  return initVecRegRenameMode();
84  }
85 
86  const RegClasses &regClasses() const { return _regClasses; }
87 };
88 
89 } // namespace gem5
90 
91 #endif // __ARCH_GENERIC_ISA_HH__
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:62
gem5::BaseISA::copyRegsFrom
virtual void copyRegsFrom(ThreadContext *src)=0
gem5::BaseISA::getExecutingAsid
virtual uint64_t getExecutingAsid() const
Definition: isa.hh:70
std::vector< RegClassInfo >
gem5::BaseISA::inUserMode
virtual bool inUserMode() const =0
gem5::BaseISA::takeOverFrom
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition: isa.hh:67
gem5::BaseISA::initVecRegRenameMode
virtual enums::VecRegRenameMode initVecRegRenameMode() const
Definition: isa.hh:75
gem5::BaseISA::_regClasses
RegClasses _regClasses
Definition: isa.hh:64
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
sim_object.hh
gem5::BaseISA::setThreadContext
virtual void setThreadContext(ThreadContext *_tc)
Definition: isa.hh:68
gem5::BaseISA::regClasses
const RegClasses & regClasses() const
Definition: isa.hh:86
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::BaseISA::vecRegRenameMode
virtual enums::VecRegRenameMode vecRegRenameMode(ThreadContext *_tc) const
Definition: isa.hh:81
gem5::BaseISA::RegClasses
std::vector< RegClassInfo > RegClasses
Definition: isa.hh:57
gem5::SimObject::SimObject
SimObject(const Params &p)
Definition: sim_object.cc:58
reg_class.hh
gem5::BaseISA
Definition: isa.hh:54
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

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