gem5 v24.0.0.0
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isa.hh
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1/*
2 * Copyright (c) 2020, 2024 Arm Limited
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4 *
5 * The license below extends only to copyright in the software and shall
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13 *
14 * Copyright 2020 Google Inc.
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18 * met: redistributions of source code must retain the above copyright
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25 * this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38 */
39
40#ifndef __ARCH_GENERIC_ISA_HH__
41#define __ARCH_GENERIC_ISA_HH__
42
43#include <vector>
44
46#include "base/logging.hh"
47#include "cpu/reg_class.hh"
48#include "mem/packet.hh"
49#include "mem/request.hh"
50#include "sim/sim_object.hh"
51
52namespace gem5
53{
54
55class ThreadContext;
56class ExecContext;
57
58class BaseISA : public SimObject
59{
60 public:
62
63 protected:
64 BaseISA(const SimObjectParams &p, const std::string &name)
66 {}
67
68 ThreadContext *tc = nullptr;
69
71
72 std::string isaName;
73
74 public:
75 virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
76 virtual void clear() {}
77
78 virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
79 virtual RegVal readMiscReg(RegIndex idx) = 0;
80
81 virtual void setMiscRegNoEffect(RegIndex idx, RegVal val) = 0;
82 virtual void setMiscReg(RegIndex idx, RegVal val) = 0;
83
84 virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) {}
85 virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
86
87 virtual uint64_t getExecutingAsid() const { return 0; }
88 virtual bool inUserMode() const = 0;
89 virtual void copyRegsFrom(ThreadContext *src) = 0;
90
91 virtual void resetThread() { panic("Thread reset not implemented."); }
92
93 const RegClasses &regClasses() const { return _regClasses; }
94 const std::string getIsaName() const { return isaName; }
95
96 // Locked memory handling functions.
97 virtual void handleLockedRead(const RequestPtr &req) {}
98 virtual void
100 {
101 handleLockedRead(req);
102 }
103 virtual bool
104 handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
105 {
106 return true;
107 }
108 virtual bool
110 Addr cacheBlockMask)
111 {
112 return handleLockedWrite(req, cacheBlockMask);
113 }
114
115 virtual void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) {}
116 virtual void
117 handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)
118 {
119 handleLockedSnoop(pkt, cacheBlockMask);
120 }
121 virtual void handleLockedSnoopHit() {}
122 virtual void
127
128 virtual void globalClearExclusive() {}
129 virtual void
134
135 void
136 serialize(CheckpointOut &cp) const override
137 {
139 }
140
148 virtual int64_t getVectorLengthInBytes() const { return -1; }
149};
150
151} // namespace gem5
152
153#endif // __ARCH_GENERIC_ISA_HH__
virtual int64_t getVectorLengthInBytes() const
This function returns the vector length of the Vector Length Agnostic extension of the ISA.
Definition isa.hh:148
virtual void handleLockedSnoop(ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask)
Definition isa.hh:117
virtual bool inUserMode() const =0
virtual void handleLockedSnoopHit(ExecContext *xc)
Definition isa.hh:123
virtual uint64_t getExecutingAsid() const
Definition isa.hh:87
virtual void resetThread()
Definition isa.hh:91
ThreadContext * tc
Definition isa.hh:68
std::string isaName
Definition isa.hh:72
const RegClasses & regClasses() const
Definition isa.hh:93
RegClasses _regClasses
Definition isa.hh:70
virtual void handleLockedRead(const RequestPtr &req)
Definition isa.hh:97
virtual void setMiscReg(RegIndex idx, RegVal val)=0
virtual RegVal readMiscReg(RegIndex idx)=0
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition isa.hh:136
virtual void handleLockedRead(ExecContext *xc, const RequestPtr &req)
Definition isa.hh:99
virtual void copyRegsFrom(ThreadContext *src)=0
virtual void clear()
Definition isa.hh:76
virtual bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
Definition isa.hh:104
virtual void globalClearExclusive(ExecContext *xc)
Definition isa.hh:130
virtual PCStateBase * newPCState(Addr new_inst_addr=0) const =0
virtual RegVal readMiscRegNoEffect(RegIndex idx) const =0
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition isa.hh:84
const std::string getIsaName() const
Definition isa.hh:94
std::vector< const RegClass * > RegClasses
Definition isa.hh:61
BaseISA(const SimObjectParams &p, const std::string &name)
Definition isa.hh:64
virtual void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
Definition isa.hh:115
virtual void handleLockedSnoopHit()
Definition isa.hh:121
virtual void setThreadContext(ThreadContext *_tc)
Definition isa.hh:85
virtual void setMiscRegNoEffect(RegIndex idx, RegVal val)=0
virtual void globalClearExclusive()
Definition isa.hh:128
virtual bool handleLockedWrite(ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask)
Definition isa.hh:109
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Abstract superclass for simulation objects.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
STL vector class.
Definition stl.hh:37
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
Bitfield< 0 > p
Bitfield< 63 > val
Definition misc.hh:804
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint16_t RegIndex
Definition types.hh:176
std::shared_ptr< Request > RequestPtr
Definition request.hh:94
uint64_t RegVal
Definition types.hh:173
std::ostream CheckpointOut
Definition serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
Declaration of the Packet class.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
#define SERIALIZE_SCALAR(scalar)
Definition serialize.hh:568

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