gem5  v21.1.0.2
pseudo_inst.hh
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40 
41 #ifndef __SIM_PSEUDO_INST_HH__
42 #define __SIM_PSEUDO_INST_HH__
43 
44 #include <gem5/asm/generic/m5ops.h>
45 
46 #include "base/bitfield.hh"
47 #include "base/compiler.hh"
48 #include "base/logging.hh"
49 #include "base/trace.hh"
50 #include "base/types.hh" // For Tick and Addr data types.
51 #include "cpu/thread_context.hh"
52 #include "debug/PseudoInst.hh"
53 #include "sim/guest_abi.hh"
54 
55 namespace gem5
56 {
57 
58 GEM5_DEPRECATED_NAMESPACE(PseudoInst, pseudo_inst);
59 namespace pseudo_inst
60 {
61 
62 static inline void
63 decodeAddrOffset(Addr offset, uint8_t &func)
64 {
65  func = bits(offset, 15, 8);
66 }
67 
68 void arm(ThreadContext *tc);
69 void quiesce(ThreadContext *tc);
70 void quiesceSkip(ThreadContext *tc);
71 void quiesceNs(ThreadContext *tc, uint64_t ns);
72 void quiesceCycles(ThreadContext *tc, uint64_t cycles);
73 uint64_t quiesceTime(ThreadContext *tc);
74 uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len,
75  uint64_t offset);
76 uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len,
77  uint64_t offset, Addr filenameAddr);
78 void loadsymbol(ThreadContext *xc);
79 void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
80 uint64_t initParam(ThreadContext *xc, uint64_t key_str1, uint64_t key_str2);
81 uint64_t rpns(ThreadContext *tc);
82 void wakeCPU(ThreadContext *tc, uint64_t cpuid);
83 void m5exit(ThreadContext *tc, Tick delay);
84 void m5fail(ThreadContext *tc, Tick delay, uint64_t code);
85 uint64_t m5sum(ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c,
86  uint64_t d, uint64_t e, uint64_t f);
87 void resetstats(ThreadContext *tc, Tick delay, Tick period);
88 void dumpstats(ThreadContext *tc, Tick delay, Tick period);
89 void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
90 void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
91 void debugbreak(ThreadContext *tc);
92 void switchcpu(ThreadContext *tc);
93 void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
94 void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
95 void m5Syscall(ThreadContext *tc);
96 void togglesync(ThreadContext *tc);
98 
112 template <typename ABI, bool store_ret>
113 bool
114 pseudoInstWork(ThreadContext *tc, uint8_t func, uint64_t &result)
115 {
116  DPRINTF(PseudoInst, "pseudo_inst::pseudoInst(%i)\n", func);
117 
118  result = 0;
119 
120  switch (func) {
121  case M5OP_ARM:
122  invokeSimcall<ABI>(tc, arm);
123  return true;
124 
125  case M5OP_QUIESCE:
126  invokeSimcall<ABI>(tc, quiesce);
127  return true;
128 
129  case M5OP_QUIESCE_NS:
130  invokeSimcall<ABI>(tc, quiesceNs);
131  return true;
132 
133  case M5OP_QUIESCE_CYCLE:
134  invokeSimcall<ABI>(tc, quiesceCycles);
135  return true;
136 
137  case M5OP_QUIESCE_TIME:
138  result = invokeSimcall<ABI, store_ret>(tc, quiesceTime);
139  return true;
140 
141  case M5OP_RPNS:
142  result = invokeSimcall<ABI, store_ret>(tc, rpns);
143  return true;
144 
145  case M5OP_WAKE_CPU:
146  invokeSimcall<ABI>(tc, wakeCPU);
147  return true;
148 
149  case M5OP_EXIT:
150  invokeSimcall<ABI>(tc, m5exit);
151  return true;
152 
153  case M5OP_FAIL:
154  invokeSimcall<ABI>(tc, m5fail);
155  return true;
156 
157  // M5OP_SUM is for sanity checking the gem5 op interface.
158  case M5OP_SUM:
159  result = invokeSimcall<ABI, store_ret>(tc, m5sum);
160  return true;
161 
162  case M5OP_INIT_PARAM:
163  result = invokeSimcall<ABI, store_ret>(tc, initParam);
164  return true;
165 
166  case M5OP_LOAD_SYMBOL:
167  invokeSimcall<ABI>(tc, loadsymbol);
168  return true;
169 
170  case M5OP_RESET_STATS:
171  invokeSimcall<ABI>(tc, resetstats);
172  return true;
173 
174  case M5OP_DUMP_STATS:
175  invokeSimcall<ABI>(tc, dumpstats);
176  return true;
177 
178  case M5OP_DUMP_RESET_STATS:
179  invokeSimcall<ABI>(tc, dumpresetstats);
180  return true;
181 
182  case M5OP_CHECKPOINT:
183  invokeSimcall<ABI>(tc, m5checkpoint);
184  return true;
185 
186  case M5OP_WRITE_FILE:
187  result = invokeSimcall<ABI, store_ret>(tc, writefile);
188  return true;
189 
190  case M5OP_READ_FILE:
191  result = invokeSimcall<ABI, store_ret>(tc, readfile);
192  return true;
193 
194  case M5OP_DEBUG_BREAK:
195  invokeSimcall<ABI>(tc, debugbreak);
196  return true;
197 
198  case M5OP_SWITCH_CPU:
199  invokeSimcall<ABI>(tc, switchcpu);
200  return true;
201 
202  case M5OP_ADD_SYMBOL:
203  invokeSimcall<ABI>(tc, addsymbol);
204  return true;
205 
206  case M5OP_PANIC:
207  panic("M5 panic instruction called at %s\n", tc->pcState());
208 
209  case M5OP_WORK_BEGIN:
210  invokeSimcall<ABI>(tc, workbegin);
211  return true;
212 
213  case M5OP_WORK_END:
214  invokeSimcall<ABI>(tc, workend);
215  return true;
216 
217  case M5OP_RESERVED1:
218  case M5OP_RESERVED2:
219  case M5OP_RESERVED3:
220  case M5OP_RESERVED4:
221  case M5OP_RESERVED5:
222  warn("Unimplemented m5 op (%#x)\n", func);
223  return false;
224 
225  /* dist-gem5 functions */
226  case M5OP_DIST_TOGGLE_SYNC:
227  invokeSimcall<ABI>(tc, togglesync);
228  return true;
229 
230  case M5OP_WORKLOAD:
231  invokeSimcall<ABI>(tc, triggerWorkloadEvent);
232  return true;
233 
234  default:
235  warn("Unhandled m5 op: %#x\n", func);
236  return false;
237  }
238 }
239 
240 template <typename ABI, bool store_ret=false>
241 bool
242 pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
243 {
244  return pseudoInstWork<ABI, store_ret>(tc, func, result);
245 }
246 
247 template <typename ABI, bool store_ret=true>
248 bool
249 pseudoInst(ThreadContext *tc, uint8_t func)
250 {
251  uint64_t result;
252  return pseudoInstWork<ABI, store_ret>(tc, func, result);
253 }
254 
255 } // namespace pseudo_inst
256 } // namespace gem5
257 
258 #endif // __SIM_PSEUDO_INST_HH__
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:444
gem5::pseudo_inst::pseudoInst
bool pseudoInst(ThreadContext *tc, uint8_t func, uint64_t &result)
Definition: pseudo_inst.hh:242
warn
#define warn(...)
Definition: logging.hh:245
gem5::pseudo_inst::workend
void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid)
Definition: pseudo_inst.cc:540
gem5::pseudo_inst::quiesceNs
void quiesceNs(ThreadContext *tc, uint64_t ns)
Definition: pseudo_inst.cc:129
gem5::MipsISA::cpuid
Bitfield< 28, 21 > cpuid
Definition: dt_constants.hh:95
gem5::pseudo_inst::quiesceTime
uint64_t quiesceTime(ThreadContext *tc)
Definition: pseudo_inst.cc:143
gem5::pseudo_inst::debugbreak
void debugbreak(ThreadContext *tc)
Definition: pseudo_inst.cc:444
gem5::pseudo_inst::switchcpu
void switchcpu(ThreadContext *tc)
Definition: pseudo_inst.cc:451
gem5::ArmISA::f
Bitfield< 6 > f
Definition: misc_types.hh:67
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
gem5::ArmISA::ns
Bitfield< 0 > ns
Definition: misc_types.hh:331
gem5::pseudo_inst::quiesce
void quiesce(ThreadContext *tc)
Definition: pseudo_inst.cc:115
gem5::pseudo_inst::rpns
uint64_t rpns(ThreadContext *tc)
Definition: pseudo_inst.cc:152
gem5::pseudo_inst::triggerWorkloadEvent
void triggerWorkloadEvent(ThreadContext *tc)
Definition: pseudo_inst.cc:465
gem5::pseudo_inst::m5Syscall
void m5Syscall(ThreadContext *tc)
gem5::pseudo_inst::loadsymbol
void loadsymbol(ThreadContext *tc)
Definition: pseudo_inst.cc:204
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
gem5::pseudo_inst::writefile
uint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset, Addr filename_addr)
Definition: pseudo_inst.cc:398
gem5::pseudo_inst::wakeCPU
void wakeCPU(ThreadContext *tc, uint64_t cpuid)
Definition: pseudo_inst.cc:159
bitfield.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:63
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::pseudo_inst::m5checkpoint
void m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
Definition: pseudo_inst.cc:346
gem5::pseudo_inst::readfile
uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
Definition: pseudo_inst.cc:360
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::pseudo_inst::m5fail
void m5fail(ThreadContext *tc, Tick delay, uint64_t code)
Definition: pseudo_inst.cc:196
gem5::pseudo_inst::decodeAddrOffset
static void decodeAddrOffset(Addr offset, uint8_t &func)
Definition: pseudo_inst.hh:63
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::pseudo_inst::quiesceSkip
void quiesceSkip(ThreadContext *tc)
Definition: pseudo_inst.cc:122
gem5::pseudo_inst::resetstats
void resetstats(ThreadContext *tc, Tick delay, Tick period)
Definition: pseudo_inst.cc:303
gem5::pseudo_inst::arm
void arm(ThreadContext *tc)
Definition: pseudo_inst.cc:105
gem5::pseudo_inst::dumpresetstats
void dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
Definition: pseudo_inst.cc:331
gem5::pseudo_inst::workbegin
void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid)
Definition: pseudo_inst.cc:477
gem5::pseudo_inst::addsymbol
void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
Definition: pseudo_inst.cc:256
types.hh
gem5::pseudo_inst::quiesceCycles
void quiesceCycles(ThreadContext *tc, uint64_t cycles)
Definition: pseudo_inst.cc:136
gem5::pseudo_inst::m5exit
void m5exit(ThreadContext *tc, Tick delay)
Definition: pseudo_inst.cc:176
gem5::pseudo_inst::pseudoInstWork
bool pseudoInstWork(ThreadContext *tc, uint8_t func, uint64_t &result)
Execute a decoded M5 pseudo instruction.
Definition: pseudo_inst.hh:114
guest_abi.hh
logging.hh
gem5::pseudo_inst::m5sum
uint64_t m5sum(ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c, uint64_t d, uint64_t e, uint64_t f)
Definition: pseudo_inst.cc:187
trace.hh
gem5::pseudo_inst::togglesync
void togglesync(ThreadContext *tc)
Definition: pseudo_inst.cc:458
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::pseudo_inst::initParam
uint64_t initParam(ThreadContext *tc, uint64_t key_str1, uint64_t key_str2)
Definition: pseudo_inst.cc:273
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::pseudo_inst::dumpstats
void dumpstats(ThreadContext *tc, Tick delay, Tick period)
Definition: pseudo_inst.cc:317
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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