pseudo_inst.hh File Reference

#include <gem5/asm/generic/m5ops.h>
#include "base/bitfield.hh"
#include "base/compiler.hh"
#include "base/logging.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
#include "debug/PseudoInst.hh"
#include "sim/guest_abi.hh"

Go to the source code of this file.

Classes
struct	gem5::pseudo_inst::GuestAddr
	This struct wrapper for Addr enables m5ops for systems with 32 bit pointer, since it allows to distinguish between address arguments and native C++ types. More...

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
namespace	gem5::pseudo_inst

Functions
static void	gem5::pseudo_inst::decodeAddrOffset (Addr offset, uint8_t &func)
std::ostream &	gem5::pseudo_inst::operator<< (std::ostream &os, const GuestAddr addr)
void	gem5::pseudo_inst::arm (ThreadContext *tc)
void	gem5::pseudo_inst::quiesce (ThreadContext *tc)
void	gem5::pseudo_inst::quiesceSkip (ThreadContext *tc)
void	gem5::pseudo_inst::quiesceNs (ThreadContext *tc, uint64_t ns)
void	gem5::pseudo_inst::quiesceCycles (ThreadContext *tc, uint64_t cycles)
uint64_t	gem5::pseudo_inst::quiesceTime (ThreadContext *tc)
uint64_t	gem5::pseudo_inst::readfile (ThreadContext *tc, GuestAddr vaddr, uint64_t len, uint64_t offset)
uint64_t	gem5::pseudo_inst::writefile (ThreadContext *tc, GuestAddr vaddr, uint64_t len, uint64_t offset, GuestAddr filename_addr)
void	gem5::pseudo_inst::loadsymbol (ThreadContext *tc)
void	gem5::pseudo_inst::addsymbol (ThreadContext *tc, GuestAddr addr, GuestAddr symbolAddr)
uint64_t	gem5::pseudo_inst::initParam (ThreadContext *tc, uint64_t key_str1, uint64_t key_str2)
uint64_t	gem5::pseudo_inst::rpns (ThreadContext *tc)
void	gem5::pseudo_inst::wakeCPU (ThreadContext *tc, uint64_t cpuid)
void	gem5::pseudo_inst::m5exit (ThreadContext *tc, Tick delay)
void	gem5::pseudo_inst::m5fail (ThreadContext *tc, Tick delay, uint64_t code)
uint64_t	gem5::pseudo_inst::m5sum (ThreadContext *tc, uint64_t a, uint64_t b, uint64_t c, uint64_t d, uint64_t e, uint64_t f)
void	gem5::pseudo_inst::resetstats (ThreadContext *tc, Tick delay, Tick period)
void	gem5::pseudo_inst::dumpstats (ThreadContext *tc, Tick delay, Tick period)
void	gem5::pseudo_inst::dumpresetstats (ThreadContext *tc, Tick delay, Tick period)
void	gem5::pseudo_inst::m5checkpoint (ThreadContext *tc, Tick delay, Tick period)
void	gem5::pseudo_inst::debugbreak (ThreadContext *tc)
void	gem5::pseudo_inst::switchcpu (ThreadContext *tc)
void	gem5::pseudo_inst::workbegin (ThreadContext *tc, uint64_t workid, uint64_t threadid)
void	gem5::pseudo_inst::workend (ThreadContext *tc, uint64_t workid, uint64_t threadid)
void	gem5::pseudo_inst::m5Syscall (ThreadContext *tc)
void	gem5::pseudo_inst::togglesync (ThreadContext *tc)
void	gem5::pseudo_inst::triggerWorkloadEvent (ThreadContext *tc)
template<typename ABI , bool store_ret>
bool	gem5::pseudo_inst::pseudoInstWork (ThreadContext *tc, uint8_t func, uint64_t &result)
	Execute a decoded M5 pseudo instruction.
template<typename ABI , bool store_ret = false>
bool	gem5::pseudo_inst::pseudoInst (ThreadContext *tc, uint8_t func, uint64_t &result)
template<typename ABI , bool store_ret = true>
bool	gem5::pseudo_inst::pseudoInst (ThreadContext *tc, uint8_t func)