gem5  v21.1.0.2
aapcs32.hh
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27 
28 #ifndef __ARCH_ARM_AAPCS32_HH__
29 #define __ARCH_ARM_AAPCS32_HH__
30 
31 #include <algorithm>
32 #include <array>
33 #include <type_traits>
34 #include <utility>
35 
36 #include "arch/arm/regs/int.hh"
37 #include "arch/arm/utility.hh"
38 #include "base/intmath.hh"
39 #include "cpu/thread_context.hh"
40 #include "mem/port_proxy.hh"
41 #include "sim/guest_abi.hh"
42 #include "sim/proxy_ptr.hh"
43 
44 namespace gem5
45 {
46 
47 class ThreadContext;
48 
49 struct Aapcs32
50 {
51  struct State
52  {
53  bool stackUsed=false; // Whether anything has been put on the stack.
54 
55  int ncrn=0; // Next general purpose register number.
56  Addr nsaa; // Next stacked argument address.
57 
58  // The maximum allowed general purpose register number.
59  static const int MAX_CRN = 3;
60 
62 
63  explicit State(const ThreadContext *tc) :
64  nsaa(tc->readIntReg(ArmISA::INTREG_SPX))
65  {}
66  };
67 };
68 
69 GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
70 namespace guest_abi
71 {
72 
73 /*
74  * Composite Types
75  */
76 
77 template <typename T, typename Enabled=void>
78 struct IsAapcs32Composite : public std::false_type {};
79 
80 template <typename T>
81 struct IsAapcs32Composite<T, typename std::enable_if_t<
82  (std::is_array<T>::value ||
83  std::is_class<T>::value ||
84  std::is_union<T>::value) &&
85  // VarArgs is technically a composite type, but it's not a normal argument.
86  !IsVarArgs<T>::value
87  >> : public std::true_type
88 {};
89 
90 // Homogeneous Aggregates
91 // These *should* be any aggregate type which has only one type of member, but
92 // we can't actually detect that or manipulate that with templates. Instead,
93 // we approximate that by detecting only arrays with that property.
94 
95 template <typename T, std::size_t count, typename Enabled=void>
97 
98 template <typename T>
99 struct IsAapcs32HomogeneousAggregate : public std::false_type {};
100 
101 template <typename E, size_t N>
102 struct IsAapcs32HomogeneousAggregate<E[N]> : public std::true_type {};
103 
105 {
106  template <typename T>
107  static T
109  {
110  state.stackUsed = true;
111 
112  // The alignment is the larger of 4 or the natural alignment of T.
113  size_t align = std::max<size_t>(4, alignof(T));
114  // Increase the size to the next multiple of 4.
115  size_t size = roundUp(sizeof(T), 4);
116 
117  // Align the stack.
118  state.nsaa = roundUp(state.nsaa, align);
119 
120  // Extract the value from it.
121  ConstVPtr<T> val(state.nsaa, tc);
122 
123  // Move the nsaa past this argument.
124  state.nsaa += size;
125 
126  // Return the value we extracted.
127  return gtoh(*val, ArmISA::byteOrder(tc));
128  }
129 };
130 
131 
132 /*
133  * Integer arguments and return values.
134  */
135 
136 template <typename Integer>
137 struct Result<Aapcs32, Integer, typename std::enable_if_t<
138  std::is_integral<Integer>::value && (sizeof(Integer) < sizeof(uint32_t))>>
139 {
140  static void
141  store(ThreadContext *tc, const Integer &i)
142  {
143  uint32_t val = std::is_signed<Integer>::value ?
144  sext<sizeof(Integer) * 8>(i) : i;
145  tc->setIntReg(ArmISA::INTREG_R0, val);
146  }
147 };
148 
149 template <typename Integer>
150 struct Result<Aapcs32, Integer, typename std::enable_if_t<
151  std::is_integral<Integer>::value && (sizeof(Integer) == sizeof(uint32_t))>>
152 {
153  static void
154  store(ThreadContext *tc, const Integer &i)
155  {
156  tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)i);
157  }
158 };
159 
160 template <typename Integer>
161 struct Result<Aapcs32, Integer, typename std::enable_if_t<
162  std::is_integral<Integer>::value && (sizeof(Integer) == sizeof(uint64_t))>>
163 {
164  static void
165  store(ThreadContext *tc, const Integer &i)
166  {
167  if (ArmISA::byteOrder(tc) == ByteOrder::little) {
168  tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)(i >> 0));
169  tc->setIntReg(ArmISA::INTREG_R1, (uint32_t)(i >> 32));
170  } else {
171  tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)(i >> 32));
172  tc->setIntReg(ArmISA::INTREG_R1, (uint32_t)(i >> 0));
173  }
174  }
175 };
176 
177 template <typename Integer>
178 struct Argument<Aapcs32, Integer, typename std::enable_if_t<
179  std::is_integral<Integer>::value && (sizeof(Integer) <= sizeof(uint32_t))
180  >> : public Aapcs32ArgumentBase
181 {
182  static Integer
184  {
185  if (state.ncrn <= state.MAX_CRN) {
186  return tc->readIntReg(state.ncrn++);
187  }
188 
189  // Max out the ncrn since we effectively exhausted it.
190  state.ncrn = state.MAX_CRN + 1;
191 
192  return loadFromStack<Integer>(tc, state);
193  }
194 };
195 
196 template <typename Integer>
197 struct Argument<Aapcs32, Integer, typename std::enable_if_t<
198  std::is_integral<Integer>::value && (sizeof(Integer) > sizeof(uint32_t))
199  >> : public Aapcs32ArgumentBase
200 {
201  static Integer
202  get(ThreadContext *tc, Aapcs32::State &state)
203  {
204  if (alignof(Integer) == 8 && (state.ncrn % 2))
205  state.ncrn++;
206 
207  if (sizeof(Integer) == sizeof(uint64_t) &&
208  state.ncrn + 1 <= state.MAX_CRN) {
209  Integer low, high;
210  if (ArmISA::byteOrder(tc) == ByteOrder::little) {
211  low = tc->readIntReg(state.ncrn++) & mask(32);
212  high = tc->readIntReg(state.ncrn++) & mask(32);
213  } else {
214  high = tc->readIntReg(state.ncrn++) & mask(32);
215  low = tc->readIntReg(state.ncrn++) & mask(32);
216  }
217  return low | (high << 32);
218  }
219 
220  // Max out the ncrn since we effectively exhausted it.
221  state.ncrn = state.MAX_CRN + 1;
222 
223  return loadFromStack<Integer>(tc, state);
224  }
225 };
226 
227 
228 /*
229  * Floating point and Short-Vector arguments and return values.
230  */
231 
232 template <typename Float>
233 struct Result<Aapcs32, Float, typename std::enable_if_t<
234  std::is_floating_point<Float>::value>>
235 {
236  static void
237  store(ThreadContext *tc, const Float &f, Aapcs32::State &state)
238  {
239  auto i = floatToBits(f);
240  storeResult<Aapcs32, decltype(i)>(tc, i, state);
241  };
242 };
243 
244 template <typename Float>
245 struct Argument<Aapcs32, Float, typename std::enable_if_t<
246  std::is_floating_point<Float>::value>> : public Aapcs32ArgumentBase
247 {
248  static Float
250  {
251  if (sizeof(Float) == sizeof(uint32_t)) {
252  return bitsToFloat32(
253  getArgument<Aapcs32, uint32_t>(tc, state));
254  } else {
255  return bitsToFloat64(
256  getArgument<Aapcs32, uint64_t>(tc, state));
257  }
258  }
259 };
260 
261 
262 /*
263  * Composite arguments and return values.
264  */
265 
266 template <typename Composite>
267 struct Result<Aapcs32, Composite, typename std::enable_if_t<
268  IsAapcs32Composite<Composite>::value>>
269 {
270  static void
271  store(ThreadContext *tc, const Composite &composite,
272  Aapcs32::State &state)
273  {
274  if (sizeof(Composite) <= sizeof(uint32_t)) {
275  Composite cp = htog(composite, ArmISA::byteOrder(tc));
276  uint32_t val;
277  memcpy((void *)&val, (void *)&cp, sizeof(Composite));
278  val = gtoh(val, ArmISA::byteOrder(tc));
279  tc->setIntReg(ArmISA::INTREG_R0, val);
280  } else {
281  VPtr<Composite> cp(state.retAddr, tc);
282  *cp = htog(composite, ArmISA::byteOrder(tc));
283  }
284  }
285 
286  static void
288  {
289  if (sizeof(Composite) > sizeof(uint32_t))
290  state.retAddr = tc->readIntReg(state.ncrn++);
291  }
292 };
293 
294 template <typename Composite>
295 struct Argument<Aapcs32, Composite, typename std::enable_if_t<
296  IsAapcs32Composite<Composite>::value>> :
297  public Aapcs32ArgumentBase
298 {
299  static Composite
301  {
302  size_t bytes = sizeof(Composite);
303  using Chunk = uint32_t;
304 
305  const int chunk_size = sizeof(Chunk);
306  const int regs = (bytes + chunk_size - 1) / chunk_size;
307 
308  if (bytes <= chunk_size) {
309  if (state.ncrn++ <= state.MAX_CRN) {
310  alignas(alignof(Composite)) uint32_t val =
311  tc->readIntReg(state.ncrn++);
312  val = htog(val, ArmISA::byteOrder(tc));
313  return gtoh(*(Composite *)&val, ArmISA::byteOrder(tc));
314  }
315  }
316 
317  if (alignof(Composite) == 8 && (state.ncrn % 2))
318  state.ncrn++;
319 
320  if (state.ncrn + regs - 1 <= state.MAX_CRN) {
321  alignas(alignof(Composite)) uint8_t buf[bytes];
322  for (int i = 0; i < regs; i++) {
323  Chunk val = tc->readIntReg(state.ncrn++);
324  val = htog(val, ArmISA::byteOrder(tc));
325  size_t to_copy = std::min<size_t>(bytes, chunk_size);
326  memcpy(buf + i * chunk_size, &val, to_copy);
327  bytes -= to_copy;
328  }
329  return gtoh(*(Composite *)buf, ArmISA::byteOrder(tc));
330  }
331 
332  if (!state.stackUsed && state.ncrn <= state.MAX_CRN) {
333  alignas(alignof(Composite)) uint8_t buf[bytes];
334 
335  int offset = 0;
336  while (state.ncrn <= state.MAX_CRN) {
337  Chunk val = tc->readIntReg(state.ncrn++);
338  val = htog(val, ArmISA::byteOrder(tc));
339  size_t to_copy = std::min<size_t>(bytes, chunk_size);
340  memcpy(buf + offset, &val, to_copy);
341  offset += to_copy;
342  bytes -= to_copy;
343  }
344 
345  if (bytes) {
346  tc->getVirtProxy().readBlob(state.nsaa, buf, bytes);
347 
348  state.stackUsed = true;
349  state.nsaa += roundUp(bytes, 4);
350  state.ncrn = state.MAX_CRN + 1;
351  }
352 
353  return gtoh(*(Composite *)buf, ArmISA::byteOrder(tc));
354  }
355 
356  state.ncrn = state.MAX_CRN + 1;
357 
358  return loadFromStack<Composite>(tc, state);
359  }
360 };
361 
362 } // namespace guest_abi
363 
364 
365 /*
366  * VFP ABI variant.
367  */
368 
369 struct Aapcs32Vfp : public Aapcs32
370 {
371  struct State : public Aapcs32::State
372  {
373  bool variadic=false; // Whether this function is variadic.
374 
375  // Whether the various single and double precision registers have
376  // been allocated.
377  std::array<bool, 16> s;
378  std::array<bool, 8> d;
379 
380  explicit State(const ThreadContext *tc) : Aapcs32::State(tc)
381  {
382  s.fill(false);
383  d.fill(false);
384  }
385 
386  int
387  allocate(float, int count)
388  {
389  int last = 0;
390  for (int i = 0; i <= s.size() - count; i++) {
391  if (s[i]) {
392  last = i + 1;
393  continue;
394  }
395  if (i - last + 1 == count) {
396  for (int j = 0; j < count; j++) {
397  s[last + j] = true;
398  d[(last + j) / 2] = true;
399  }
400  return last;
401  }
402  }
403  s.fill(true);
404  d.fill(true);
405  return -1;
406  }
407 
408  int
409  allocate(double, int count)
410  {
411  int last = 0;
412  for (int i = 0; i <= d.size() - count; i++) {
413  if (d[i]) {
414  last = i + 1;
415  continue;
416  }
417  if (i - last + 1 == count) {
418  for (int j = 0; j < count; j++) {
419  d[last + j] = true;
420  s[(last + j) * 2] = true;
421  s[(last + j) * 2 + 1] = true;
422  }
423  return last;
424  }
425  }
426  s.fill(true);
427  d.fill(true);
428  return -1;
429  }
430  };
431 };
432 
433 GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
434 namespace guest_abi
435 {
436 
437 /*
438  * Integer arguments and return values.
439  */
440 
441 template <typename Integer>
442 struct Result<Aapcs32Vfp, Integer, typename std::enable_if_t<
443  std::is_integral<Integer>::value>> : public Result<Aapcs32, Integer>
444 {};
445 
446 template <typename Integer>
447 struct Argument<Aapcs32Vfp, Integer, typename std::enable_if_t<
448  std::is_integral<Integer>::value>> :
449  public Argument<Aapcs32, Integer>
450 {};
451 
452 
453 /*
454  * Floating point arguments and return values.
455  */
456 
457 template <typename Float>
458 struct Result<Aapcs32Vfp, Float, typename std::enable_if_t<
459  std::is_floating_point<Float>::value>>
460 {
461  static void
462  store(ThreadContext *tc, const Float &f, Aapcs32Vfp::State &state)
463  {
464  if (state.variadic) {
465  storeResult<Aapcs32, Float>(tc, f, state);
466  return;
467  }
468 
469  RegId id(VecRegClass, 0);
470  auto reg = tc->readVecReg(id);
471  reg.as<Float>()[0] = f;
472  tc->setVecReg(id, reg);
473  };
474 };
475 
476 template <typename Float>
477 struct Argument<Aapcs32Vfp, Float, typename std::enable_if_t<
478  std::is_floating_point<Float>::value>> : public Aapcs32ArgumentBase
479 {
480  static Float
482  {
483  if (state.variadic)
484  return getArgument<Aapcs32, Float>(tc, state);
485 
486  const int index = state.allocate(Float{}, 1);
487 
488  if (index >= 0) {
489  constexpr int lane_per_reg = 16 / sizeof(Float);
490  const int reg = index / lane_per_reg;
491  const int lane = index % lane_per_reg;
492 
494  auto val = tc->readVecReg(id);
495  return val.as<Float>()[lane];
496  }
497 
498  return loadFromStack<Float>(tc, state);
499  }
500 };
501 
502 
503 /*
504  * Composite arguments and return values which are not Homogeneous Aggregates.
505  */
506 
507 template <typename Composite>
508 struct Result<Aapcs32Vfp, Composite, typename std::enable_if_t<
509  IsAapcs32Composite<Composite>::value &&
510  !IsAapcs32HomogeneousAggregate<Composite>::value>> :
511  public Result<Aapcs32, Composite>
512 {};
513 
514 template <typename Composite>
515 struct Argument<Aapcs32Vfp, Composite, typename std::enable_if_t<
516  IsAapcs32Composite<Composite>::value &&
517  !IsAapcs32HomogeneousAggregate<Composite>::value>> :
518  public Argument<Aapcs32, Composite>
519 {};
520 
521 
522 /*
523  * Homogeneous Aggregate argument and return values.
524  */
525 
526 template <typename T>
527 struct Aapcs32ArrayType { using Type = void; };
528 
529 template <typename E, size_t N>
530 struct Aapcs32ArrayType<E[N]> { using Type = E; };
531 
532 template <typename HA>
533 struct Argument<Aapcs32Vfp, HA, typename std::enable_if_t<
534  IsAapcs32HomogeneousAggregate<HA>::value>> :
535  public Aapcs32ArgumentBase
536 {
537  static bool
539  {
540  using Elem = typename Aapcs32ArrayType<HA>::Type;
541  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
542  return state.variadic || !std::is_floating_point<Elem>::value ||
543  Count > 4;
544  }
545 
546  static HA
548  {
549  using Elem = typename Aapcs32ArrayType<HA>::Type;
550  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
551 
552  if (useBaseABI(state))
553  return getArgument<Aapcs32, HA>(tc, state);
554 
555  const int base = state.allocate(Elem{}, Count);
556  if (base >= 0) {
557  constexpr int lane_per_reg = 16 / sizeof(Elem);
558  HA ha;
559  for (int i = 0; i < Count; i++) {
560  const int index = base + i;
561  const int reg = index / lane_per_reg;
562  const int lane = index % lane_per_reg;
563 
565  auto val = tc->readVecReg(id);
566  ha[i] = val.as<Elem>()[lane];
567  }
568  return ha;
569  }
570 
571  return loadFromStack<HA>(tc, state);
572  }
573 
574  static void
576  {
577  if (useBaseABI(state))
578  return Argument<Aapcs32, HA>::prepare(tc, state);
579  }
580 };
581 
582 template <typename HA>
583 struct Result<Aapcs32Vfp, HA,
584  typename std::enable_if_t<IsAapcs32HomogeneousAggregate<HA>::value>>
585 {
586  static bool
588  {
589  using Elem = typename Aapcs32ArrayType<HA>::Type;
590  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
591  return state.variadic || !std::is_floating_point<Elem>::value ||
592  Count > 4;
593  }
594 
595  static HA
596  store(ThreadContext *tc, const HA &ha, Aapcs32Vfp::State &state)
597  {
598  using Elem = typename Aapcs32ArrayType<HA>::Type;
599  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
600 
601  if (useBaseABI(state)) {
602  storeResult<Aapcs32, HA>(tc, ha, state);
603  return;
604  }
605 
606  constexpr int lane_per_reg = 16 / sizeof(Elem);
607  for (int i = 0; i < Count; i++) {
608  const int reg = i / lane_per_reg;
609  const int lane = i % lane_per_reg;
610 
612  auto val = tc->readVecReg(id);
613  val.as<Elem>()[lane] = ha[i];
614  tc->setVecReg(id, val);
615  }
616  }
617 
618  static void
620  {
621  if (useBaseABI(state))
622  return Result<Aapcs32, HA>::prepare(tc, state);
623  }
624 };
625 
626 
627 /*
628  * Varargs
629  */
630 
631 template <typename ...Types>
632 struct Argument<Aapcs32Vfp, VarArgs<Types...>>
633 {
634  static VarArgs<Types...>
635  get(ThreadContext *tc, typename Aapcs32Vfp::State &state)
636  {
637  state.variadic = true;
638  return getArgument<Aapcs32, VarArgs<Types...>>(tc, state);
639  }
640 };
641 
642 } // namespace guest_abi
643 } // namespace gem5
644 
645 #endif // __ARCH_ARM_AAPCS32_HH__
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::Aapcs32Vfp::State::allocate
int allocate(double, int count)
Definition: aapcs32.hh:409
gem5::Aapcs32Vfp::State::State
State(const ThreadContext *tc)
Definition: aapcs32.hh:380
gem5::bitsToFloat32
static float bitsToFloat32(uint32_t val)
Definition: types.hh:213
gem5::ConstProxyPtr
Definition: proxy_ptr.hh:109
gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32Composite< Composite >::value > >::get
static Composite get(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:300
gem5::guest_abi::getArgument
static Arg getArgument(ThreadContext *tc, typename ABI::State &state)
Definition: layout.hh:170
gem5::Aapcs32Vfp
Definition: aapcs32.hh:369
gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral< Integer >::value &&(sizeof(Integer)==sizeof(uint64_t))> >::store
static void store(ThreadContext *tc, const Integer &i)
Definition: aapcs32.hh:165
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::Aapcs32::State::retAddr
Addr retAddr
Definition: aapcs32.hh:61
gem5::Aapcs32::State
Definition: aapcs32.hh:51
gem5::ArmISA::f
Bitfield< 6 > f
Definition: misc_types.hh:67
gem5::bitsToFloat64
static double bitsToFloat64(uint64_t val)
Definition: types.hh:225
gem5::Aapcs32
Definition: aapcs32.hh:49
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::get
static HA get(ThreadContext *tc, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:547
gem5::ArmISA::byteOrder
ByteOrder byteOrder(const ThreadContext *tc)
Definition: utility.hh:412
proxy_ptr.hh
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::guest_abi::Aapcs32ArgumentBase::loadFromStack
static T loadFromStack(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:108
gem5::Aapcs32Vfp::State::variadic
bool variadic
Definition: aapcs32.hh:373
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Aapcs32Vfp::State::d
std::array< bool, 8 > d
Definition: aapcs32.hh:378
gem5::guest_abi::Aapcs32ArrayType
Definition: aapcs32.hh:527
gem5::Aapcs32::State::ncrn
int ncrn
Definition: aapcs32.hh:55
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32Composite< Composite >::value > >::prepare
static void prepare(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:287
gem5::guest_abi::Result< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::store
static void store(ThreadContext *tc, const Float &f, Aapcs32::State &state)
Definition: aapcs32.hh:237
gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::prepare
static void prepare(ThreadContext *tc, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:575
gem5::Aapcs32::State::State
State(const ThreadContext *tc)
Definition: aapcs32.hh:63
gem5::ThreadContext::readVecReg
virtual const TheISA::VecRegContainer & readVecReg(const RegId &reg) const =0
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::get
static Float get(ThreadContext *tc, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:481
gem5::floatToBits
static uint64_t floatToBits(double val)
Definition: types.hh:209
gem5::high
high
Definition: intmath.hh:176
gem5::guest_abi::IsAapcs32HomogeneousAggregate
Definition: aapcs32.hh:99
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::useBaseABI
static bool useBaseABI(Aapcs32Vfp::State &state)
Definition: aapcs32.hh:587
gem5::ThreadContext::getVirtProxy
virtual PortProxy & getVirtProxy()=0
gem5::guest_abi::enable_if_t< std::is_integral< Integer >::value &&(sizeof(Integer)<=sizeof(uint32_t)) > >::get
static Integer get(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:183
gem5::guest_abi::enable_if_t< std::is_integral< Integer >::value &&(sizeof(Integer)< sizeof(uint32_t))> >::store
static void store(ThreadContext *tc, const Integer &i)
Definition: aapcs32.hh:141
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::guest_abi::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::store
static void store(ThreadContext *tc, const Float &f, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:462
port_proxy.hh
gem5::gtoh
T gtoh(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:194
gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::prepare
static void prepare(ThreadContext *tc, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:619
gem5::Aapcs32Vfp::State::allocate
int allocate(float, int count)
Definition: aapcs32.hh:387
gem5::Aapcs32Vfp::State::s
std::array< bool, 16 > s
Definition: aapcs32.hh:377
gem5::htog
T htog(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:187
gem5::ProxyPtr
Definition: proxy_ptr.hh:238
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::PortProxy::readBlob
void readBlob(Addr addr, void *p, int size) const
Higher level interfaces based on the above.
Definition: port_proxy.hh:182
gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::useBaseABI
static bool useBaseABI(Aapcs32Vfp::State &state)
Definition: aapcs32.hh:538
gem5::guest_abi::Aapcs32ArrayType::Type
void Type
Definition: aapcs32.hh:527
gem5::guest_abi::IsAapcs32Composite
Definition: aapcs32.hh:78
gem5::Aapcs32::State::nsaa
Addr nsaa
Definition: aapcs32.hh:56
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::guest_abi::Argument< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::get
static Float get(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:249
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
utility.hh
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::guest_abi::Argument< Aapcs32Vfp, VarArgs< Types... > >::get
static VarArgs< Types... > get(ThreadContext *tc, typename Aapcs32Vfp::State &state)
Definition: aapcs32.hh:635
gem5::Aapcs32::State::MAX_CRN
static const int MAX_CRN
Definition: aapcs32.hh:59
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32Composite< Composite >::value > >::store
static void store(ThreadContext *tc, const Composite &composite, Aapcs32::State &state)
Definition: aapcs32.hh:271
guest_abi.hh
gem5::X86ISA::E
Bitfield< 31, 0 > E
Definition: int.hh:53
gem5::roundUp
static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::guest_abi::Aapcs32ArgumentBase
Definition: aapcs32.hh:104
gem5::guest_abi::Argument
Definition: definition.hh:99
gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral< Integer >::value &&(sizeof(Integer)==sizeof(uint32_t))> >::store
static void store(ThreadContext *tc, const Integer &i)
Definition: aapcs32.hh:154
gem5::Aapcs32Vfp::State
Definition: aapcs32.hh:371
gem5::guest_abi::VarArgs
Definition: varargs.hh:150
intmath.hh
gem5::guest_abi::Result
Definition: definition.hh:64
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::ha
Bitfield< 39 > ha
Definition: misc_types.hh:543
gem5::ThreadContext::setVecReg
virtual void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val)=0
gem5::guest_abi::Aapcs32ArrayType< E[N]>::Type
E Type
Definition: aapcs32.hh:530
int.hh
gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::store
static HA store(ThreadContext *tc, const HA &ha, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:596
thread_context.hh
gem5::Aapcs32::State::stackUsed
bool stackUsed
Definition: aapcs32.hh:53
gem5::guest_abi::Aapcs32HomogeneousAggregate
T[count] Aapcs32HomogeneousAggregate
Definition: aapcs32.hh:96
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88

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