gem5  v21.2.1.1
aapcs32.hh
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27 
28 #ifndef __ARCH_ARM_AAPCS32_HH__
29 #define __ARCH_ARM_AAPCS32_HH__
30 
31 #include <algorithm>
32 #include <array>
33 #include <type_traits>
34 #include <utility>
35 
36 #include "arch/arm/regs/int.hh"
37 #include "arch/arm/utility.hh"
38 #include "base/intmath.hh"
39 #include "cpu/thread_context.hh"
40 #include "mem/port_proxy.hh"
43 #include "sim/full_system.hh"
44 #include "sim/guest_abi.hh"
45 #include "sim/proxy_ptr.hh"
46 
47 namespace gem5
48 {
49 
50 class ThreadContext;
51 
52 struct Aapcs32
53 {
54  struct State
55  {
56  bool stackUsed=false; // Whether anything has been put on the stack.
57 
58  int ncrn=0; // Next general purpose register number.
59  Addr nsaa; // Next stacked argument address.
60 
61  // The maximum allowed general purpose register number.
62  static const int MAX_CRN = 3;
63 
65 
66  explicit State(const ThreadContext *tc) :
67  nsaa(tc->readIntReg(ArmISA::INTREG_SPX))
68  {}
69  };
70 };
71 
72 GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
73 namespace guest_abi
74 {
75 
76 /*
77  * Composite Types
78  */
79 
80 template <typename T, typename Enabled=void>
81 struct IsAapcs32Composite : public std::false_type {};
82 
83 template <typename T>
84 struct IsAapcs32Composite<T, typename std::enable_if_t<
85  (std::is_array_v<T> || std::is_class_v<T> || std::is_union_v<T>) &&
86  // VarArgs is technically a composite type, but it's not a normal argument.
87  !IsVarArgsV<T>
88  >> : public std::true_type
89 {};
90 
91 template <typename T>
93 
94 // Homogeneous Aggregates
95 // These *should* be any aggregate type which has only one type of member, but
96 // we can't actually detect that or manipulate that with templates. Instead,
97 // we approximate that by detecting only arrays with that property.
98 
99 template <typename T, std::size_t count, typename Enabled=void>
101 
102 template <typename T>
103 struct IsAapcs32HomogeneousAggregate : public std::false_type {};
104 
105 template <typename E, size_t N>
106 struct IsAapcs32HomogeneousAggregate<E[N]> : public std::true_type {};
107 
108 template <typename T>
111 
113 {
114  template <typename T>
115  static T
117  {
118  state.stackUsed = true;
119 
120  // The alignment is the larger of 4 or the natural alignment of T.
121  size_t align = std::max<size_t>(4, alignof(T));
122  // Increase the size to the next multiple of 4.
123  size_t size = roundUp(sizeof(T), 4);
124 
125  // Align the stack.
126  state.nsaa = roundUp(state.nsaa, align);
127 
128  // Extract the value from it.
129  ConstVPtr<T> val(state.nsaa, tc);
130 
131  // Move the nsaa past this argument.
132  state.nsaa += size;
133 
134  // Return the value we extracted.
135  return gtoh(*val, ArmISA::byteOrder(tc));
136  }
137 };
138 
139 
140 /*
141  * Integer arguments and return values.
142  */
143 
144 template <typename Integer>
145 struct Result<Aapcs32, Integer, typename std::enable_if_t<
146  std::is_integral_v<Integer> && (sizeof(Integer) < sizeof(uint32_t))>>
147 {
148  static void
149  store(ThreadContext *tc, const Integer &i)
150  {
151  uint32_t val = std::is_signed_v<Integer> ?
152  sext<sizeof(Integer) * 8>(i) : i;
153  tc->setIntReg(ArmISA::INTREG_R0, val);
154  }
155 };
156 
157 template <typename Integer>
158 struct Result<Aapcs32, Integer, typename std::enable_if_t<
159  std::is_integral_v<Integer> && (sizeof(Integer) == sizeof(uint32_t))>>
160 {
161  static void
162  store(ThreadContext *tc, const Integer &i)
163  {
164  tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)i);
165  }
166 };
167 
168 template <typename Integer>
169 struct Result<Aapcs32, Integer, typename std::enable_if_t<
170  std::is_integral_v<Integer> && (sizeof(Integer) == sizeof(uint64_t))>>
171 {
172  static void
173  store(ThreadContext *tc, const Integer &i)
174  {
175  if (ArmISA::byteOrder(tc) == ByteOrder::little) {
176  tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)(i >> 0));
177  tc->setIntReg(ArmISA::INTREG_R1, (uint32_t)(i >> 32));
178  } else {
179  tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)(i >> 32));
180  tc->setIntReg(ArmISA::INTREG_R1, (uint32_t)(i >> 0));
181  }
182  }
183 };
184 
185 template <typename Integer>
186 struct Argument<Aapcs32, Integer, typename std::enable_if_t<
187  std::is_integral_v<Integer> && (sizeof(Integer) <= sizeof(uint32_t))
188  >> : public Aapcs32ArgumentBase
189 {
190  static Integer
192  {
193  if (state.ncrn <= state.MAX_CRN) {
194  return tc->readIntReg(state.ncrn++);
195  }
196 
197  // Max out the ncrn since we effectively exhausted it.
198  state.ncrn = state.MAX_CRN + 1;
199 
200  return loadFromStack<Integer>(tc, state);
201  }
202 };
203 
204 template <typename Integer>
205 struct Argument<Aapcs32, Integer, typename std::enable_if_t<
206  std::is_integral_v<Integer> && (sizeof(Integer) > sizeof(uint32_t))
207  >> : public Aapcs32ArgumentBase
208 {
209  static Integer
210  get(ThreadContext *tc, Aapcs32::State &state)
211  {
212  if (alignof(Integer) == 8 && (state.ncrn % 2))
213  state.ncrn++;
214 
215  if (sizeof(Integer) == sizeof(uint64_t) &&
216  state.ncrn + 1 <= state.MAX_CRN) {
217  Integer low, high;
218  if (ArmISA::byteOrder(tc) == ByteOrder::little) {
219  low = tc->readIntReg(state.ncrn++) & mask(32);
220  high = tc->readIntReg(state.ncrn++) & mask(32);
221  } else {
222  high = tc->readIntReg(state.ncrn++) & mask(32);
223  low = tc->readIntReg(state.ncrn++) & mask(32);
224  }
225  return low | (high << 32);
226  }
227 
228  // Max out the ncrn since we effectively exhausted it.
229  state.ncrn = state.MAX_CRN + 1;
230 
231  return loadFromStack<Integer>(tc, state);
232  }
233 };
234 
235 
236 /*
237  * Floating point and Short-Vector arguments and return values.
238  */
239 
240 template <typename Float>
241 struct Result<Aapcs32, Float, typename std::enable_if_t<
242  std::is_floating_point_v<Float>>>
243 {
244  static void
245  store(ThreadContext *tc, const Float &f, Aapcs32::State &state)
246  {
247  auto i = floatToBits(f);
248  storeResult<Aapcs32, decltype(i)>(tc, i, state);
249  };
250 };
251 
252 template <typename Float>
253 struct Argument<Aapcs32, Float, typename std::enable_if_t<
254  std::is_floating_point_v<Float>>> : public Aapcs32ArgumentBase
255 {
256  static Float
258  {
259  if (sizeof(Float) == sizeof(uint32_t)) {
260  return bitsToFloat32(
261  getArgument<Aapcs32, uint32_t>(tc, state));
262  } else {
263  return bitsToFloat64(
264  getArgument<Aapcs32, uint64_t>(tc, state));
265  }
266  }
267 };
268 
269 
270 /*
271  * Composite arguments and return values.
272  */
273 
274 template <typename Composite>
275 struct Result<Aapcs32, Composite, typename std::enable_if_t<
276  IsAapcs32CompositeV<Composite>>>
277 {
278  static void
279  store(ThreadContext *tc, const Composite &composite,
280  Aapcs32::State &state)
281  {
282  if (sizeof(Composite) <= sizeof(uint32_t)) {
283  Composite cp = htog(composite, ArmISA::byteOrder(tc));
284  uint32_t val;
285  memcpy((void *)&val, (void *)&cp, sizeof(Composite));
286  val = gtoh(val, ArmISA::byteOrder(tc));
287  tc->setIntReg(ArmISA::INTREG_R0, val);
288  } else {
289  VPtr<Composite> cp(state.retAddr, tc);
290  *cp = htog(composite, ArmISA::byteOrder(tc));
291  }
292  }
293 
294  static void
296  {
297  if (sizeof(Composite) > sizeof(uint32_t))
298  state.retAddr = tc->readIntReg(state.ncrn++);
299  }
300 };
301 
302 template <typename Composite>
303 struct Argument<Aapcs32, Composite, typename std::enable_if_t<
304  IsAapcs32CompositeV<Composite>>> :
305  public Aapcs32ArgumentBase
306 {
307  static Composite
309  {
310  size_t bytes = sizeof(Composite);
311  using Chunk = uint32_t;
312 
313  const int chunk_size = sizeof(Chunk);
314  const int regs = (bytes + chunk_size - 1) / chunk_size;
315 
316  if (bytes <= chunk_size) {
317  if (state.ncrn++ <= state.MAX_CRN) {
318  alignas(alignof(Composite)) uint32_t val =
319  tc->readIntReg(state.ncrn++);
320  val = htog(val, ArmISA::byteOrder(tc));
321  return gtoh(*(Composite *)&val, ArmISA::byteOrder(tc));
322  }
323  }
324 
325  if (alignof(Composite) == 8 && (state.ncrn % 2))
326  state.ncrn++;
327 
328  if (state.ncrn + regs - 1 <= state.MAX_CRN) {
329  alignas(alignof(Composite)) uint8_t buf[bytes];
330  for (int i = 0; i < regs; i++) {
331  Chunk val = tc->readIntReg(state.ncrn++);
332  val = htog(val, ArmISA::byteOrder(tc));
333  size_t to_copy = std::min<size_t>(bytes, chunk_size);
334  memcpy(buf + i * chunk_size, &val, to_copy);
335  bytes -= to_copy;
336  }
337  return gtoh(*(Composite *)buf, ArmISA::byteOrder(tc));
338  }
339 
340  if (!state.stackUsed && state.ncrn <= state.MAX_CRN) {
341  alignas(alignof(Composite)) uint8_t buf[bytes];
342 
343  int offset = 0;
344  while (state.ncrn <= state.MAX_CRN) {
345  Chunk val = tc->readIntReg(state.ncrn++);
346  val = htog(val, ArmISA::byteOrder(tc));
347  size_t to_copy = std::min<size_t>(bytes, chunk_size);
348  memcpy(buf + offset, &val, to_copy);
349  offset += to_copy;
350  bytes -= to_copy;
351  }
352 
353  if (bytes) {
355  SETranslatingPortProxy(tc)).readBlob(
356  state.nsaa, buf, bytes);
357 
358  state.stackUsed = true;
359  state.nsaa += roundUp(bytes, 4);
360  state.ncrn = state.MAX_CRN + 1;
361  }
362 
363  return gtoh(*(Composite *)buf, ArmISA::byteOrder(tc));
364  }
365 
366  state.ncrn = state.MAX_CRN + 1;
367 
368  return loadFromStack<Composite>(tc, state);
369  }
370 };
371 
372 } // namespace guest_abi
373 
374 
375 /*
376  * VFP ABI variant.
377  */
378 
379 struct Aapcs32Vfp : public Aapcs32
380 {
381  struct State : public Aapcs32::State
382  {
383  bool variadic=false; // Whether this function is variadic.
384 
385  // Whether the various single and double precision registers have
386  // been allocated.
387  std::array<bool, 16> s;
388  std::array<bool, 8> d;
389 
390  explicit State(const ThreadContext *tc) : Aapcs32::State(tc)
391  {
392  s.fill(false);
393  d.fill(false);
394  }
395 
396  int
397  allocate(float, int count)
398  {
399  int last = 0;
400  for (int i = 0; i <= s.size() - count; i++) {
401  if (s[i]) {
402  last = i + 1;
403  continue;
404  }
405  if (i - last + 1 == count) {
406  for (int j = 0; j < count; j++) {
407  s[last + j] = true;
408  d[(last + j) / 2] = true;
409  }
410  return last;
411  }
412  }
413  s.fill(true);
414  d.fill(true);
415  return -1;
416  }
417 
418  int
419  allocate(double, int count)
420  {
421  int last = 0;
422  for (int i = 0; i <= d.size() - count; i++) {
423  if (d[i]) {
424  last = i + 1;
425  continue;
426  }
427  if (i - last + 1 == count) {
428  for (int j = 0; j < count; j++) {
429  d[last + j] = true;
430  s[(last + j) * 2] = true;
431  s[(last + j) * 2 + 1] = true;
432  }
433  return last;
434  }
435  }
436  s.fill(true);
437  d.fill(true);
438  return -1;
439  }
440  };
441 };
442 
443 GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
444 namespace guest_abi
445 {
446 
447 /*
448  * Integer arguments and return values.
449  */
450 
451 template <typename Integer>
452 struct Result<Aapcs32Vfp, Integer, typename std::enable_if_t<
453  std::is_integral_v<Integer>>> : public Result<Aapcs32, Integer>
454 {};
455 
456 template <typename Integer>
457 struct Argument<Aapcs32Vfp, Integer, typename std::enable_if_t<
458  std::is_integral_v<Integer>>> : public Argument<Aapcs32, Integer>
459 {};
460 
461 
462 /*
463  * Floating point arguments and return values.
464  */
465 
466 template <typename Float>
467 struct Result<Aapcs32Vfp, Float, typename std::enable_if_t<
468  std::is_floating_point_v<Float>>>
469 {
470  static void
471  store(ThreadContext *tc, const Float &f, Aapcs32Vfp::State &state)
472  {
473  if (state.variadic) {
474  storeResult<Aapcs32, Float>(tc, f, state);
475  return;
476  }
477 
478  auto bytes = floatToBits(f);
479  auto *vec_elems = static_cast<ArmISA::VecElem *>(&bytes);
480  constexpr int chunks = sizeof(Float) / sizeof(ArmISA::VecElem);
481  for (int chunk = 0; chunk < chunks; chunk++) {
482  int reg = chunk / ArmISA::NumVecElemPerVecReg;
483  int elem = chunk % ArmISA::NumVecElemPerVecReg;
484  tc->setVecElem(RegId(VecElemClass, reg, elem), vec_elems[chunk]);
485  }
486  };
487 };
488 
489 template <typename Float>
490 struct Argument<Aapcs32Vfp, Float, typename std::enable_if_t<
491  std::is_floating_point_v<Float>>> : public Aapcs32ArgumentBase
492 {
493  static Float
495  {
496  if (state.variadic)
497  return getArgument<Aapcs32, Float>(tc, state);
498 
499  const int index = state.allocate(Float{}, 1);
500 
501  if (index < 0)
502  return loadFromStack<Float>(tc, state);
503 
504  decltype(floatToBits(Float{})) result;
505  auto *vec_elems = static_cast<ArmISA::VecElem *>(&result);
506 
507  constexpr int chunks = sizeof(Float) / sizeof(ArmISA::VecElem);
508  for (int chunk = 0; chunk < chunks; chunk++) {
509  int reg = chunk / ArmISA::NumVecElemPerVecReg;
510  int elem = chunk % ArmISA::NumVecElemPerVecReg;
511  vec_elems[chunk] = tc->readVecElem(RegId(VecElemClass, reg, elem));
512  }
513 
514  return bitsToFloat(result);
515  }
516 };
517 
518 
519 /*
520  * Composite arguments and return values which are not Homogeneous Aggregates.
521  */
522 
523 template <typename Composite>
524 struct Result<Aapcs32Vfp, Composite, typename std::enable_if_t<
525  IsAapcs32CompositeV<Composite> &&
526  !IsAapcs32HomogeneousAggregateV<Composite>>> :
527  public Result<Aapcs32, Composite>
528 {};
529 
530 template <typename Composite>
531 struct Argument<Aapcs32Vfp, Composite, typename std::enable_if_t<
532  IsAapcs32CompositeV<Composite> &&
533  !IsAapcs32HomogeneousAggregateV<Composite>>> :
534  public Argument<Aapcs32, Composite>
535 {};
536 
537 
538 /*
539  * Homogeneous Aggregate argument and return values.
540  */
541 
542 template <typename T>
543 struct Aapcs32ArrayType { using Type = void; };
544 
545 template <typename E, size_t N>
546 struct Aapcs32ArrayType<E[N]> { using Type = E; };
547 
548 template <typename HA>
549 struct Argument<Aapcs32Vfp, HA, typename std::enable_if_t<
550  IsAapcs32HomogeneousAggregateV<HA>>> :
551  public Aapcs32ArgumentBase
552 {
553  static bool
555  {
556  using Elem = typename Aapcs32ArrayType<HA>::Type;
557  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
558  return state.variadic || !std::is_floating_point_v<Elem> ||
559  Count > 4;
560  }
561 
562  static HA
564  {
565  using Elem = typename Aapcs32ArrayType<HA>::Type;
566  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
567 
568  if (useBaseABI(state))
569  return getArgument<Aapcs32, HA>(tc, state);
570 
571  const int base = state.allocate(Elem{}, Count);
572  if (base >= 0) {
573  constexpr int lane_per_reg = 16 / sizeof(Elem);
574  HA ha;
575  for (int i = 0; i < Count; i++) {
576  const int index = base + i;
577  const int reg = index / lane_per_reg;
578  const int lane = index % lane_per_reg;
579 
581  auto val = tc->readVecReg(id);
582  ha[i] = val.as<Elem>()[lane];
583  }
584  return ha;
585  }
586 
587  return loadFromStack<HA>(tc, state);
588  }
589 
590  static void
592  {
593  if (useBaseABI(state))
594  return Argument<Aapcs32, HA>::prepare(tc, state);
595  }
596 };
597 
598 template <typename HA>
599 struct Result<Aapcs32Vfp, HA,
600  typename std::enable_if_t<IsAapcs32HomogeneousAggregateV<HA>>>
601 {
602  static bool
604  {
605  using Elem = typename Aapcs32ArrayType<HA>::Type;
606  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
607  return state.variadic || !std::is_floating_point_v<Elem> ||
608  Count > 4;
609  }
610 
611  static HA
612  store(ThreadContext *tc, const HA &ha, Aapcs32Vfp::State &state)
613  {
614  using Elem = typename Aapcs32ArrayType<HA>::Type;
615  constexpr size_t Count = sizeof(HA) / sizeof(Elem);
616 
617  if (useBaseABI(state)) {
618  storeResult<Aapcs32, HA>(tc, ha, state);
619  return;
620  }
621 
622  constexpr int lane_per_reg = 16 / sizeof(Elem);
623  for (int i = 0; i < Count; i++) {
624  const int reg = i / lane_per_reg;
625  const int lane = i % lane_per_reg;
626 
628  auto val = tc->readVecReg(id);
629  val.as<Elem>()[lane] = ha[i];
630  tc->setVecReg(id, val);
631  }
632  }
633 
634  static void
636  {
637  if (useBaseABI(state))
638  return Result<Aapcs32, HA>::prepare(tc, state);
639  }
640 };
641 
642 
643 /*
644  * Varargs
645  */
646 
647 template <typename ...Types>
648 struct Argument<Aapcs32Vfp, VarArgs<Types...>>
649 {
650  static VarArgs<Types...>
651  get(ThreadContext *tc, typename Aapcs32Vfp::State &state)
652  {
653  state.variadic = true;
654  return getArgument<Aapcs32, VarArgs<Types...>>(tc, state);
655  }
656 };
657 
658 } // namespace guest_abi
659 } // namespace gem5
660 
661 #endif // __ARCH_ARM_AAPCS32_HH__
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::Aapcs32Vfp::State::allocate
int allocate(double, int count)
Definition: aapcs32.hh:419
gem5::Aapcs32Vfp::State::State
State(const ThreadContext *tc)
Definition: aapcs32.hh:390
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::SETranslatingPortProxy
Definition: se_translating_port_proxy.hh:49
gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::prepare
static void prepare(ThreadContext *tc, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:635
gem5::bitsToFloat32
static float bitsToFloat32(uint32_t val)
Definition: types.hh:213
gem5::ConstProxyPtr
Definition: proxy_ptr.hh:109
gem5::guest_abi::getArgument
static Arg getArgument(ThreadContext *tc, typename ABI::State &state)
Definition: layout.hh:171
gem5::Aapcs32Vfp
Definition: aapcs32.hh:379
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::Aapcs32::State::retAddr
Addr retAddr
Definition: aapcs32.hh:64
gem5::guest_abi::Argument< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::get
static Float get(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:257
gem5::Aapcs32::State
Definition: aapcs32.hh:54
gem5::ArmISA::f
Bitfield< 6 > f
Definition: misc_types.hh:68
gem5::bitsToFloat64
static double bitsToFloat64(uint64_t val)
Definition: types.hh:225
gem5::guest_abi::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=sizeof(uint32_t)) > >::get
static Integer get(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:191
gem5::Aapcs32
Definition: aapcs32.hh:52
translating_port_proxy.hh
gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::prepare
static void prepare(ThreadContext *tc, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:591
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
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static void store(ThreadContext *tc, const Integer &i)
Definition: aapcs32.hh:149
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static void store(ThreadContext *tc, const Composite &composite, Aapcs32::State &state)
Definition: aapcs32.hh:279
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ByteOrder byteOrder(const ThreadContext *tc)
Definition: utility.hh:365
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Bitfield< 51, 12 > base
Definition: pagetable.hh:141
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static T loadFromStack(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:116
gem5::Aapcs32Vfp::State::variadic
bool variadic
Definition: aapcs32.hh:383
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Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::Aapcs32Vfp::State::d
std::array< bool, 8 > d
Definition: aapcs32.hh:388
gem5::guest_abi::Aapcs32ArrayType
Definition: aapcs32.hh:543
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int ncrn
Definition: aapcs32.hh:58
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void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
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constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> >::store
static void store(ThreadContext *tc, const Integer &i)
Definition: aapcs32.hh:173
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This proxy attempts to translate virtual addresses using the TLBs.
Definition: translating_port_proxy.hh:60
gem5::guest_abi::Result< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store
static void store(ThreadContext *tc, const Float &f, Aapcs32::State &state)
Definition: aapcs32.hh:245
gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store
static HA store(ThreadContext *tc, const HA &ha, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:612
gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get
static Composite get(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:308
gem5::Aapcs32::State::State
State(const ThreadContext *tc)
Definition: aapcs32.hh:66
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virtual const TheISA::VecRegContainer & readVecReg(const RegId &reg) const =0
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Bitfield< 24 > j
Definition: misc_types.hh:57
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static uint64_t floatToBits(double val)
Definition: types.hh:209
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high
Definition: intmath.hh:176
gem5::guest_abi::IsAapcs32HomogeneousAggregate
Definition: aapcs32.hh:103
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ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get
static HA get(ThreadContext *tc, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:563
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count
Definition: misc.hh:709
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T gtoh(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:194
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static bool useBaseABI(Aapcs32Vfp::State &state)
Definition: aapcs32.hh:554
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int allocate(float, int count)
Definition: aapcs32.hh:397
gem5::Aapcs32Vfp::State::s
std::array< bool, 16 > s
Definition: aapcs32.hh:387
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T htog(T value, ByteOrder guest_byte_order)
Definition: byteswap.hh:187
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Definition: proxy_ptr.hh:238
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static double bitsToFloat(uint64_t val)
Definition: types.hh:236
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Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::guest_abi::Aapcs32ArrayType::Type
void Type
Definition: aapcs32.hh:543
gem5::guest_abi::IsAapcs32Composite
Definition: aapcs32.hh:81
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Addr nsaa
Definition: aapcs32.hh:59
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uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
utility.hh
full_system.hh
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virtual RegVal readVecElem(const RegId &reg) const =0
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Definition: types.hh:92
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static VarArgs< Types... > get(ThreadContext *tc, typename Aapcs32Vfp::State &state)
Definition: aapcs32.hh:651
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bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::Aapcs32::State::MAX_CRN
static const int MAX_CRN
Definition: aapcs32.hh:62
gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::prepare
static void prepare(ThreadContext *tc, Aapcs32::State &state)
Definition: aapcs32.hh:295
gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::get
static Float get(ThreadContext *tc, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:494
gem5::guest_abi::IsAapcs32HomogeneousAggregateV
constexpr bool IsAapcs32HomogeneousAggregateV
Definition: aapcs32.hh:109
gem5::guest_abi::IsAapcs32CompositeV
constexpr bool IsAapcs32CompositeV
Definition: aapcs32.hh:92
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
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uint32_t VecElem
Definition: vec.hh:60
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gem5::X86ISA::E
Bitfield< 31, 0 > E
Definition: int.hh:53
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static constexpr T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:260
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virtual void setVecElem(const RegId &reg, RegVal val)=0
gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::useBaseABI
static bool useBaseABI(Aapcs32Vfp::State &state)
Definition: aapcs32.hh:603
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::guest_abi::Aapcs32ArgumentBase
Definition: aapcs32.hh:112
gem5::guest_abi::Argument
Definition: definition.hh:99
se_translating_port_proxy.hh
gem5::Aapcs32Vfp::State
Definition: aapcs32.hh:381
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::guest_abi::VarArgs
Definition: varargs.hh:150
intmath.hh
gem5::guest_abi::Result
Definition: definition.hh:64
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ArmISA::ha
Bitfield< 39 > ha
Definition: misc_types.hh:544
gem5::ThreadContext::setVecReg
virtual void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val)=0
gem5::guest_abi::Aapcs32ArrayType< E[N]>::Type
E Type
Definition: aapcs32.hh:546
int.hh
thread_context.hh
gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint32_t))> >::store
static void store(ThreadContext *tc, const Integer &i)
Definition: aapcs32.hh:162
gem5::Aapcs32::State::stackUsed
bool stackUsed
Definition: aapcs32.hh:56
gem5::guest_abi::Aapcs32HomogeneousAggregate
T[count] Aapcs32HomogeneousAggregate
Definition: aapcs32.hh:100
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::guest_abi::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store
static void store(ThreadContext *tc, const Float &f, Aapcs32Vfp::State &state)
Definition: aapcs32.hh:471

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